arch/powerpc/platforms/powernv/eeh-powernv.c

   1 /*
   2  * The file intends to implement the platform dependent EEH operations on
   3  * powernv platform. Actually, the powernv was created in order to fully
   4  * hypervisor support.
   5  *
   6  * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/atomic.h>
  15 #include <linux/debugfs.h>
  16 #include <linux/delay.h>
  17 #include <linux/export.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/list.h>
  21 #include <linux/msi.h>
  22 #include <linux/of.h>
  23 #include <linux/pci.h>
  24 #include <linux/proc_fs.h>
  25 #include <linux/rbtree.h>
  26 #include <linux/sched.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/spinlock.h>
  29
  30 #include <asm/eeh.h>
  31 #include <asm/eeh_event.h>
  32 #include <asm/firmware.h>
  33 #include <asm/io.h>
  34 #include <asm/iommu.h>
  35 #include <asm/machdep.h>
  36 #include <asm/msi_bitmap.h>
  37 #include <asm/opal.h>
  38 #include <asm/ppc-pci.h>
  39
  40 #include "powernv.h"
  41 #include "pci.h"
  42
  43 static bool pnv_eeh_nb_init = false;
  44 static int eeh_event_irq = -EINVAL;
  45
  46 static int pnv_eeh_init(void)
  47 {
  48         struct pci_controller *hose;
  49         struct pnv_phb *phb;
  50
  51         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
  52                 pr_warn("%s: OPAL is required !\n",
  53                         __func__);
  54                 return -EINVAL;
  55         }
  56
  57         /* Set probe mode */
  58         eeh_add_flag(EEH_PROBE_MODE_DEV);
  59
  60         /*
  61          * P7IOC blocks PCI config access to frozen PE, but PHB3
  62          * doesn't do that. So we have to selectively enable I/O
  63          * prior to collecting error log.
  64          */
  65         list_for_each_entry(hose, &hose_list, list_node) {
  66                 phb = hose->private_data;
  67
  68                 if (phb->model == PNV_PHB_MODEL_P7IOC)
  69                         eeh_add_flag(EEH_ENABLE_IO_FOR_LOG);
  70
  71                 /*
  72                  * PE#0 should be regarded as valid by EEH core
  73                  * if it's not the reserved one. Currently, we
  74                  * have the reserved PE#255 and PE#127 for PHB3
  75                  * and P7IOC separately. So we should regard
  76                  * PE#0 as valid for PHB3 and P7IOC.
  77                  */
  78                 if (phb->ioda.reserved_pe != 0)
  79                         eeh_add_flag(EEH_VALID_PE_ZERO);
  80
  81                 break;
  82         }
  83
  84         return 0;
  85 }
  86
  87 static irqreturn_t pnv_eeh_event(int irq, void *data)
  88 {
  89         /*
  90          * We simply send a special EEH event if EEH has been
  91          * enabled. We don't care about EEH events until we've
  92          * finished processing the outstanding ones. Event processing
  93          * gets unmasked in next_error() if EEH is enabled.
  94          */
  95         disable_irq_nosync(irq);
  96
  97         if (eeh_enabled())
  98                 eeh_send_failure_event(NULL);
  99
 100         return IRQ_HANDLED;
 101 }
 102
 103 #ifdef CONFIG_DEBUG_FS
 104 static ssize_t pnv_eeh_ei_write(struct file *filp,
 105                                 const char __user *user_buf,
 106                                 size_t count, loff_t *ppos)
 107 {
 108         struct pci_controller *hose = filp->private_data;
 109         struct eeh_dev *edev;
 110         struct eeh_pe *pe;
 111         int pe_no, type, func;
 112         unsigned long addr, mask;
 113         char buf[50];
 114         int ret;
 115
 116         if (!eeh_ops || !eeh_ops->err_inject)
 117                 return -ENXIO;
 118
 119         /* Copy over argument buffer */
 120         ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
 121         if (!ret)
 122                 return -EFAULT;
 123
 124         /* Retrieve parameters */
 125         ret = sscanf(buf, "%x:%x:%x:%lx:%lx",
 126                      &pe_no, &type, &func, &addr, &mask);
 127         if (ret != 5)
 128                 return -EINVAL;
 129
 130         /* Retrieve PE */
 131         edev = kzalloc(sizeof(*edev), GFP_KERNEL);
 132         if (!edev)
 133                 return -ENOMEM;
 134         edev->phb = hose;
 135         edev->pe_config_addr = pe_no;
 136         pe = eeh_pe_get(edev);
 137         kfree(edev);
 138         if (!pe)
 139                 return -ENODEV;
 140
 141         /* Do error injection */
 142         ret = eeh_ops->err_inject(pe, type, func, addr, mask);
 143         return ret < 0 ? ret : count;
 144 }
 145
 146 static const struct file_operations pnv_eeh_ei_fops = {
 147         .open   = simple_open,
 148         .llseek = no_llseek,
 149         .write  = pnv_eeh_ei_write,
 150 };
 151
 152 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val)
 153 {
 154         struct pci_controller *hose = data;
 155         struct pnv_phb *phb = hose->private_data;
 156
 157         out_be64(phb->regs + offset, val);
 158         return 0;
 159 }
 160
 161 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val)
 162 {
 163         struct pci_controller *hose = data;
 164         struct pnv_phb *phb = hose->private_data;
 165
 166         *val = in_be64(phb->regs + offset);
 167         return 0;
 168 }
 169
 170 static int pnv_eeh_outb_dbgfs_set(void *data, u64 val)
 171 {
 172         return pnv_eeh_dbgfs_set(data, 0xD10, val);
 173 }
 174
 175 static int pnv_eeh_outb_dbgfs_get(void *data, u64 *val)
 176 {
 177         return pnv_eeh_dbgfs_get(data, 0xD10, val);
 178 }
 179
 180 static int pnv_eeh_inbA_dbgfs_set(void *data, u64 val)
 181 {
 182         return pnv_eeh_dbgfs_set(data, 0xD90, val);
 183 }
 184
 185 static int pnv_eeh_inbA_dbgfs_get(void *data, u64 *val)
 186 {
 187         return pnv_eeh_dbgfs_get(data, 0xD90, val);
 188 }
 189
 190 static int pnv_eeh_inbB_dbgfs_set(void *data, u64 val)
 191 {
 192         return pnv_eeh_dbgfs_set(data, 0xE10, val);
 193 }
 194
 195 static int pnv_eeh_inbB_dbgfs_get(void *data, u64 *val)
 196 {
 197         return pnv_eeh_dbgfs_get(data, 0xE10, val);
 198 }
 199
 200 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_outb_dbgfs_ops, pnv_eeh_outb_dbgfs_get,
 201                         pnv_eeh_outb_dbgfs_set, "0x%llx\n");
 202 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_inbA_dbgfs_ops, pnv_eeh_inbA_dbgfs_get,
 203                         pnv_eeh_inbA_dbgfs_set, "0x%llx\n");
 204 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_inbB_dbgfs_ops, pnv_eeh_inbB_dbgfs_get,
 205                         pnv_eeh_inbB_dbgfs_set, "0x%llx\n");
 206 #endif /* CONFIG_DEBUG_FS */
 207
 208 /**
 209  * pnv_eeh_post_init - EEH platform dependent post initialization
 210  *
 211  * EEH platform dependent post initialization on powernv. When
 212  * the function is called, the EEH PEs and devices should have
 213  * been built. If the I/O cache staff has been built, EEH is
 214  * ready to supply service.
 215  */
 216 static int pnv_eeh_post_init(void)
 217 {
 218         struct pci_controller *hose;
 219         struct pnv_phb *phb;
 220         int ret = 0;
 221
 222         /* Register OPAL event notifier */
 223         if (!pnv_eeh_nb_init) {
 224                 eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR));
 225                 if (eeh_event_irq < 0) {
 226                         pr_err("%s: Can't register OPAL event interrupt (%d)\n",
 227                                __func__, eeh_event_irq);
 228                         return eeh_event_irq;
 229                 }
 230
 231                 ret = request_irq(eeh_event_irq, pnv_eeh_event,
 232                                 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL);
 233                 if (ret < 0) {
 234                         irq_dispose_mapping(eeh_event_irq);
 235                         pr_err("%s: Can't request OPAL event interrupt (%d)\n",
 236                                __func__, eeh_event_irq);
 237                         return ret;
 238                 }
 239
 240                 pnv_eeh_nb_init = true;
 241         }
 242
 243         if (!eeh_enabled())
 244                 disable_irq(eeh_event_irq);
 245
 246         list_for_each_entry(hose, &hose_list, list_node) {
 247                 phb = hose->private_data;
 248
 249                 /*
 250                  * If EEH is enabled, we're going to rely on that.
 251                  * Otherwise, we restore to conventional mechanism
 252                  * to clear frozen PE during PCI config access.
 253                  */
 254                 if (eeh_enabled())
 255                         phb->flags |= PNV_PHB_FLAG_EEH;
 256                 else
 257                         phb->flags &= ~PNV_PHB_FLAG_EEH;
 258
 259                 /* Create debugfs entries */
 260 #ifdef CONFIG_DEBUG_FS
 261                 if (phb->has_dbgfs || !phb->dbgfs)
 262                         continue;
 263
 264                 phb->has_dbgfs = 1;
 265                 debugfs_create_file("err_injct", 0200,
 266                                     phb->dbgfs, hose,
 267                                     &pnv_eeh_ei_fops);
 268
 269                 debugfs_create_file("err_injct_outbound", 0600,
 270                                     phb->dbgfs, hose,
 271                                     &pnv_eeh_outb_dbgfs_ops);
 272                 debugfs_create_file("err_injct_inboundA", 0600,
 273                                     phb->dbgfs, hose,
 274                                     &pnv_eeh_inbA_dbgfs_ops);
 275                 debugfs_create_file("err_injct_inboundB", 0600,
 276                                     phb->dbgfs, hose,
 277                                     &pnv_eeh_inbB_dbgfs_ops);
 278 #endif /* CONFIG_DEBUG_FS */
 279         }
 280
 281         return ret;
 282 }
 283
 284 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap)
 285 {
 286         int pos = PCI_CAPABILITY_LIST;
 287         int cnt = 48;   /* Maximal number of capabilities */
 288         u32 status, id;
 289
 290         if (!pdn)
 291                 return 0;
 292
 293         /* Check if the device supports capabilities */
 294         pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status);
 295         if (!(status & PCI_STATUS_CAP_LIST))
 296                 return 0;
 297
 298         while (cnt--) {
 299                 pnv_pci_cfg_read(pdn, pos, 1, &pos);
 300                 if (pos < 0x40)
 301                         break;
 302
 303                 pos &= ~3;
 304                 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
 305                 if (id == 0xff)
 306                         break;
 307
 308                 /* Found */
 309                 if (id == cap)
 310                         return pos;
 311
 312                 /* Next one */
 313                 pos += PCI_CAP_LIST_NEXT;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap)
 320 {
 321         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
 322         u32 header;
 323         int pos = 256, ttl = (4096 - 256) / 8;
 324
 325         if (!edev || !edev->pcie_cap)
 326                 return 0;
 327         if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
 328                 return 0;
 329         else if (!header)
 330                 return 0;
 331
 332         while (ttl-- > 0) {
 333                 if (PCI_EXT_CAP_ID(header) == cap && pos)
 334                         return pos;
 335
 336                 pos = PCI_EXT_CAP_NEXT(header);
 337                 if (pos < 256)
 338                         break;
 339
 340                 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
 341                         break;
 342         }
 343
 344         return 0;
 345 }
 346
 347 /**
 348  * pnv_eeh_probe - Do probe on PCI device
 349  * @pdn: PCI device node
 350  * @data: unused
 351  *
 352  * When EEH module is installed during system boot, all PCI devices
 353  * are checked one by one to see if it supports EEH. The function
 354  * is introduced for the purpose. By default, EEH has been enabled
 355  * on all PCI devices. That's to say, we only need do necessary
 356  * initialization on the corresponding eeh device and create PE
 357  * accordingly.
 358  *
 359  * It's notable that's unsafe to retrieve the EEH device through
 360  * the corresponding PCI device. During the PCI device hotplug, which
 361  * was possiblly triggered by EEH core, the binding between EEH device
 362  * and the PCI device isn't built yet.
 363  */
 364 static void *pnv_eeh_probe(struct pci_dn *pdn, void *data)
 365 {
 366         struct pci_controller *hose = pdn->phb;
 367         struct pnv_phb *phb = hose->private_data;
 368         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
 369         uint32_t pcie_flags;
 370         int ret;
 371
 372         /*
 373          * When probing the root bridge, which doesn't have any
 374          * subordinate PCI devices. We don't have OF node for
 375          * the root bridge. So it's not reasonable to continue
 376          * the probing.
 377          */
 378         if (!edev || edev->pe)
 379                 return NULL;
 380
 381         /* Skip for PCI-ISA bridge */
 382         if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
 383                 return NULL;
 384
 385         /* Initialize eeh device */
 386         edev->class_code = pdn->class_code;
 387         edev->mode      &= 0xFFFFFF00;
 388         edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
 389         edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
 390         edev->aer_cap  = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
 391         if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
 392                 edev->mode |= EEH_DEV_BRIDGE;
 393                 if (edev->pcie_cap) {
 394                         pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
 395                                          2, &pcie_flags);
 396                         pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
 397                         if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
 398                                 edev->mode |= EEH_DEV_ROOT_PORT;
 399                         else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
 400                                 edev->mode |= EEH_DEV_DS_PORT;
 401                 }
 402         }
 403
 404         edev->config_addr    = (pdn->busno << 8) | (pdn->devfn);
 405         edev->pe_config_addr = phb->ioda.pe_rmap[edev->config_addr];
 406
 407         /* Create PE */
 408         ret = eeh_add_to_parent_pe(edev);
 409         if (ret) {
 410                 pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%d)\n",
 411                         __func__, hose->global_number, pdn->busno,
 412                         PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret);
 413                 return NULL;
 414         }
 415
 416         /*
 417          * If the PE contains any one of following adapters, the
 418          * PCI config space can't be accessed when dumping EEH log.
 419          * Otherwise, we will run into fenced PHB caused by shortage
 420          * of outbound credits in the adapter. The PCI config access
 421          * should be blocked until PE reset. MMIO access is dropped
 422          * by hardware certainly. In order to drop PCI config requests,
 423          * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which
 424          * will be checked in the backend for PE state retrival. If
 425          * the PE becomes frozen for the first time and the flag has
 426          * been set for the PE, we will set EEH_PE_CFG_BLOCKED for
 427          * that PE to block its config space.
 428          *
 429          * Broadcom Austin 4-ports NICs (14e4:1657)
 430          * Broadcom Shiner 4-ports 1G NICs (14e4:168a)
 431          * Broadcom Shiner 2-ports 10G NICs (14e4:168e)
 432          */
 433         if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
 434              pdn->device_id == 0x1657) ||
 435             (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
 436              pdn->device_id == 0x168a) ||
 437             (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
 438              pdn->device_id == 0x168e))
 439                 edev->pe->state |= EEH_PE_CFG_RESTRICTED;
 440
 441         /*
 442          * Cache the PE primary bus, which can't be fetched when
 443          * full hotplug is in progress. In that case, all child
 444          * PCI devices of the PE are expected to be removed prior
 445          * to PE reset.
 446          */
 447         if (!edev->pe->bus)
 448                 edev->pe->bus = pci_find_bus(hose->global_number,
 449                                              pdn->busno);
 450
 451         /*
 452          * Enable EEH explicitly so that we will do EEH check
 453          * while accessing I/O stuff
 454          */
 455         eeh_add_flag(EEH_ENABLED);
 456
 457         /* Save memory bars */
 458         eeh_save_bars(edev);
 459
 460         return NULL;
 461 }
 462
 463 /**
 464  * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
 465  * @pe: EEH PE
 466  * @option: operation to be issued
 467  *
 468  * The function is used to control the EEH functionality globally.
 469  * Currently, following options are support according to PAPR:
 470  * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
 471  */
 472 static int pnv_eeh_set_option(struct eeh_pe *pe, int option)
 473 {
 474         struct pci_controller *hose = pe->phb;
 475         struct pnv_phb *phb = hose->private_data;
 476         bool freeze_pe = false;
 477         int opt;
 478         s64 rc;
 479
 480         switch (option) {
 481         case EEH_OPT_DISABLE:
 482                 return -EPERM;
 483         case EEH_OPT_ENABLE:
 484                 return 0;
 485         case EEH_OPT_THAW_MMIO:
 486                 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO;
 487                 break;
 488         case EEH_OPT_THAW_DMA:
 489                 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA;
 490                 break;
 491         case EEH_OPT_FREEZE_PE:
 492                 freeze_pe = true;
 493                 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL;
 494                 break;
 495         default:
 496                 pr_warn("%s: Invalid option %d\n", __func__, option);
 497                 return -EINVAL;
 498         }
 499
 500         /* Freeze master and slave PEs if PHB supports compound PEs */
 501         if (freeze_pe) {
 502                 if (phb->freeze_pe) {
 503                         phb->freeze_pe(phb, pe->addr);
 504                         return 0;
 505                 }
 506
 507                 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt);
 508                 if (rc != OPAL_SUCCESS) {
 509                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 510                                 __func__, rc, phb->hose->global_number,
 511                                 pe->addr);
 512                         return -EIO;
 513                 }
 514
 515                 return 0;
 516         }
 517
 518         /* Unfreeze master and slave PEs if PHB supports */
 519         if (phb->unfreeze_pe)
 520                 return phb->unfreeze_pe(phb, pe->addr, opt);
 521
 522         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt);
 523         if (rc != OPAL_SUCCESS) {
 524                 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n",
 525                         __func__, rc, option, phb->hose->global_number,
 526                         pe->addr);
 527                 return -EIO;
 528         }
 529
 530         return 0;
 531 }
 532
 533 /**
 534  * pnv_eeh_get_pe_addr - Retrieve PE address
 535  * @pe: EEH PE
 536  *
 537  * Retrieve the PE address according to the given tranditional
 538  * PCI BDF (Bus/Device/Function) address.
 539  */
 540 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe)
 541 {
 542         return pe->addr;
 543 }
 544
 545 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe)
 546 {
 547         struct pnv_phb *phb = pe->phb->private_data;
 548         s64 rc;
 549
 550         rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,
 551                                          PNV_PCI_DIAG_BUF_SIZE);
 552         if (rc != OPAL_SUCCESS)
 553                 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n",
 554                         __func__, rc, pe->phb->global_number);
 555 }
 556
 557 static int pnv_eeh_get_phb_state(struct eeh_pe *pe)
 558 {
 559         struct pnv_phb *phb = pe->phb->private_data;
 560         u8 fstate;
 561         __be16 pcierr;
 562         s64 rc;
 563         int result = 0;
 564
 565         rc = opal_pci_eeh_freeze_status(phb->opal_id,
 566                                         pe->addr,
 567                                         &fstate,
 568                                         &pcierr,
 569                                         NULL);
 570         if (rc != OPAL_SUCCESS) {
 571                 pr_warn("%s: Failure %lld getting PHB#%x state\n",
 572                         __func__, rc, phb->hose->global_number);
 573                 return EEH_STATE_NOT_SUPPORT;
 574         }
 575
 576         /*
 577          * Check PHB state. If the PHB is frozen for the
 578          * first time, to dump the PHB diag-data.
 579          */
 580         if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) {
 581                 result = (EEH_STATE_MMIO_ACTIVE  |
 582                           EEH_STATE_DMA_ACTIVE   |
 583                           EEH_STATE_MMIO_ENABLED |
 584                           EEH_STATE_DMA_ENABLED);
 585         } else if (!(pe->state & EEH_PE_ISOLATED)) {
 586                 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
 587                 pnv_eeh_get_phb_diag(pe);
 588
 589                 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
 590                         pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
 591         }
 592
 593         return result;
 594 }
 595
 596 static int pnv_eeh_get_pe_state(struct eeh_pe *pe)
 597 {
 598         struct pnv_phb *phb = pe->phb->private_data;
 599         u8 fstate;
 600         __be16 pcierr;
 601         s64 rc;
 602         int result;
 603
 604         /*
 605          * We don't clobber hardware frozen state until PE
 606          * reset is completed. In order to keep EEH core
 607          * moving forward, we have to return operational
 608          * state during PE reset.
 609          */
 610         if (pe->state & EEH_PE_RESET) {
 611                 result = (EEH_STATE_MMIO_ACTIVE  |
 612                           EEH_STATE_DMA_ACTIVE   |
 613                           EEH_STATE_MMIO_ENABLED |
 614                           EEH_STATE_DMA_ENABLED);
 615                 return result;
 616         }
 617
 618         /*
 619          * Fetch PE state from hardware. If the PHB
 620          * supports compound PE, let it handle that.
 621          */
 622         if (phb->get_pe_state) {
 623                 fstate = phb->get_pe_state(phb, pe->addr);
 624         } else {
 625                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 626                                                 pe->addr,
 627                                                 &fstate,
 628                                                 &pcierr,
 629                                                 NULL);
 630                 if (rc != OPAL_SUCCESS) {
 631                         pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n",
 632                                 __func__, rc, phb->hose->global_number,
 633                                 pe->addr);
 634                         return EEH_STATE_NOT_SUPPORT;
 635                 }
 636         }
 637
 638         /* Figure out state */
 639         switch (fstate) {
 640         case OPAL_EEH_STOPPED_NOT_FROZEN:
 641                 result = (EEH_STATE_MMIO_ACTIVE  |
 642                           EEH_STATE_DMA_ACTIVE   |
 643                           EEH_STATE_MMIO_ENABLED |
 644                           EEH_STATE_DMA_ENABLED);
 645                 break;
 646         case OPAL_EEH_STOPPED_MMIO_FREEZE:
 647                 result = (EEH_STATE_DMA_ACTIVE |
 648                           EEH_STATE_DMA_ENABLED);
 649                 break;
 650         case OPAL_EEH_STOPPED_DMA_FREEZE:
 651                 result = (EEH_STATE_MMIO_ACTIVE |
 652                           EEH_STATE_MMIO_ENABLED);
 653                 break;
 654         case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
 655                 result = 0;
 656                 break;
 657         case OPAL_EEH_STOPPED_RESET:
 658                 result = EEH_STATE_RESET_ACTIVE;
 659                 break;
 660         case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
 661                 result = EEH_STATE_UNAVAILABLE;
 662                 break;
 663         case OPAL_EEH_STOPPED_PERM_UNAVAIL:
 664                 result = EEH_STATE_NOT_SUPPORT;
 665                 break;
 666         default:
 667                 result = EEH_STATE_NOT_SUPPORT;
 668                 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n",
 669                         __func__, phb->hose->global_number,
 670                         pe->addr, fstate);
 671         }
 672
 673         /*
 674          * If PHB supports compound PE, to freeze all
 675          * slave PEs for consistency.
 676          *
 677          * If the PE is switching to frozen state for the
 678          * first time, to dump the PHB diag-data.
 679          */
 680         if (!(result & EEH_STATE_NOT_SUPPORT) &&
 681             !(result & EEH_STATE_UNAVAILABLE) &&
 682             !(result & EEH_STATE_MMIO_ACTIVE) &&
 683             !(result & EEH_STATE_DMA_ACTIVE)  &&
 684             !(pe->state & EEH_PE_ISOLATED)) {
 685                 if (phb->freeze_pe)
 686                         phb->freeze_pe(phb, pe->addr);
 687
 688                 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
 689                 pnv_eeh_get_phb_diag(pe);
 690
 691                 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
 692                         pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
 693         }
 694
 695         return result;
 696 }
 697
 698 /**
 699  * pnv_eeh_get_state - Retrieve PE state
 700  * @pe: EEH PE
 701  * @delay: delay while PE state is temporarily unavailable
 702  *
 703  * Retrieve the state of the specified PE. For IODA-compitable
 704  * platform, it should be retrieved from IODA table. Therefore,
 705  * we prefer passing down to hardware implementation to handle
 706  * it.
 707  */
 708 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)
 709 {
 710         int ret;
 711
 712         if (pe->type & EEH_PE_PHB)
 713                 ret = pnv_eeh_get_phb_state(pe);
 714         else
 715                 ret = pnv_eeh_get_pe_state(pe);
 716
 717         if (!delay)
 718                 return ret;
 719
 720         /*
 721          * If the PE state is temporarily unavailable,
 722          * to inform the EEH core delay for default
 723          * period (1 second)
 724          */
 725         *delay = 0;
 726         if (ret & EEH_STATE_UNAVAILABLE)
 727                 *delay = 1000;
 728
 729         return ret;
 730 }
 731
 732 static s64 pnv_eeh_phb_poll(struct pnv_phb *phb)
 733 {
 734         s64 rc = OPAL_HARDWARE;
 735
 736         while (1) {
 737                 rc = opal_pci_poll(phb->opal_id);
 738                 if (rc <= 0)
 739                         break;
 740
 741                 if (system_state < SYSTEM_RUNNING)
 742                         udelay(1000 * rc);
 743                 else
 744                         msleep(rc);
 745         }
 746
 747         return rc;
 748 }
 749
 750 int pnv_eeh_phb_reset(struct pci_controller *hose, int option)
 751 {
 752         struct pnv_phb *phb = hose->private_data;
 753         s64 rc = OPAL_HARDWARE;
 754
 755         pr_debug("%s: Reset PHB#%x, option=%d\n",
 756                  __func__, hose->global_number, option);
 757
 758         /* Issue PHB complete reset request */
 759         if (option == EEH_RESET_FUNDAMENTAL ||
 760             option == EEH_RESET_HOT)
 761                 rc = opal_pci_reset(phb->opal_id,
 762                                     OPAL_RESET_PHB_COMPLETE,
 763                                     OPAL_ASSERT_RESET);
 764         else if (option == EEH_RESET_DEACTIVATE)
 765                 rc = opal_pci_reset(phb->opal_id,
 766                                     OPAL_RESET_PHB_COMPLETE,
 767                                     OPAL_DEASSERT_RESET);
 768         if (rc < 0)
 769                 goto out;
 770
 771         /*
 772          * Poll state of the PHB until the request is done
 773          * successfully. The PHB reset is usually PHB complete
 774          * reset followed by hot reset on root bus. So we also
 775          * need the PCI bus settlement delay.
 776          */
 777         rc = pnv_eeh_phb_poll(phb);
 778         if (option == EEH_RESET_DEACTIVATE) {
 779                 if (system_state < SYSTEM_RUNNING)
 780                         udelay(1000 * EEH_PE_RST_SETTLE_TIME);
 781                 else
 782                         msleep(EEH_PE_RST_SETTLE_TIME);
 783         }
 784 out:
 785         if (rc != OPAL_SUCCESS)
 786                 return -EIO;
 787
 788         return 0;
 789 }
 790
 791 static int pnv_eeh_root_reset(struct pci_controller *hose, int option)
 792 {
 793         struct pnv_phb *phb = hose->private_data;
 794         s64 rc = OPAL_HARDWARE;
 795
 796         pr_debug("%s: Reset PHB#%x, option=%d\n",
 797                  __func__, hose->global_number, option);
 798
 799         /*
 800          * During the reset deassert time, we needn't care
 801          * the reset scope because the firmware does nothing
 802          * for fundamental or hot reset during deassert phase.
 803          */
 804         if (option == EEH_RESET_FUNDAMENTAL)
 805                 rc = opal_pci_reset(phb->opal_id,
 806                                     OPAL_RESET_PCI_FUNDAMENTAL,
 807                                     OPAL_ASSERT_RESET);
 808         else if (option == EEH_RESET_HOT)
 809                 rc = opal_pci_reset(phb->opal_id,
 810                                     OPAL_RESET_PCI_HOT,
 811                                     OPAL_ASSERT_RESET);
 812         else if (option == EEH_RESET_DEACTIVATE)
 813                 rc = opal_pci_reset(phb->opal_id,
 814                                     OPAL_RESET_PCI_HOT,
 815                                     OPAL_DEASSERT_RESET);
 816         if (rc < 0)
 817                 goto out;
 818
 819         /* Poll state of the PHB until the request is done */
 820         rc = pnv_eeh_phb_poll(phb);
 821         if (option == EEH_RESET_DEACTIVATE)
 822                 msleep(EEH_PE_RST_SETTLE_TIME);
 823 out:
 824         if (rc != OPAL_SUCCESS)
 825                 return -EIO;
 826
 827         return 0;
 828 }
 829
 830 static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option)
 831 {
 832         struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
 833         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
 834         int aer = edev ? edev->aer_cap : 0;
 835         u32 ctrl;
 836
 837         pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n",
 838                  __func__, pci_domain_nr(dev->bus),
 839                  dev->bus->number, option);
 840
 841         switch (option) {
 842         case EEH_RESET_FUNDAMENTAL:
 843         case EEH_RESET_HOT:
 844                 /* Don't report linkDown event */
 845                 if (aer) {
 846                         eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
 847                                              4, &ctrl);
 848                         ctrl |= PCI_ERR_UNC_SURPDN;
 849                         eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
 850                                               4, ctrl);
 851                 }
 852
 853                 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
 854                 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
 855                 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
 856
 857                 msleep(EEH_PE_RST_HOLD_TIME);
 858                 break;
 859         case EEH_RESET_DEACTIVATE:
 860                 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
 861                 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 862                 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
 863
 864                 msleep(EEH_PE_RST_SETTLE_TIME);
 865
 866                 /* Continue reporting linkDown event */
 867                 if (aer) {
 868                         eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
 869                                              4, &ctrl);
 870                         ctrl &= ~PCI_ERR_UNC_SURPDN;
 871                         eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
 872                                               4, ctrl);
 873                 }
 874
 875                 break;
 876         }
 877
 878         return 0;
 879 }
 880
 881 void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
 882 {
 883         struct pci_controller *hose;
 884
 885         if (pci_is_root_bus(dev->bus)) {
 886                 hose = pci_bus_to_host(dev->bus);
 887                 pnv_eeh_root_reset(hose, EEH_RESET_HOT);
 888                 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
 889         } else {
 890                 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT);
 891                 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
 892         }
 893 }
 894
 895 /**
 896  * pnv_eeh_reset - Reset the specified PE
 897  * @pe: EEH PE
 898  * @option: reset option
 899  *
 900  * Do reset on the indicated PE. For PCI bus sensitive PE,
 901  * we need to reset the parent p2p bridge. The PHB has to
 902  * be reinitialized if the p2p bridge is root bridge. For
 903  * PCI device sensitive PE, we will try to reset the device
 904  * through FLR. For now, we don't have OPAL APIs to do HARD
 905  * reset yet, so all reset would be SOFT (HOT) reset.
 906  */
 907 static int pnv_eeh_reset(struct eeh_pe *pe, int option)
 908 {
 909         struct pci_controller *hose = pe->phb;
 910         struct pci_bus *bus;
 911         int ret;
 912
 913         /*
 914          * For PHB reset, we always have complete reset. For those PEs whose
 915          * primary bus derived from root complex (root bus) or root port
 916          * (usually bus#1), we apply hot or fundamental reset on the root port.
 917          * For other PEs, we always have hot reset on the PE primary bus.
 918          *
 919          * Here, we have different design to pHyp, which always clear the
 920          * frozen state during PE reset. However, the good idea here from
 921          * benh is to keep frozen state before we get PE reset done completely
 922          * (until BAR restore). With the frozen state, HW drops illegal IO
 923          * or MMIO access, which can incur recrusive frozen PE during PE
 924          * reset. The side effect is that EEH core has to clear the frozen
 925          * state explicitly after BAR restore.
 926          */
 927         if (pe->type & EEH_PE_PHB) {
 928                 ret = pnv_eeh_phb_reset(hose, option);
 929         } else {
 930                 struct pnv_phb *phb;
 931                 s64 rc;
 932
 933                 /*
 934                  * The frozen PE might be caused by PAPR error injection
 935                  * registers, which are expected to be cleared after hitting
 936                  * frozen PE as stated in the hardware spec. Unfortunately,
 937                  * that's not true on P7IOC. So we have to clear it manually
 938                  * to avoid recursive EEH errors during recovery.
 939                  */
 940                 phb = hose->private_data;
 941                 if (phb->model == PNV_PHB_MODEL_P7IOC &&
 942                     (option == EEH_RESET_HOT ||
 943                     option == EEH_RESET_FUNDAMENTAL)) {
 944                         rc = opal_pci_reset(phb->opal_id,
 945                                             OPAL_RESET_PHB_ERROR,
 946                                             OPAL_ASSERT_RESET);
 947                         if (rc != OPAL_SUCCESS) {
 948                                 pr_warn("%s: Failure %lld clearing "
 949                                         "error injection registers\n",
 950                                         __func__, rc);
 951                                 return -EIO;
 952                         }
 953                 }
 954
 955                 bus = eeh_pe_bus_get(pe);
 956                 if (pci_is_root_bus(bus) ||
 957                         pci_is_root_bus(bus->parent))
 958                         ret = pnv_eeh_root_reset(hose, option);
 959                 else
 960                         ret = pnv_eeh_bridge_reset(bus->self, option);
 961         }
 962
 963         return ret;
 964 }
 965
 966 /**
 967  * pnv_eeh_wait_state - Wait for PE state
 968  * @pe: EEH PE
 969  * @max_wait: maximal period in millisecond
 970  *
 971  * Wait for the state of associated PE. It might take some time
 972  * to retrieve the PE's state.
 973  */
 974 static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait)
 975 {
 976         int ret;
 977         int mwait;
 978
 979         while (1) {
 980                 ret = pnv_eeh_get_state(pe, &mwait);
 981
 982                 /*
 983                  * If the PE's state is temporarily unavailable,
 984                  * we have to wait for the specified time. Otherwise,
 985                  * the PE's state will be returned immediately.
 986                  */
 987                 if (ret != EEH_STATE_UNAVAILABLE)
 988                         return ret;
 989
 990                 if (max_wait <= 0) {
 991                         pr_warn("%s: Timeout getting PE#%x's state (%d)\n",
 992                                 __func__, pe->addr, max_wait);
 993                         return EEH_STATE_NOT_SUPPORT;
 994                 }
 995
 996                 max_wait -= mwait;
 997                 msleep(mwait);
 998         }
 999
1000         return EEH_STATE_NOT_SUPPORT;
1001 }
1002
1003 /**
1004  * pnv_eeh_get_log - Retrieve error log
1005  * @pe: EEH PE
1006  * @severity: temporary or permanent error log
1007  * @drv_log: driver log to be combined with retrieved error log
1008  * @len: length of driver log
1009  *
1010  * Retrieve the temporary or permanent error from the PE.
1011  */
1012 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity,
1013                            char *drv_log, unsigned long len)
1014 {
1015         if (!eeh_has_flag(EEH_EARLY_DUMP_LOG))
1016                 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
1017
1018         return 0;
1019 }
1020
1021 /**
1022  * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
1023  * @pe: EEH PE
1024  *
1025  * The function will be called to reconfigure the bridges included
1026  * in the specified PE so that the mulfunctional PE would be recovered
1027  * again.
1028  */
1029 static int pnv_eeh_configure_bridge(struct eeh_pe *pe)
1030 {
1031         return 0;
1032 }
1033
1034 /**
1035  * pnv_pe_err_inject - Inject specified error to the indicated PE
1036  * @pe: the indicated PE
1037  * @type: error type
1038  * @func: specific error type
1039  * @addr: address
1040  * @mask: address mask
1041  *
1042  * The routine is called to inject specified error, which is
1043  * determined by @type and @func, to the indicated PE for
1044  * testing purpose.
1045  */
1046 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
1047                               unsigned long addr, unsigned long mask)
1048 {
1049         struct pci_controller *hose = pe->phb;
1050         struct pnv_phb *phb = hose->private_data;
1051         s64 rc;
1052
1053         if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR &&
1054             type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) {
1055                 pr_warn("%s: Invalid error type %d\n",
1056                         __func__, type);
1057                 return -ERANGE;
1058         }
1059
1060         if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR ||
1061             func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) {
1062                 pr_warn("%s: Invalid error function %d\n",
1063                         __func__, func);
1064                 return -ERANGE;
1065         }
1066
1067         /* Firmware supports error injection ? */
1068         if (!opal_check_token(OPAL_PCI_ERR_INJECT)) {
1069                 pr_warn("%s: Firmware doesn't support error injection\n",
1070                         __func__);
1071                 return -ENXIO;
1072         }
1073
1074         /* Do error injection */
1075         rc = opal_pci_err_inject(phb->opal_id, pe->addr,
1076                                  type, func, addr, mask);
1077         if (rc != OPAL_SUCCESS) {
1078                 pr_warn("%s: Failure %lld injecting error "
1079                         "%d-%d to PHB#%x-PE#%x\n",
1080                         __func__, rc, type, func,
1081                         hose->global_number, pe->addr);
1082                 return -EIO;
1083         }
1084
1085         return 0;
1086 }
1087
1088 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn)
1089 {
1090         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1091
1092         if (!edev || !edev->pe)
1093                 return false;
1094
1095         if (edev->pe->state & EEH_PE_CFG_BLOCKED)
1096                 return true;
1097
1098         return false;
1099 }
1100
1101 static int pnv_eeh_read_config(struct pci_dn *pdn,
1102                                int where, int size, u32 *val)
1103 {
1104         if (!pdn)
1105                 return PCIBIOS_DEVICE_NOT_FOUND;
1106
1107         if (pnv_eeh_cfg_blocked(pdn)) {
1108                 *val = 0xFFFFFFFF;
1109                 return PCIBIOS_SET_FAILED;
1110         }
1111
1112         return pnv_pci_cfg_read(pdn, where, size, val);
1113 }
1114
1115 static int pnv_eeh_write_config(struct pci_dn *pdn,
1116                                 int where, int size, u32 val)
1117 {
1118         if (!pdn)
1119                 return PCIBIOS_DEVICE_NOT_FOUND;
1120
1121         if (pnv_eeh_cfg_blocked(pdn))
1122                 return PCIBIOS_SET_FAILED;
1123
1124         return pnv_pci_cfg_write(pdn, where, size, val);
1125 }
1126
1127 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data)
1128 {
1129         /* GEM */
1130         if (data->gemXfir || data->gemRfir ||
1131             data->gemRirqfir || data->gemMask || data->gemRwof)
1132                 pr_info("  GEM: %016llx %016llx %016llx %016llx %016llx\n",
1133                         be64_to_cpu(data->gemXfir),
1134                         be64_to_cpu(data->gemRfir),
1135                         be64_to_cpu(data->gemRirqfir),
1136                         be64_to_cpu(data->gemMask),
1137                         be64_to_cpu(data->gemRwof));
1138
1139         /* LEM */
1140         if (data->lemFir || data->lemErrMask ||
1141             data->lemAction0 || data->lemAction1 || data->lemWof)
1142                 pr_info("  LEM: %016llx %016llx %016llx %016llx %016llx\n",
1143                         be64_to_cpu(data->lemFir),
1144                         be64_to_cpu(data->lemErrMask),
1145                         be64_to_cpu(data->lemAction0),
1146                         be64_to_cpu(data->lemAction1),
1147                         be64_to_cpu(data->lemWof));
1148 }
1149
1150 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose)
1151 {
1152         struct pnv_phb *phb = hose->private_data;
1153         struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag;
1154         long rc;
1155
1156         rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
1157         if (rc != OPAL_SUCCESS) {
1158                 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n",
1159                         __func__, phb->hub_id, rc);
1160                 return;
1161         }
1162
1163         switch (data->type) {
1164         case OPAL_P7IOC_DIAG_TYPE_RGC:
1165                 pr_info("P7IOC diag-data for RGC\n\n");
1166                 pnv_eeh_dump_hub_diag_common(data);
1167                 if (data->rgc.rgcStatus || data->rgc.rgcLdcp)
1168                         pr_info("  RGC: %016llx %016llx\n",
1169                                 be64_to_cpu(data->rgc.rgcStatus),
1170                                 be64_to_cpu(data->rgc.rgcLdcp));
1171                 break;
1172         case OPAL_P7IOC_DIAG_TYPE_BI:
1173                 pr_info("P7IOC diag-data for BI %s\n\n",
1174                         data->bi.biDownbound ? "Downbound" : "Upbound");
1175                 pnv_eeh_dump_hub_diag_common(data);
1176                 if (data->bi.biLdcp0 || data->bi.biLdcp1 ||
1177                     data->bi.biLdcp2 || data->bi.biFenceStatus)
1178                         pr_info("  BI:  %016llx %016llx %016llx %016llx\n",
1179                                 be64_to_cpu(data->bi.biLdcp0),
1180                                 be64_to_cpu(data->bi.biLdcp1),
1181                                 be64_to_cpu(data->bi.biLdcp2),
1182                                 be64_to_cpu(data->bi.biFenceStatus));
1183                 break;
1184         case OPAL_P7IOC_DIAG_TYPE_CI:
1185                 pr_info("P7IOC diag-data for CI Port %d\n\n",
1186                         data->ci.ciPort);
1187                 pnv_eeh_dump_hub_diag_common(data);
1188                 if (data->ci.ciPortStatus || data->ci.ciPortLdcp)
1189                         pr_info("  CI:  %016llx %016llx\n",
1190                                 be64_to_cpu(data->ci.ciPortStatus),
1191                                 be64_to_cpu(data->ci.ciPortLdcp));
1192                 break;
1193         case OPAL_P7IOC_DIAG_TYPE_MISC:
1194                 pr_info("P7IOC diag-data for MISC\n\n");
1195                 pnv_eeh_dump_hub_diag_common(data);
1196                 break;
1197         case OPAL_P7IOC_DIAG_TYPE_I2C:
1198                 pr_info("P7IOC diag-data for I2C\n\n");
1199                 pnv_eeh_dump_hub_diag_common(data);
1200                 break;
1201         default:
1202                 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n",
1203                         __func__, phb->hub_id, data->type);
1204         }
1205 }
1206
1207 static int pnv_eeh_get_pe(struct pci_controller *hose,
1208                           u16 pe_no, struct eeh_pe **pe)
1209 {
1210         struct pnv_phb *phb = hose->private_data;
1211         struct pnv_ioda_pe *pnv_pe;
1212         struct eeh_pe *dev_pe;
1213         struct eeh_dev edev;
1214
1215         /*
1216          * If PHB supports compound PE, to fetch
1217          * the master PE because slave PE is invisible
1218          * to EEH core.
1219          */
1220         pnv_pe = &phb->ioda.pe_array[pe_no];
1221         if (pnv_pe->flags & PNV_IODA_PE_SLAVE) {
1222                 pnv_pe = pnv_pe->master;
1223                 WARN_ON(!pnv_pe ||
1224                         !(pnv_pe->flags & PNV_IODA_PE_MASTER));
1225                 pe_no = pnv_pe->pe_number;
1226         }
1227
1228         /* Find the PE according to PE# */
1229         memset(&edev, 0, sizeof(struct eeh_dev));
1230         edev.phb = hose;
1231         edev.pe_config_addr = pe_no;
1232         dev_pe = eeh_pe_get(&edev);
1233         if (!dev_pe)
1234                 return -EEXIST;
1235
1236         /* Freeze the (compound) PE */
1237         *pe = dev_pe;
1238         if (!(dev_pe->state & EEH_PE_ISOLATED))
1239                 phb->freeze_pe(phb, pe_no);
1240
1241         /*
1242          * At this point, we're sure the (compound) PE should
1243          * have been frozen. However, we still need poke until
1244          * hitting the frozen PE on top level.
1245          */
1246         dev_pe = dev_pe->parent;
1247         while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) {
1248                 int ret;
1249                 int active_flags = (EEH_STATE_MMIO_ACTIVE |
1250                                     EEH_STATE_DMA_ACTIVE);
1251
1252                 ret = eeh_ops->get_state(dev_pe, NULL);
1253                 if (ret <= 0 || (ret & active_flags) == active_flags) {
1254                         dev_pe = dev_pe->parent;
1255                         continue;
1256                 }
1257
1258                 /* Frozen parent PE */
1259                 *pe = dev_pe;
1260                 if (!(dev_pe->state & EEH_PE_ISOLATED))
1261                         phb->freeze_pe(phb, dev_pe->addr);
1262
1263                 /* Next one */
1264                 dev_pe = dev_pe->parent;
1265         }
1266
1267         return 0;
1268 }
1269
1270 /**
1271  * pnv_eeh_next_error - Retrieve next EEH error to handle
1272  * @pe: Affected PE
1273  *
1274  * The function is expected to be called by EEH core while it gets
1275  * special EEH event (without binding PE). The function calls to
1276  * OPAL APIs for next error to handle. The informational error is
1277  * handled internally by platform. However, the dead IOC, dead PHB,
1278  * fenced PHB and frozen PE should be handled by EEH core eventually.
1279  */
1280 static int pnv_eeh_next_error(struct eeh_pe **pe)
1281 {
1282         struct pci_controller *hose;
1283         struct pnv_phb *phb;
1284         struct eeh_pe *phb_pe, *parent_pe;
1285         __be64 frozen_pe_no;
1286         __be16 err_type, severity;
1287         int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
1288         long rc;
1289         int state, ret = EEH_NEXT_ERR_NONE;
1290
1291         /*
1292          * While running here, it's safe to purge the event queue. The
1293          * event should still be masked.
1294          */
1295         eeh_remove_event(NULL, false);
1296
1297         list_for_each_entry(hose, &hose_list, list_node) {
1298                 /*
1299                  * If the subordinate PCI buses of the PHB has been
1300                  * removed or is exactly under error recovery, we
1301                  * needn't take care of it any more.
1302                  */
1303                 phb = hose->private_data;
1304                 phb_pe = eeh_phb_pe_get(hose);
1305                 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
1306                         continue;
1307
1308                 rc = opal_pci_next_error(phb->opal_id,
1309                                          &frozen_pe_no, &err_type, &severity);
1310                 if (rc != OPAL_SUCCESS) {
1311                         pr_devel("%s: Invalid return value on "
1312                                  "PHB#%x (0x%lx) from opal_pci_next_error",
1313                                  __func__, hose->global_number, rc);
1314                         continue;
1315                 }
1316
1317                 /* If the PHB doesn't have error, stop processing */
1318                 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR ||
1319                     be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) {
1320                         pr_devel("%s: No error found on PHB#%x\n",
1321                                  __func__, hose->global_number);
1322                         continue;
1323                 }
1324
1325                 /*
1326                  * Processing the error. We're expecting the error with
1327                  * highest priority reported upon multiple errors on the
1328                  * specific PHB.
1329                  */
1330                 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
1331                         __func__, be16_to_cpu(err_type),
1332                         be16_to_cpu(severity), be64_to_cpu(frozen_pe_no),
1333                         hose->global_number);
1334                 switch (be16_to_cpu(err_type)) {
1335                 case OPAL_EEH_IOC_ERROR:
1336                         if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) {
1337                                 pr_err("EEH: dead IOC detected\n");
1338                                 ret = EEH_NEXT_ERR_DEAD_IOC;
1339                         } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1340                                 pr_info("EEH: IOC informative error "
1341                                         "detected\n");
1342                                 pnv_eeh_get_and_dump_hub_diag(hose);
1343                                 ret = EEH_NEXT_ERR_NONE;
1344                         }
1345
1346                         break;
1347                 case OPAL_EEH_PHB_ERROR:
1348                         if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) {
1349                                 *pe = phb_pe;
1350                                 pr_err("EEH: dead PHB#%x detected, "
1351                                        "location: %s\n",
1352                                         hose->global_number,
1353                                         eeh_pe_loc_get(phb_pe));
1354                                 ret = EEH_NEXT_ERR_DEAD_PHB;
1355                         } else if (be16_to_cpu(severity) ==
1356                                    OPAL_EEH_SEV_PHB_FENCED) {
1357                                 *pe = phb_pe;
1358                                 pr_err("EEH: Fenced PHB#%x detected, "
1359                                        "location: %s\n",
1360                                         hose->global_number,
1361                                         eeh_pe_loc_get(phb_pe));
1362                                 ret = EEH_NEXT_ERR_FENCED_PHB;
1363                         } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1364                                 pr_info("EEH: PHB#%x informative error "
1365                                         "detected, location: %s\n",
1366                                         hose->global_number,
1367                                         eeh_pe_loc_get(phb_pe));
1368                                 pnv_eeh_get_phb_diag(phb_pe);
1369                                 pnv_pci_dump_phb_diag_data(hose, phb_pe->data);
1370                                 ret = EEH_NEXT_ERR_NONE;
1371                         }
1372
1373                         break;
1374                 case OPAL_EEH_PE_ERROR:
1375                         /*
1376                          * If we can't find the corresponding PE, we
1377                          * just try to unfreeze.
1378                          */
1379                         if (pnv_eeh_get_pe(hose,
1380                                 be64_to_cpu(frozen_pe_no), pe)) {
1381                                 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n",
1382                                         hose->global_number, be64_to_cpu(frozen_pe_no));
1383                                 pr_info("EEH: PHB location: %s\n",
1384                                         eeh_pe_loc_get(phb_pe));
1385
1386                                 /* Dump PHB diag-data */
1387                                 rc = opal_pci_get_phb_diag_data2(phb->opal_id,
1388                                         phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
1389                                 if (rc == OPAL_SUCCESS)
1390                                         pnv_pci_dump_phb_diag_data(hose,
1391                                                         phb->diag.blob);
1392
1393                                 /* Try best to clear it */
1394                                 opal_pci_eeh_freeze_clear(phb->opal_id,
1395                                         frozen_pe_no,
1396                                         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
1397                                 ret = EEH_NEXT_ERR_NONE;
1398                         } else if ((*pe)->state & EEH_PE_ISOLATED ||
1399                                    eeh_pe_passed(*pe)) {
1400                                 ret = EEH_NEXT_ERR_NONE;
1401                         } else {
1402                                 pr_err("EEH: Frozen PE#%x "
1403                                        "on PHB#%x detected\n",
1404                                        (*pe)->addr,
1405                                         (*pe)->phb->global_number);
1406                                 pr_err("EEH: PE location: %s, "
1407                                        "PHB location: %s\n",
1408                                        eeh_pe_loc_get(*pe),
1409                                        eeh_pe_loc_get(phb_pe));
1410                                 ret = EEH_NEXT_ERR_FROZEN_PE;
1411                         }
1412
1413                         break;
1414                 default:
1415                         pr_warn("%s: Unexpected error type %d\n",
1416                                 __func__, be16_to_cpu(err_type));
1417                 }
1418
1419                 /*
1420                  * EEH core will try recover from fenced PHB or
1421                  * frozen PE. In the time for frozen PE, EEH core
1422                  * enable IO path for that before collecting logs,
1423                  * but it ruins the site. So we have to dump the
1424                  * log in advance here.
1425                  */
1426                 if ((ret == EEH_NEXT_ERR_FROZEN_PE  ||
1427                     ret == EEH_NEXT_ERR_FENCED_PHB) &&
1428                     !((*pe)->state & EEH_PE_ISOLATED)) {
1429                         eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1430                         pnv_eeh_get_phb_diag(*pe);
1431
1432                         if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
1433                                 pnv_pci_dump_phb_diag_data((*pe)->phb,
1434                                                            (*pe)->data);
1435                 }
1436
1437                 /*
1438                  * We probably have the frozen parent PE out there and
1439                  * we need have to handle frozen parent PE firstly.
1440                  */
1441                 if (ret == EEH_NEXT_ERR_FROZEN_PE) {
1442                         parent_pe = (*pe)->parent;
1443                         while (parent_pe) {
1444                                 /* Hit the ceiling ? */
1445                                 if (parent_pe->type & EEH_PE_PHB)
1446                                         break;
1447
1448                                 /* Frozen parent PE ? */
1449                                 state = eeh_ops->get_state(parent_pe, NULL);
1450                                 if (state > 0 &&
1451                                     (state & active_flags) != active_flags)
1452                                         *pe = parent_pe;
1453
1454                                 /* Next parent level */
1455                                 parent_pe = parent_pe->parent;
1456                         }
1457
1458                         /* We possibly migrate to another PE */
1459                         eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1460                 }
1461
1462                 /*
1463                  * If we have no errors on the specific PHB or only
1464                  * informative error there, we continue poking it.
1465                  * Otherwise, we need actions to be taken by upper
1466                  * layer.
1467                  */
1468                 if (ret > EEH_NEXT_ERR_INF)
1469                         break;
1470         }
1471
1472         /* Unmask the event */
1473         if (ret == EEH_NEXT_ERR_NONE && eeh_enabled())
1474                 enable_irq(eeh_event_irq);
1475
1476         return ret;
1477 }
1478
1479 static int pnv_eeh_restore_config(struct pci_dn *pdn)
1480 {
1481         struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1482         struct pnv_phb *phb;
1483         s64 ret;
1484
1485         if (!edev)
1486                 return -EEXIST;
1487
1488         phb = edev->phb->private_data;
1489         ret = opal_pci_reinit(phb->opal_id,
1490                               OPAL_REINIT_PCI_DEV, edev->config_addr);
1491         if (ret) {
1492                 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n",
1493                         __func__, edev->config_addr, ret);
1494                 return -EIO;
1495         }
1496
1497         return 0;
1498 }
1499
1500 static struct eeh_ops pnv_eeh_ops = {
1501         .name                   = "powernv",
1502         .init                   = pnv_eeh_init,
1503         .post_init              = pnv_eeh_post_init,
1504         .probe                  = pnv_eeh_probe,
1505         .set_option             = pnv_eeh_set_option,
1506         .get_pe_addr            = pnv_eeh_get_pe_addr,
1507         .get_state              = pnv_eeh_get_state,
1508         .reset                  = pnv_eeh_reset,
1509         .wait_state             = pnv_eeh_wait_state,
1510         .get_log                = pnv_eeh_get_log,
1511         .configure_bridge       = pnv_eeh_configure_bridge,
1512         .err_inject             = pnv_eeh_err_inject,
1513         .read_config            = pnv_eeh_read_config,
1514         .write_config           = pnv_eeh_write_config,
1515         .next_error             = pnv_eeh_next_error,
1516         .restore_config         = pnv_eeh_restore_config
1517 };
1518
1519 /**
1520  * eeh_powernv_init - Register platform dependent EEH operations
1521  *
1522  * EEH initialization on powernv platform. This function should be
1523  * called before any EEH related functions.
1524  */
1525 static int __init eeh_powernv_init(void)
1526 {
1527         int ret = -EINVAL;
1528
1529         eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE);
1530         ret = eeh_ops_register(&pnv_eeh_ops);
1531         if (!ret)
1532                 pr_info("EEH: PowerNV platform initialized\n");
1533         else
1534                 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret);
1535
1536         return ret;
1537 }
1538 machine_early_initcall(powernv, eeh_powernv_init);