arch/powerpc/mm/book3s64/hash_utils.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * PowerPC64 port by Mike Corrigan and Dave Engebretsen
   4  *   {mikejc|engebret}@us.ibm.com
   5  *
   6  *    Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
   7  *
   8  * SMP scalability work:
   9  *    Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
  10  *
  11  *    Module name: htab.c
  12  *
  13  *    Description:
  14  *      PowerPC Hashed Page Table functions
  15  */
  16
  17 #undef DEBUG
  18 #undef DEBUG_LOW
  19
  20 #define pr_fmt(fmt) "hash-mmu: " fmt
  21 #include <linux/spinlock.h>
  22 #include <linux/errno.h>
  23 #include <linux/sched/mm.h>
  24 #include <linux/proc_fs.h>
  25 #include <linux/stat.h>
  26 #include <linux/sysctl.h>
  27 #include <linux/export.h>
  28 #include <linux/ctype.h>
  29 #include <linux/cache.h>
  30 #include <linux/init.h>
  31 #include <linux/signal.h>
  32 #include <linux/memblock.h>
  33 #include <linux/context_tracking.h>
  34 #include <linux/libfdt.h>
  35 #include <linux/pkeys.h>
  36 #include <linux/hugetlb.h>
  37
  38 #include <asm/debugfs.h>
  39 #include <asm/processor.h>
  40 #include <asm/pgtable.h>
  41 #include <asm/mmu.h>
  42 #include <asm/mmu_context.h>
  43 #include <asm/page.h>
  44 #include <asm/types.h>
  45 #include <linux/uaccess.h>
  46 #include <asm/machdep.h>
  47 #include <asm/prom.h>
  48 #include <asm/io.h>
  49 #include <asm/eeh.h>
  50 #include <asm/tlb.h>
  51 #include <asm/cacheflush.h>
  52 #include <asm/cputable.h>
  53 #include <asm/sections.h>
  54 #include <asm/copro.h>
  55 #include <asm/udbg.h>
  56 #include <asm/code-patching.h>
  57 #include <asm/fadump.h>
  58 #include <asm/firmware.h>
  59 #include <asm/tm.h>
  60 #include <asm/trace.h>
  61 #include <asm/ps3.h>
  62 #include <asm/pte-walk.h>
  63 #include <asm/asm-prototypes.h>
  64
  65 #include <mm/mmu_decl.h>
  66
  67 #ifdef DEBUG
  68 #define DBG(fmt...) udbg_printf(fmt)
  69 #else
  70 #define DBG(fmt...)
  71 #endif
  72
  73 #ifdef DEBUG_LOW
  74 #define DBG_LOW(fmt...) udbg_printf(fmt)
  75 #else
  76 #define DBG_LOW(fmt...)
  77 #endif
  78
  79 #define KB (1024)
  80 #define MB (1024*KB)
  81 #define GB (1024L*MB)
  82
  83 /*
  84  * Note:  pte   --> Linux PTE
  85  *        HPTE  --> PowerPC Hashed Page Table Entry
  86  *
  87  * Execution context:
  88  *   htab_initialize is called with the MMU off (of course), but
  89  *   the kernel has been copied down to zero so it can directly
  90  *   reference global data.  At this point it is very difficult
  91  *   to print debug info.
  92  *
  93  */
  94
  95 static unsigned long _SDR1;
  96 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
  97 EXPORT_SYMBOL_GPL(mmu_psize_defs);
  98
  99 u8 hpte_page_sizes[1 << LP_BITS];
 100 EXPORT_SYMBOL_GPL(hpte_page_sizes);
 101
 102 struct hash_pte *htab_address;
 103 unsigned long htab_size_bytes;
 104 unsigned long htab_hash_mask;
 105 EXPORT_SYMBOL_GPL(htab_hash_mask);
 106 int mmu_linear_psize = MMU_PAGE_4K;
 107 EXPORT_SYMBOL_GPL(mmu_linear_psize);
 108 int mmu_virtual_psize = MMU_PAGE_4K;
 109 int mmu_vmalloc_psize = MMU_PAGE_4K;
 110 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 111 int mmu_vmemmap_psize = MMU_PAGE_4K;
 112 #endif
 113 int mmu_io_psize = MMU_PAGE_4K;
 114 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
 115 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
 116 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
 117 u16 mmu_slb_size = 64;
 118 EXPORT_SYMBOL_GPL(mmu_slb_size);
 119 #ifdef CONFIG_PPC_64K_PAGES
 120 int mmu_ci_restrictions;
 121 #endif
 122 #ifdef CONFIG_DEBUG_PAGEALLOC
 123 static u8 *linear_map_hash_slots;
 124 static unsigned long linear_map_hash_count;
 125 static DEFINE_SPINLOCK(linear_map_hash_lock);
 126 #endif /* CONFIG_DEBUG_PAGEALLOC */
 127 struct mmu_hash_ops mmu_hash_ops;
 128 EXPORT_SYMBOL(mmu_hash_ops);
 129
 130 /*
 131  * These are definitions of page sizes arrays to be used when none
 132  * is provided by the firmware.
 133  */
 134
 135 /*
 136  * Fallback (4k pages only)
 137  */
 138 static struct mmu_psize_def mmu_psize_defaults[] = {
 139         [MMU_PAGE_4K] = {
 140                 .shift  = 12,
 141                 .sllp   = 0,
 142                 .penc   = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
 143                 .avpnm  = 0,
 144                 .tlbiel = 0,
 145         },
 146 };
 147
 148 /*
 149  * POWER4, GPUL, POWER5
 150  *
 151  * Support for 16Mb large pages
 152  */
 153 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
 154         [MMU_PAGE_4K] = {
 155                 .shift  = 12,
 156                 .sllp   = 0,
 157                 .penc   = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
 158                 .avpnm  = 0,
 159                 .tlbiel = 1,
 160         },
 161         [MMU_PAGE_16M] = {
 162                 .shift  = 24,
 163                 .sllp   = SLB_VSID_L,
 164                 .penc   = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
 165                             [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
 166                 .avpnm  = 0x1UL,
 167                 .tlbiel = 0,
 168         },
 169 };
 170
 171 /*
 172  * 'R' and 'C' update notes:
 173  *  - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
 174  *     create writeable HPTEs without C set, because the hcall H_PROTECT
 175  *     that we use in that case will not update C
 176  *  - The above is however not a problem, because we also don't do that
 177  *     fancy "no flush" variant of eviction and we use H_REMOVE which will
 178  *     do the right thing and thus we don't have the race I described earlier
 179  *
 180  *    - Under bare metal,  we do have the race, so we need R and C set
 181  *    - We make sure R is always set and never lost
 182  *    - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
 183  */
 184 unsigned long htab_convert_pte_flags(unsigned long pteflags)
 185 {
 186         unsigned long rflags = 0;
 187
 188         /* _PAGE_EXEC -> NOEXEC */
 189         if ((pteflags & _PAGE_EXEC) == 0)
 190                 rflags |= HPTE_R_N;
 191         /*
 192          * PPP bits:
 193          * Linux uses slb key 0 for kernel and 1 for user.
 194          * kernel RW areas are mapped with PPP=0b000
 195          * User area is mapped with PPP=0b010 for read/write
 196          * or PPP=0b011 for read-only (including writeable but clean pages).
 197          */
 198         if (pteflags & _PAGE_PRIVILEGED) {
 199                 /*
 200                  * Kernel read only mapped with ppp bits 0b110
 201                  */
 202                 if (!(pteflags & _PAGE_WRITE)) {
 203                         if (mmu_has_feature(MMU_FTR_KERNEL_RO))
 204                                 rflags |= (HPTE_R_PP0 | 0x2);
 205                         else
 206                                 rflags |= 0x3;
 207                 }
 208         } else {
 209                 if (pteflags & _PAGE_RWX)
 210                         rflags |= 0x2;
 211                 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
 212                         rflags |= 0x1;
 213         }
 214         /*
 215          * We can't allow hardware to update hpte bits. Hence always
 216          * set 'R' bit and set 'C' if it is a write fault
 217          */
 218         rflags |=  HPTE_R_R;
 219
 220         if (pteflags & _PAGE_DIRTY)
 221                 rflags |= HPTE_R_C;
 222         /*
 223          * Add in WIG bits
 224          */
 225
 226         if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
 227                 rflags |= HPTE_R_I;
 228         else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
 229                 rflags |= (HPTE_R_I | HPTE_R_G);
 230         else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
 231                 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
 232         else
 233                 /*
 234                  * Add memory coherence if cache inhibited is not set
 235                  */
 236                 rflags |= HPTE_R_M;
 237
 238         rflags |= pte_to_hpte_pkey_bits(pteflags);
 239         return rflags;
 240 }
 241
 242 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
 243                       unsigned long pstart, unsigned long prot,
 244                       int psize, int ssize)
 245 {
 246         unsigned long vaddr, paddr;
 247         unsigned int step, shift;
 248         int ret = 0;
 249
 250         shift = mmu_psize_defs[psize].shift;
 251         step = 1 << shift;
 252
 253         prot = htab_convert_pte_flags(prot);
 254
 255         DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
 256             vstart, vend, pstart, prot, psize, ssize);
 257
 258         for (vaddr = vstart, paddr = pstart; vaddr < vend;
 259              vaddr += step, paddr += step) {
 260                 unsigned long hash, hpteg;
 261                 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
 262                 unsigned long vpn  = hpt_vpn(vaddr, vsid, ssize);
 263                 unsigned long tprot = prot;
 264
 265                 /*
 266                  * If we hit a bad address return error.
 267                  */
 268                 if (!vsid)
 269                         return -1;
 270                 /* Make kernel text executable */
 271                 if (overlaps_kernel_text(vaddr, vaddr + step))
 272                         tprot &= ~HPTE_R_N;
 273
 274                 /* Make kvm guest trampolines executable */
 275                 if (overlaps_kvm_tmp(vaddr, vaddr + step))
 276                         tprot &= ~HPTE_R_N;
 277
 278                 /*
 279                  * If relocatable, check if it overlaps interrupt vectors that
 280                  * are copied down to real 0. For relocatable kernel
 281                  * (e.g. kdump case) we copy interrupt vectors down to real
 282                  * address 0. Mark that region as executable. This is
 283                  * because on p8 system with relocation on exception feature
 284                  * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
 285                  * in order to execute the interrupt handlers in virtual
 286                  * mode the vector region need to be marked as executable.
 287                  */
 288                 if ((PHYSICAL_START > MEMORY_START) &&
 289                         overlaps_interrupt_vector_text(vaddr, vaddr + step))
 290                                 tprot &= ~HPTE_R_N;
 291
 292                 hash = hpt_hash(vpn, shift, ssize);
 293                 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
 294
 295                 BUG_ON(!mmu_hash_ops.hpte_insert);
 296                 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
 297                                                HPTE_V_BOLTED, psize, psize,
 298                                                ssize);
 299
 300                 if (ret < 0)
 301                         break;
 302
 303 #ifdef CONFIG_DEBUG_PAGEALLOC
 304                 if (debug_pagealloc_enabled() &&
 305                         (paddr >> PAGE_SHIFT) < linear_map_hash_count)
 306                         linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
 307 #endif /* CONFIG_DEBUG_PAGEALLOC */
 308         }
 309         return ret < 0 ? ret : 0;
 310 }
 311
 312 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
 313                       int psize, int ssize)
 314 {
 315         unsigned long vaddr;
 316         unsigned int step, shift;
 317         int rc;
 318         int ret = 0;
 319
 320         shift = mmu_psize_defs[psize].shift;
 321         step = 1 << shift;
 322
 323         if (!mmu_hash_ops.hpte_removebolted)
 324                 return -ENODEV;
 325
 326         for (vaddr = vstart; vaddr < vend; vaddr += step) {
 327                 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
 328                 if (rc == -ENOENT) {
 329                         ret = -ENOENT;
 330                         continue;
 331                 }
 332                 if (rc < 0)
 333                         return rc;
 334         }
 335
 336         return ret;
 337 }
 338
 339 static bool disable_1tb_segments = false;
 340
 341 static int __init parse_disable_1tb_segments(char *p)
 342 {
 343         disable_1tb_segments = true;
 344         return 0;
 345 }
 346 early_param("disable_1tb_segments", parse_disable_1tb_segments);
 347
 348 static int __init htab_dt_scan_seg_sizes(unsigned long node,
 349                                          const char *uname, int depth,
 350                                          void *data)
 351 {
 352         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 353         const __be32 *prop;
 354         int size = 0;
 355
 356         /* We are scanning "cpu" nodes only */
 357         if (type == NULL || strcmp(type, "cpu") != 0)
 358                 return 0;
 359
 360         prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
 361         if (prop == NULL)
 362                 return 0;
 363         for (; size >= 4; size -= 4, ++prop) {
 364                 if (be32_to_cpu(prop[0]) == 40) {
 365                         DBG("1T segment support detected\n");
 366
 367                         if (disable_1tb_segments) {
 368                                 DBG("1T segments disabled by command line\n");
 369                                 break;
 370                         }
 371
 372                         cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
 373                         return 1;
 374                 }
 375         }
 376         cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
 377         return 0;
 378 }
 379
 380 static int __init get_idx_from_shift(unsigned int shift)
 381 {
 382         int idx = -1;
 383
 384         switch (shift) {
 385         case 0xc:
 386                 idx = MMU_PAGE_4K;
 387                 break;
 388         case 0x10:
 389                 idx = MMU_PAGE_64K;
 390                 break;
 391         case 0x14:
 392                 idx = MMU_PAGE_1M;
 393                 break;
 394         case 0x18:
 395                 idx = MMU_PAGE_16M;
 396                 break;
 397         case 0x22:
 398                 idx = MMU_PAGE_16G;
 399                 break;
 400         }
 401         return idx;
 402 }
 403
 404 static int __init htab_dt_scan_page_sizes(unsigned long node,
 405                                           const char *uname, int depth,
 406                                           void *data)
 407 {
 408         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 409         const __be32 *prop;
 410         int size = 0;
 411
 412         /* We are scanning "cpu" nodes only */
 413         if (type == NULL || strcmp(type, "cpu") != 0)
 414                 return 0;
 415
 416         prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
 417         if (!prop)
 418                 return 0;
 419
 420         pr_info("Page sizes from device-tree:\n");
 421         size /= 4;
 422         cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
 423         while(size > 0) {
 424                 unsigned int base_shift = be32_to_cpu(prop[0]);
 425                 unsigned int slbenc = be32_to_cpu(prop[1]);
 426                 unsigned int lpnum = be32_to_cpu(prop[2]);
 427                 struct mmu_psize_def *def;
 428                 int idx, base_idx;
 429
 430                 size -= 3; prop += 3;
 431                 base_idx = get_idx_from_shift(base_shift);
 432                 if (base_idx < 0) {
 433                         /* skip the pte encoding also */
 434                         prop += lpnum * 2; size -= lpnum * 2;
 435                         continue;
 436                 }
 437                 def = &mmu_psize_defs[base_idx];
 438                 if (base_idx == MMU_PAGE_16M)
 439                         cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
 440
 441                 def->shift = base_shift;
 442                 if (base_shift <= 23)
 443                         def->avpnm = 0;
 444                 else
 445                         def->avpnm = (1 << (base_shift - 23)) - 1;
 446                 def->sllp = slbenc;
 447                 /*
 448                  * We don't know for sure what's up with tlbiel, so
 449                  * for now we only set it for 4K and 64K pages
 450                  */
 451                 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
 452                         def->tlbiel = 1;
 453                 else
 454                         def->tlbiel = 0;
 455
 456                 while (size > 0 && lpnum) {
 457                         unsigned int shift = be32_to_cpu(prop[0]);
 458                         int penc  = be32_to_cpu(prop[1]);
 459
 460                         prop += 2; size -= 2;
 461                         lpnum--;
 462
 463                         idx = get_idx_from_shift(shift);
 464                         if (idx < 0)
 465                                 continue;
 466
 467                         if (penc == -1)
 468                                 pr_err("Invalid penc for base_shift=%d "
 469                                        "shift=%d\n", base_shift, shift);
 470
 471                         def->penc[idx] = penc;
 472                         pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
 473                                 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
 474                                 base_shift, shift, def->sllp,
 475                                 def->avpnm, def->tlbiel, def->penc[idx]);
 476                 }
 477         }
 478
 479         return 1;
 480 }
 481
 482 #ifdef CONFIG_HUGETLB_PAGE
 483 /*
 484  * Scan for 16G memory blocks that have been set aside for huge pages
 485  * and reserve those blocks for 16G huge pages.
 486  */
 487 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
 488                                         const char *uname, int depth,
 489                                         void *data) {
 490         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 491         const __be64 *addr_prop;
 492         const __be32 *page_count_prop;
 493         unsigned int expected_pages;
 494         long unsigned int phys_addr;
 495         long unsigned int block_size;
 496
 497         /* We are scanning "memory" nodes only */
 498         if (type == NULL || strcmp(type, "memory") != 0)
 499                 return 0;
 500
 501         /*
 502          * This property is the log base 2 of the number of virtual pages that
 503          * will represent this memory block.
 504          */
 505         page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
 506         if (page_count_prop == NULL)
 507                 return 0;
 508         expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
 509         addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
 510         if (addr_prop == NULL)
 511                 return 0;
 512         phys_addr = be64_to_cpu(addr_prop[0]);
 513         block_size = be64_to_cpu(addr_prop[1]);
 514         if (block_size != (16 * GB))
 515                 return 0;
 516         printk(KERN_INFO "Huge page(16GB) memory: "
 517                         "addr = 0x%lX size = 0x%lX pages = %d\n",
 518                         phys_addr, block_size, expected_pages);
 519         if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
 520                 memblock_reserve(phys_addr, block_size * expected_pages);
 521                 pseries_add_gpage(phys_addr, block_size, expected_pages);
 522         }
 523         return 0;
 524 }
 525 #endif /* CONFIG_HUGETLB_PAGE */
 526
 527 static void mmu_psize_set_default_penc(void)
 528 {
 529         int bpsize, apsize;
 530         for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
 531                 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
 532                         mmu_psize_defs[bpsize].penc[apsize] = -1;
 533 }
 534
 535 #ifdef CONFIG_PPC_64K_PAGES
 536
 537 static bool might_have_hea(void)
 538 {
 539         /*
 540          * The HEA ethernet adapter requires awareness of the
 541          * GX bus. Without that awareness we can easily assume
 542          * we will never see an HEA ethernet device.
 543          */
 544 #ifdef CONFIG_IBMEBUS
 545         return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
 546                 firmware_has_feature(FW_FEATURE_SPLPAR);
 547 #else
 548         return false;
 549 #endif
 550 }
 551
 552 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
 553
 554 static void __init htab_scan_page_sizes(void)
 555 {
 556         int rc;
 557
 558         /* se the invalid penc to -1 */
 559         mmu_psize_set_default_penc();
 560
 561         /* Default to 4K pages only */
 562         memcpy(mmu_psize_defs, mmu_psize_defaults,
 563                sizeof(mmu_psize_defaults));
 564
 565         /*
 566          * Try to find the available page sizes in the device-tree
 567          */
 568         rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
 569         if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
 570                 /*
 571                  * Nothing in the device-tree, but the CPU supports 16M pages,
 572                  * so let's fallback on a known size list for 16M capable CPUs.
 573                  */
 574                 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
 575                        sizeof(mmu_psize_defaults_gp));
 576         }
 577
 578 #ifdef CONFIG_HUGETLB_PAGE
 579         if (!hugetlb_disabled) {
 580                 /* Reserve 16G huge page memory sections for huge pages */
 581                 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
 582         }
 583 #endif /* CONFIG_HUGETLB_PAGE */
 584 }
 585
 586 /*
 587  * Fill in the hpte_page_sizes[] array.
 588  * We go through the mmu_psize_defs[] array looking for all the
 589  * supported base/actual page size combinations.  Each combination
 590  * has a unique pagesize encoding (penc) value in the low bits of
 591  * the LP field of the HPTE.  For actual page sizes less than 1MB,
 592  * some of the upper LP bits are used for RPN bits, meaning that
 593  * we need to fill in several entries in hpte_page_sizes[].
 594  *
 595  * In diagrammatic form, with r = RPN bits and z = page size bits:
 596  *        PTE LP     actual page size
 597  *    rrrr rrrz         >=8KB
 598  *    rrrr rrzz         >=16KB
 599  *    rrrr rzzz         >=32KB
 600  *    rrrr zzzz         >=64KB
 601  *    ...
 602  *
 603  * The zzzz bits are implementation-specific but are chosen so that
 604  * no encoding for a larger page size uses the same value in its
 605  * low-order N bits as the encoding for the 2^(12+N) byte page size
 606  * (if it exists).
 607  */
 608 static void init_hpte_page_sizes(void)
 609 {
 610         long int ap, bp;
 611         long int shift, penc;
 612
 613         for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
 614                 if (!mmu_psize_defs[bp].shift)
 615                         continue;       /* not a supported page size */
 616                 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
 617                         penc = mmu_psize_defs[bp].penc[ap];
 618                         if (penc == -1 || !mmu_psize_defs[ap].shift)
 619                                 continue;
 620                         shift = mmu_psize_defs[ap].shift - LP_SHIFT;
 621                         if (shift <= 0)
 622                                 continue;       /* should never happen */
 623                         /*
 624                          * For page sizes less than 1MB, this loop
 625                          * replicates the entry for all possible values
 626                          * of the rrrr bits.
 627                          */
 628                         while (penc < (1 << LP_BITS)) {
 629                                 hpte_page_sizes[penc] = (ap << 4) | bp;
 630                                 penc += 1 << shift;
 631                         }
 632                 }
 633         }
 634 }
 635
 636 static void __init htab_init_page_sizes(void)
 637 {
 638         init_hpte_page_sizes();
 639
 640         if (!debug_pagealloc_enabled()) {
 641                 /*
 642                  * Pick a size for the linear mapping. Currently, we only
 643                  * support 16M, 1M and 4K which is the default
 644                  */
 645                 if (mmu_psize_defs[MMU_PAGE_16M].shift)
 646                         mmu_linear_psize = MMU_PAGE_16M;
 647                 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
 648                         mmu_linear_psize = MMU_PAGE_1M;
 649         }
 650
 651 #ifdef CONFIG_PPC_64K_PAGES
 652         /*
 653          * Pick a size for the ordinary pages. Default is 4K, we support
 654          * 64K for user mappings and vmalloc if supported by the processor.
 655          * We only use 64k for ioremap if the processor
 656          * (and firmware) support cache-inhibited large pages.
 657          * If not, we use 4k and set mmu_ci_restrictions so that
 658          * hash_page knows to switch processes that use cache-inhibited
 659          * mappings to 4k pages.
 660          */
 661         if (mmu_psize_defs[MMU_PAGE_64K].shift) {
 662                 mmu_virtual_psize = MMU_PAGE_64K;
 663                 mmu_vmalloc_psize = MMU_PAGE_64K;
 664                 if (mmu_linear_psize == MMU_PAGE_4K)
 665                         mmu_linear_psize = MMU_PAGE_64K;
 666                 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
 667                         /*
 668                          * When running on pSeries using 64k pages for ioremap
 669                          * would stop us accessing the HEA ethernet. So if we
 670                          * have the chance of ever seeing one, stay at 4k.
 671                          */
 672                         if (!might_have_hea())
 673                                 mmu_io_psize = MMU_PAGE_64K;
 674                 } else
 675                         mmu_ci_restrictions = 1;
 676         }
 677 #endif /* CONFIG_PPC_64K_PAGES */
 678
 679 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 680         /*
 681          * We try to use 16M pages for vmemmap if that is supported
 682          * and we have at least 1G of RAM at boot
 683          */
 684         if (mmu_psize_defs[MMU_PAGE_16M].shift &&
 685             memblock_phys_mem_size() >= 0x40000000)
 686                 mmu_vmemmap_psize = MMU_PAGE_16M;
 687         else if (mmu_psize_defs[MMU_PAGE_64K].shift)
 688                 mmu_vmemmap_psize = MMU_PAGE_64K;
 689         else
 690                 mmu_vmemmap_psize = MMU_PAGE_4K;
 691 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
 692
 693         printk(KERN_DEBUG "Page orders: linear mapping = %d, "
 694                "virtual = %d, io = %d"
 695 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 696                ", vmemmap = %d"
 697 #endif
 698                "\n",
 699                mmu_psize_defs[mmu_linear_psize].shift,
 700                mmu_psize_defs[mmu_virtual_psize].shift,
 701                mmu_psize_defs[mmu_io_psize].shift
 702 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 703                ,mmu_psize_defs[mmu_vmemmap_psize].shift
 704 #endif
 705                );
 706 }
 707
 708 static int __init htab_dt_scan_pftsize(unsigned long node,
 709                                        const char *uname, int depth,
 710                                        void *data)
 711 {
 712         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 713         const __be32 *prop;
 714
 715         /* We are scanning "cpu" nodes only */
 716         if (type == NULL || strcmp(type, "cpu") != 0)
 717                 return 0;
 718
 719         prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
 720         if (prop != NULL) {
 721                 /* pft_size[0] is the NUMA CEC cookie */
 722                 ppc64_pft_size = be32_to_cpu(prop[1]);
 723                 return 1;
 724         }
 725         return 0;
 726 }
 727
 728 unsigned htab_shift_for_mem_size(unsigned long mem_size)
 729 {
 730         unsigned memshift = __ilog2(mem_size);
 731         unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
 732         unsigned pteg_shift;
 733
 734         /* round mem_size up to next power of 2 */
 735         if ((1UL << memshift) < mem_size)
 736                 memshift += 1;
 737
 738         /* aim for 2 pages / pteg */
 739         pteg_shift = memshift - (pshift + 1);
 740
 741         /*
 742          * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
 743          * size permitted by the architecture.
 744          */
 745         return max(pteg_shift + 7, 18U);
 746 }
 747
 748 static unsigned long __init htab_get_table_size(void)
 749 {
 750         /*
 751          * If hash size isn't already provided by the platform, we try to
 752          * retrieve it from the device-tree. If it's not there neither, we
 753          * calculate it now based on the total RAM size
 754          */
 755         if (ppc64_pft_size == 0)
 756                 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
 757         if (ppc64_pft_size)
 758                 return 1UL << ppc64_pft_size;
 759
 760         return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
 761 }
 762
 763 #ifdef CONFIG_MEMORY_HOTPLUG
 764 int resize_hpt_for_hotplug(unsigned long new_mem_size)
 765 {
 766         unsigned target_hpt_shift;
 767
 768         if (!mmu_hash_ops.resize_hpt)
 769                 return 0;
 770
 771         target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
 772
 773         /*
 774          * To avoid lots of HPT resizes if memory size is fluctuating
 775          * across a boundary, we deliberately have some hysterisis
 776          * here: we immediately increase the HPT size if the target
 777          * shift exceeds the current shift, but we won't attempt to
 778          * reduce unless the target shift is at least 2 below the
 779          * current shift
 780          */
 781         if (target_hpt_shift > ppc64_pft_size ||
 782             target_hpt_shift < ppc64_pft_size - 1)
 783                 return mmu_hash_ops.resize_hpt(target_hpt_shift);
 784
 785         return 0;
 786 }
 787
 788 int hash__create_section_mapping(unsigned long start, unsigned long end, int nid)
 789 {
 790         int rc;
 791
 792         if (end >= H_VMALLOC_START) {
 793                 pr_warn("Outside the supported range\n");
 794                 return -1;
 795         }
 796
 797         rc = htab_bolt_mapping(start, end, __pa(start),
 798                                pgprot_val(PAGE_KERNEL), mmu_linear_psize,
 799                                mmu_kernel_ssize);
 800
 801         if (rc < 0) {
 802                 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
 803                                               mmu_kernel_ssize);
 804                 BUG_ON(rc2 && (rc2 != -ENOENT));
 805         }
 806         return rc;
 807 }
 808
 809 int hash__remove_section_mapping(unsigned long start, unsigned long end)
 810 {
 811         int rc = htab_remove_mapping(start, end, mmu_linear_psize,
 812                                      mmu_kernel_ssize);
 813         WARN_ON(rc < 0);
 814         return rc;
 815 }
 816 #endif /* CONFIG_MEMORY_HOTPLUG */
 817
 818 static void __init hash_init_partition_table(phys_addr_t hash_table,
 819                                              unsigned long htab_size)
 820 {
 821         mmu_partition_table_init();
 822
 823         /*
 824          * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
 825          * For now, UPRT is 0 and we have no segment table.
 826          */
 827         htab_size =  __ilog2(htab_size) - 18;
 828         mmu_partition_table_set_entry(0, hash_table | htab_size, 0);
 829         pr_info("Partition table %p\n", partition_tb);
 830 }
 831
 832 static void __init htab_initialize(void)
 833 {
 834         unsigned long table;
 835         unsigned long pteg_count;
 836         unsigned long prot;
 837         unsigned long base = 0, size = 0;
 838         struct memblock_region *reg;
 839
 840         DBG(" -> htab_initialize()\n");
 841
 842         if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
 843                 mmu_kernel_ssize = MMU_SEGSIZE_1T;
 844                 mmu_highuser_ssize = MMU_SEGSIZE_1T;
 845                 printk(KERN_INFO "Using 1TB segments\n");
 846         }
 847
 848         /*
 849          * Calculate the required size of the htab.  We want the number of
 850          * PTEGs to equal one half the number of real pages.
 851          */
 852         htab_size_bytes = htab_get_table_size();
 853         pteg_count = htab_size_bytes >> 7;
 854
 855         htab_hash_mask = pteg_count - 1;
 856
 857         if (firmware_has_feature(FW_FEATURE_LPAR) ||
 858             firmware_has_feature(FW_FEATURE_PS3_LV1)) {
 859                 /* Using a hypervisor which owns the htab */
 860                 htab_address = NULL;
 861                 _SDR1 = 0;
 862                 /*
 863                  * On POWER9, we need to do a H_REGISTER_PROC_TBL hcall
 864                  * to inform the hypervisor that we wish to use the HPT.
 865                  */
 866                 if (cpu_has_feature(CPU_FTR_ARCH_300))
 867                         register_process_table(0, 0, 0);
 868 #ifdef CONFIG_FA_DUMP
 869                 /*
 870                  * If firmware assisted dump is active firmware preserves
 871                  * the contents of htab along with entire partition memory.
 872                  * Clear the htab if firmware assisted dump is active so
 873                  * that we dont end up using old mappings.
 874                  */
 875                 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
 876                         mmu_hash_ops.hpte_clear_all();
 877 #endif
 878         } else {
 879                 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
 880
 881 #ifdef CONFIG_PPC_CELL
 882                 /*
 883                  * Cell may require the hash table down low when using the
 884                  * Axon IOMMU in order to fit the dynamic region over it, see
 885                  * comments in cell/iommu.c
 886                  */
 887                 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
 888                         limit = 0x80000000;
 889                         pr_info("Hash table forced below 2G for Axon IOMMU\n");
 890                 }
 891 #endif /* CONFIG_PPC_CELL */
 892
 893                 table = memblock_phys_alloc_range(htab_size_bytes,
 894                                                   htab_size_bytes,
 895                                                   0, limit);
 896                 if (!table)
 897                         panic("ERROR: Failed to allocate %pa bytes below %pa\n",
 898                               &htab_size_bytes, &limit);
 899
 900                 DBG("Hash table allocated at %lx, size: %lx\n", table,
 901                     htab_size_bytes);
 902
 903                 htab_address = __va(table);
 904
 905                 /* htab absolute addr + encoded htabsize */
 906                 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
 907
 908                 /* Initialize the HPT with no entries */
 909                 memset((void *)table, 0, htab_size_bytes);
 910
 911                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
 912                         /* Set SDR1 */
 913                         mtspr(SPRN_SDR1, _SDR1);
 914                 else
 915                         hash_init_partition_table(table, htab_size_bytes);
 916         }
 917
 918         prot = pgprot_val(PAGE_KERNEL);
 919
 920 #ifdef CONFIG_DEBUG_PAGEALLOC
 921         if (debug_pagealloc_enabled()) {
 922                 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
 923                 linear_map_hash_slots = memblock_alloc_try_nid(
 924                                 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT,
 925                                 ppc64_rma_size, NUMA_NO_NODE);
 926                 if (!linear_map_hash_slots)
 927                         panic("%s: Failed to allocate %lu bytes max_addr=%pa\n",
 928                               __func__, linear_map_hash_count, &ppc64_rma_size);
 929         }
 930 #endif /* CONFIG_DEBUG_PAGEALLOC */
 931
 932         /* create bolted the linear mapping in the hash table */
 933         for_each_memblock(memory, reg) {
 934                 base = (unsigned long)__va(reg->base);
 935                 size = reg->size;
 936
 937                 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
 938                     base, size, prot);
 939
 940                 if ((base + size) >= H_VMALLOC_START) {
 941                         pr_warn("Outside the supported range\n");
 942                         continue;
 943                 }
 944
 945                 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
 946                                 prot, mmu_linear_psize, mmu_kernel_ssize));
 947         }
 948         memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
 949
 950         /*
 951          * If we have a memory_limit and we've allocated TCEs then we need to
 952          * explicitly map the TCE area at the top of RAM. We also cope with the
 953          * case that the TCEs start below memory_limit.
 954          * tce_alloc_start/end are 16MB aligned so the mapping should work
 955          * for either 4K or 16MB pages.
 956          */
 957         if (tce_alloc_start) {
 958                 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
 959                 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
 960
 961                 if (base + size >= tce_alloc_start)
 962                         tce_alloc_start = base + size + 1;
 963
 964                 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
 965                                          __pa(tce_alloc_start), prot,
 966                                          mmu_linear_psize, mmu_kernel_ssize));
 967         }
 968
 969
 970         DBG(" <- htab_initialize()\n");
 971 }
 972 #undef KB
 973 #undef MB
 974
 975 void __init hash__early_init_devtree(void)
 976 {
 977         /* Initialize segment sizes */
 978         of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
 979
 980         /* Initialize page sizes */
 981         htab_scan_page_sizes();
 982 }
 983
 984 struct hash_mm_context init_hash_mm_context;
 985 void __init hash__early_init_mmu(void)
 986 {
 987 #ifndef CONFIG_PPC_64K_PAGES
 988         /*
 989          * We have code in __hash_page_4K() and elsewhere, which assumes it can
 990          * do the following:
 991          *   new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
 992          *
 993          * Where the slot number is between 0-15, and values of 8-15 indicate
 994          * the secondary bucket. For that code to work H_PAGE_F_SECOND and
 995          * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
 996          * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
 997          * with a BUILD_BUG_ON().
 998          */
 999         BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul  << (H_PAGE_F_GIX_SHIFT + 3)));
1000 #endif /* CONFIG_PPC_64K_PAGES */
1001
1002         htab_init_page_sizes();
1003
1004         /*
1005          * initialize page table size
1006          */
1007         __pte_frag_nr = H_PTE_FRAG_NR;
1008         __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
1009         __pmd_frag_nr = H_PMD_FRAG_NR;
1010         __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT;
1011
1012         __pte_index_size = H_PTE_INDEX_SIZE;
1013         __pmd_index_size = H_PMD_INDEX_SIZE;
1014         __pud_index_size = H_PUD_INDEX_SIZE;
1015         __pgd_index_size = H_PGD_INDEX_SIZE;
1016         __pud_cache_index = H_PUD_CACHE_INDEX;
1017         __pte_table_size = H_PTE_TABLE_SIZE;
1018         __pmd_table_size = H_PMD_TABLE_SIZE;
1019         __pud_table_size = H_PUD_TABLE_SIZE;
1020         __pgd_table_size = H_PGD_TABLE_SIZE;
1021         /*
1022          * 4k use hugepd format, so for hash set then to
1023          * zero
1024          */
1025         __pmd_val_bits = HASH_PMD_VAL_BITS;
1026         __pud_val_bits = HASH_PUD_VAL_BITS;
1027         __pgd_val_bits = HASH_PGD_VAL_BITS;
1028
1029         __kernel_virt_start = H_KERN_VIRT_START;
1030         __vmalloc_start = H_VMALLOC_START;
1031         __vmalloc_end = H_VMALLOC_END;
1032         __kernel_io_start = H_KERN_IO_START;
1033         __kernel_io_end = H_KERN_IO_END;
1034         vmemmap = (struct page *)H_VMEMMAP_START;
1035         ioremap_bot = IOREMAP_BASE;
1036
1037 #ifdef CONFIG_PCI
1038         pci_io_base = ISA_IO_BASE;
1039 #endif
1040
1041         /* Select appropriate backend */
1042         if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1043                 ps3_early_mm_init();
1044         else if (firmware_has_feature(FW_FEATURE_LPAR))
1045                 hpte_init_pseries();
1046         else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1047                 hpte_init_native();
1048
1049         if (!mmu_hash_ops.hpte_insert)
1050                 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1051
1052         /*
1053          * Initialize the MMU Hash table and create the linear mapping
1054          * of memory. Has to be done before SLB initialization as this is
1055          * currently where the page size encoding is obtained.
1056          */
1057         htab_initialize();
1058
1059         init_mm.context.hash_context = &init_hash_mm_context;
1060         mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT);
1061
1062         pr_info("Initializing hash mmu with SLB\n");
1063         /* Initialize SLB management */
1064         slb_initialize();
1065
1066         if (cpu_has_feature(CPU_FTR_ARCH_206)
1067                         && cpu_has_feature(CPU_FTR_HVMODE))
1068                 tlbiel_all();
1069 }
1070
1071 #ifdef CONFIG_SMP
1072 void hash__early_init_mmu_secondary(void)
1073 {
1074         /* Initialize hash table for that CPU */
1075         if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1076
1077                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1078                         mtspr(SPRN_SDR1, _SDR1);
1079                 else
1080                         mtspr(SPRN_PTCR,
1081                               __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
1082         }
1083         /* Initialize SLB */
1084         slb_initialize();
1085
1086         if (cpu_has_feature(CPU_FTR_ARCH_206)
1087                         && cpu_has_feature(CPU_FTR_HVMODE))
1088                 tlbiel_all();
1089 }
1090 #endif /* CONFIG_SMP */
1091
1092 /*
1093  * Called by asm hashtable.S for doing lazy icache flush
1094  */
1095 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1096 {
1097         struct page *page;
1098
1099         if (!pfn_valid(pte_pfn(pte)))
1100                 return pp;
1101
1102         page = pte_page(pte);
1103
1104         /* page is dirty */
1105         if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1106                 if (trap == 0x400) {
1107                         flush_dcache_icache_page(page);
1108                         set_bit(PG_arch_1, &page->flags);
1109                 } else
1110                         pp |= HPTE_R_N;
1111         }
1112         return pp;
1113 }
1114
1115 #ifdef CONFIG_PPC_MM_SLICES
1116 static unsigned int get_paca_psize(unsigned long addr)
1117 {
1118         unsigned char *psizes;
1119         unsigned long index, mask_index;
1120
1121         if (addr < SLICE_LOW_TOP) {
1122                 psizes = get_paca()->mm_ctx_low_slices_psize;
1123                 index = GET_LOW_SLICE_INDEX(addr);
1124         } else {
1125                 psizes = get_paca()->mm_ctx_high_slices_psize;
1126                 index = GET_HIGH_SLICE_INDEX(addr);
1127         }
1128         mask_index = index & 0x1;
1129         return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1130 }
1131
1132 #else
1133 unsigned int get_paca_psize(unsigned long addr)
1134 {
1135         return get_paca()->mm_ctx_user_psize;
1136 }
1137 #endif
1138
1139 /*
1140  * Demote a segment to using 4k pages.
1141  * For now this makes the whole process use 4k pages.
1142  */
1143 #ifdef CONFIG_PPC_64K_PAGES
1144 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1145 {
1146         if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1147                 return;
1148         slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1149         copro_flush_all_slbs(mm);
1150         if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1151
1152                 copy_mm_to_paca(mm);
1153                 slb_flush_and_restore_bolted();
1154         }
1155 }
1156 #endif /* CONFIG_PPC_64K_PAGES */
1157
1158 #ifdef CONFIG_PPC_SUBPAGE_PROT
1159 /*
1160  * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1161  * Userspace sets the subpage permissions using the subpage_prot system call.
1162  *
1163  * Result is 0: full permissions, _PAGE_RW: read-only,
1164  * _PAGE_RWX: no access.
1165  */
1166 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1167 {
1168         struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context);
1169         u32 spp = 0;
1170         u32 **sbpm, *sbpp;
1171
1172         if (!spt)
1173                 return 0;
1174
1175         if (ea >= spt->maxaddr)
1176                 return 0;
1177         if (ea < 0x100000000UL) {
1178                 /* addresses below 4GB use spt->low_prot */
1179                 sbpm = spt->low_prot;
1180         } else {
1181                 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1182                 if (!sbpm)
1183                         return 0;
1184         }
1185         sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1186         if (!sbpp)
1187                 return 0;
1188         spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1189
1190         /* extract 2-bit bitfield for this 4k subpage */
1191         spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1192
1193         /*
1194          * 0 -> full premission
1195          * 1 -> Read only
1196          * 2 -> no access.
1197          * We return the flag that need to be cleared.
1198          */
1199         spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1200         return spp;
1201 }
1202
1203 #else /* CONFIG_PPC_SUBPAGE_PROT */
1204 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1205 {
1206         return 0;
1207 }
1208 #endif
1209
1210 void hash_failure_debug(unsigned long ea, unsigned long access,
1211                         unsigned long vsid, unsigned long trap,
1212                         int ssize, int psize, int lpsize, unsigned long pte)
1213 {
1214         if (!printk_ratelimit())
1215                 return;
1216         pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1217                 ea, access, current->comm);
1218         pr_info("    trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1219                 trap, vsid, ssize, psize, lpsize, pte);
1220 }
1221
1222 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1223                              int psize, bool user_region)
1224 {
1225         if (user_region) {
1226                 if (psize != get_paca_psize(ea)) {
1227                         copy_mm_to_paca(mm);
1228                         slb_flush_and_restore_bolted();
1229                 }
1230         } else if (get_paca()->vmalloc_sllp !=
1231                    mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1232                 get_paca()->vmalloc_sllp =
1233                         mmu_psize_defs[mmu_vmalloc_psize].sllp;
1234                 slb_vmalloc_update();
1235         }
1236 }
1237
1238 /*
1239  * Result code is:
1240  *  0 - handled
1241  *  1 - normal page fault
1242  * -1 - critical hash insertion error
1243  * -2 - access not permitted by subpage protection mechanism
1244  */
1245 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1246                  unsigned long access, unsigned long trap,
1247                  unsigned long flags)
1248 {
1249         bool is_thp;
1250         enum ctx_state prev_state = exception_enter();
1251         pgd_t *pgdir;
1252         unsigned long vsid;
1253         pte_t *ptep;
1254         unsigned hugeshift;
1255         int rc, user_region = 0;
1256         int psize, ssize;
1257
1258         DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1259                 ea, access, trap);
1260         trace_hash_fault(ea, access, trap);
1261
1262         /* Get region & vsid */
1263         switch (get_region_id(ea)) {
1264         case USER_REGION_ID:
1265                 user_region = 1;
1266                 if (! mm) {
1267                         DBG_LOW(" user region with no mm !\n");
1268                         rc = 1;
1269                         goto bail;
1270                 }
1271                 psize = get_slice_psize(mm, ea);
1272                 ssize = user_segment_size(ea);
1273                 vsid = get_user_vsid(&mm->context, ea, ssize);
1274                 break;
1275         case VMALLOC_REGION_ID:
1276                 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1277                 psize = mmu_vmalloc_psize;
1278                 ssize = mmu_kernel_ssize;
1279                 break;
1280
1281         case IO_REGION_ID:
1282                 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1283                 psize = mmu_io_psize;
1284                 ssize = mmu_kernel_ssize;
1285                 break;
1286         default:
1287                 /*
1288                  * Not a valid range
1289                  * Send the problem up to do_page_fault()
1290                  */
1291                 rc = 1;
1292                 goto bail;
1293         }
1294         DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1295
1296         /* Bad address. */
1297         if (!vsid) {
1298                 DBG_LOW("Bad address!\n");
1299                 rc = 1;
1300                 goto bail;
1301         }
1302         /* Get pgdir */
1303         pgdir = mm->pgd;
1304         if (pgdir == NULL) {
1305                 rc = 1;
1306                 goto bail;
1307         }
1308
1309         /* Check CPU locality */
1310         if (user_region && mm_is_thread_local(mm))
1311                 flags |= HPTE_LOCAL_UPDATE;
1312
1313 #ifndef CONFIG_PPC_64K_PAGES
1314         /*
1315          * If we use 4K pages and our psize is not 4K, then we might
1316          * be hitting a special driver mapping, and need to align the
1317          * address before we fetch the PTE.
1318          *
1319          * It could also be a hugepage mapping, in which case this is
1320          * not necessary, but it's not harmful, either.
1321          */
1322         if (psize != MMU_PAGE_4K)
1323                 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1324 #endif /* CONFIG_PPC_64K_PAGES */
1325
1326         /* Get PTE and page size from page tables */
1327         ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1328         if (ptep == NULL || !pte_present(*ptep)) {
1329                 DBG_LOW(" no PTE !\n");
1330                 rc = 1;
1331                 goto bail;
1332         }
1333
1334         /* Add _PAGE_PRESENT to the required access perm */
1335         access |= _PAGE_PRESENT;
1336
1337         /*
1338          * Pre-check access permissions (will be re-checked atomically
1339          * in __hash_page_XX but this pre-check is a fast path
1340          */
1341         if (!check_pte_access(access, pte_val(*ptep))) {
1342                 DBG_LOW(" no access !\n");
1343                 rc = 1;
1344                 goto bail;
1345         }
1346
1347         if (hugeshift) {
1348                 if (is_thp)
1349                         rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1350                                              trap, flags, ssize, psize);
1351 #ifdef CONFIG_HUGETLB_PAGE
1352                 else
1353                         rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1354                                               flags, ssize, hugeshift, psize);
1355 #else
1356                 else {
1357                         /*
1358                          * if we have hugeshift, and is not transhuge with
1359                          * hugetlb disabled, something is really wrong.
1360                          */
1361                         rc = 1;
1362                         WARN_ON(1);
1363                 }
1364 #endif
1365                 if (current->mm == mm)
1366                         check_paca_psize(ea, mm, psize, user_region);
1367
1368                 goto bail;
1369         }
1370
1371 #ifndef CONFIG_PPC_64K_PAGES
1372         DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1373 #else
1374         DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1375                 pte_val(*(ptep + PTRS_PER_PTE)));
1376 #endif
1377         /* Do actual hashing */
1378 #ifdef CONFIG_PPC_64K_PAGES
1379         /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1380         if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1381                 demote_segment_4k(mm, ea);
1382                 psize = MMU_PAGE_4K;
1383         }
1384
1385         /*
1386          * If this PTE is non-cacheable and we have restrictions on
1387          * using non cacheable large pages, then we switch to 4k
1388          */
1389         if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1390                 if (user_region) {
1391                         demote_segment_4k(mm, ea);
1392                         psize = MMU_PAGE_4K;
1393                 } else if (ea < VMALLOC_END) {
1394                         /*
1395                          * some driver did a non-cacheable mapping
1396                          * in vmalloc space, so switch vmalloc
1397                          * to 4k pages
1398                          */
1399                         printk(KERN_ALERT "Reducing vmalloc segment "
1400                                "to 4kB pages because of "
1401                                "non-cacheable mapping\n");
1402                         psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1403                         copro_flush_all_slbs(mm);
1404                 }
1405         }
1406
1407 #endif /* CONFIG_PPC_64K_PAGES */
1408
1409         if (current->mm == mm)
1410                 check_paca_psize(ea, mm, psize, user_region);
1411
1412 #ifdef CONFIG_PPC_64K_PAGES
1413         if (psize == MMU_PAGE_64K)
1414                 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1415                                      flags, ssize);
1416         else
1417 #endif /* CONFIG_PPC_64K_PAGES */
1418         {
1419                 int spp = subpage_protection(mm, ea);
1420                 if (access & spp)
1421                         rc = -2;
1422                 else
1423                         rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1424                                             flags, ssize, spp);
1425         }
1426
1427         /*
1428          * Dump some info in case of hash insertion failure, they should
1429          * never happen so it is really useful to know if/when they do
1430          */
1431         if (rc == -1)
1432                 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1433                                    psize, pte_val(*ptep));
1434 #ifndef CONFIG_PPC_64K_PAGES
1435         DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1436 #else
1437         DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1438                 pte_val(*(ptep + PTRS_PER_PTE)));
1439 #endif
1440         DBG_LOW(" -> rc=%d\n", rc);
1441
1442 bail:
1443         exception_exit(prev_state);
1444         return rc;
1445 }
1446 EXPORT_SYMBOL_GPL(hash_page_mm);
1447
1448 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1449               unsigned long dsisr)
1450 {
1451         unsigned long flags = 0;
1452         struct mm_struct *mm = current->mm;
1453
1454         if ((get_region_id(ea) == VMALLOC_REGION_ID) ||
1455             (get_region_id(ea) == IO_REGION_ID))
1456                 mm = &init_mm;
1457
1458         if (dsisr & DSISR_NOHPTE)
1459                 flags |= HPTE_NOHPTE_UPDATE;
1460
1461         return hash_page_mm(mm, ea, access, trap, flags);
1462 }
1463 EXPORT_SYMBOL_GPL(hash_page);
1464
1465 int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1466                 unsigned long dsisr)
1467 {
1468         unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1469         unsigned long flags = 0;
1470         struct mm_struct *mm = current->mm;
1471         unsigned int region_id = get_region_id(ea);
1472
1473         if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID))
1474                 mm = &init_mm;
1475
1476         if (dsisr & DSISR_NOHPTE)
1477                 flags |= HPTE_NOHPTE_UPDATE;
1478
1479         if (dsisr & DSISR_ISSTORE)
1480                 access |= _PAGE_WRITE;
1481         /*
1482          * We set _PAGE_PRIVILEGED only when
1483          * kernel mode access kernel space.
1484          *
1485          * _PAGE_PRIVILEGED is NOT set
1486          * 1) when kernel mode access user space
1487          * 2) user space access kernel space.
1488          */
1489         access |= _PAGE_PRIVILEGED;
1490         if ((msr & MSR_PR) || (region_id == USER_REGION_ID))
1491                 access &= ~_PAGE_PRIVILEGED;
1492
1493         if (trap == 0x400)
1494                 access |= _PAGE_EXEC;
1495
1496         return hash_page_mm(mm, ea, access, trap, flags);
1497 }
1498
1499 #ifdef CONFIG_PPC_MM_SLICES
1500 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1501 {
1502         int psize = get_slice_psize(mm, ea);
1503
1504         /* We only prefault standard pages for now */
1505         if (unlikely(psize != mm_ctx_user_psize(&mm->context)))
1506                 return false;
1507
1508         /*
1509          * Don't prefault if subpage protection is enabled for the EA.
1510          */
1511         if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1512                 return false;
1513
1514         return true;
1515 }
1516 #else
1517 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1518 {
1519         return true;
1520 }
1521 #endif
1522
1523 void hash_preload(struct mm_struct *mm, unsigned long ea,
1524                   bool is_exec, unsigned long trap)
1525 {
1526         int hugepage_shift;
1527         unsigned long vsid;
1528         pgd_t *pgdir;
1529         pte_t *ptep;
1530         unsigned long flags;
1531         int rc, ssize, update_flags = 0;
1532         unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0);
1533
1534         BUG_ON(get_region_id(ea) != USER_REGION_ID);
1535
1536         if (!should_hash_preload(mm, ea))
1537                 return;
1538
1539         DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1540                 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1541
1542         /* Get Linux PTE if available */
1543         pgdir = mm->pgd;
1544         if (pgdir == NULL)
1545                 return;
1546
1547         /* Get VSID */
1548         ssize = user_segment_size(ea);
1549         vsid = get_user_vsid(&mm->context, ea, ssize);
1550         if (!vsid)
1551                 return;
1552         /*
1553          * Hash doesn't like irqs. Walking linux page table with irq disabled
1554          * saves us from holding multiple locks.
1555          */
1556         local_irq_save(flags);
1557
1558         /*
1559          * THP pages use update_mmu_cache_pmd. We don't do
1560          * hash preload there. Hence can ignore THP here
1561          */
1562         ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift);
1563         if (!ptep)
1564                 goto out_exit;
1565
1566         WARN_ON(hugepage_shift);
1567 #ifdef CONFIG_PPC_64K_PAGES
1568         /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1569          * a 64K kernel), then we don't preload, hash_page() will take
1570          * care of it once we actually try to access the page.
1571          * That way we don't have to duplicate all of the logic for segment
1572          * page size demotion here
1573          */
1574         if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1575                 goto out_exit;
1576 #endif /* CONFIG_PPC_64K_PAGES */
1577
1578         /* Is that local to this CPU ? */
1579         if (mm_is_thread_local(mm))
1580                 update_flags |= HPTE_LOCAL_UPDATE;
1581
1582         /* Hash it in */
1583 #ifdef CONFIG_PPC_64K_PAGES
1584         if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K)
1585                 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1586                                      update_flags, ssize);
1587         else
1588 #endif /* CONFIG_PPC_64K_PAGES */
1589                 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1590                                     ssize, subpage_protection(mm, ea));
1591
1592         /* Dump some info in case of hash insertion failure, they should
1593          * never happen so it is really useful to know if/when they do
1594          */
1595         if (rc == -1)
1596                 hash_failure_debug(ea, access, vsid, trap, ssize,
1597                                    mm_ctx_user_psize(&mm->context),
1598                                    mm_ctx_user_psize(&mm->context),
1599                                    pte_val(*ptep));
1600 out_exit:
1601         local_irq_restore(flags);
1602 }
1603
1604 #ifdef CONFIG_PPC_MEM_KEYS
1605 /*
1606  * Return the protection key associated with the given address and the
1607  * mm_struct.
1608  */
1609 u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address)
1610 {
1611         pte_t *ptep;
1612         u16 pkey = 0;
1613         unsigned long flags;
1614
1615         if (!mm || !mm->pgd)
1616                 return 0;
1617
1618         local_irq_save(flags);
1619         ptep = find_linux_pte(mm->pgd, address, NULL, NULL);
1620         if (ptep)
1621                 pkey = pte_to_pkey_bits(pte_val(READ_ONCE(*ptep)));
1622         local_irq_restore(flags);
1623
1624         return pkey;
1625 }
1626 #endif /* CONFIG_PPC_MEM_KEYS */
1627
1628 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1629 static inline void tm_flush_hash_page(int local)
1630 {
1631         /*
1632          * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1633          * page back to a block device w/PIO could pick up transactional data
1634          * (bad!) so we force an abort here. Before the sync the page will be
1635          * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1636          * kernel uses a page from userspace without unmapping it first, it may
1637          * see the speculated version.
1638          */
1639         if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1640             MSR_TM_ACTIVE(current->thread.regs->msr)) {
1641                 tm_enable();
1642                 tm_abort(TM_CAUSE_TLBI);
1643         }
1644 }
1645 #else
1646 static inline void tm_flush_hash_page(int local)
1647 {
1648 }
1649 #endif
1650
1651 /*
1652  * Return the global hash slot, corresponding to the given PTE, which contains
1653  * the HPTE.
1654  */
1655 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
1656                 int ssize, real_pte_t rpte, unsigned int subpg_index)
1657 {
1658         unsigned long hash, gslot, hidx;
1659
1660         hash = hpt_hash(vpn, shift, ssize);
1661         hidx = __rpte_to_hidx(rpte, subpg_index);
1662         if (hidx & _PTEIDX_SECONDARY)
1663                 hash = ~hash;
1664         gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1665         gslot += hidx & _PTEIDX_GROUP_IX;
1666         return gslot;
1667 }
1668
1669 /*
1670  * WARNING: This is called from hash_low_64.S, if you change this prototype,
1671  *          do not forget to update the assembly call site !
1672  */
1673 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1674                      unsigned long flags)
1675 {
1676         unsigned long index, shift, gslot;
1677         int local = flags & HPTE_LOCAL_UPDATE;
1678
1679         DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1680         pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1681                 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
1682                 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
1683                 /*
1684                  * We use same base page size and actual psize, because we don't
1685                  * use these functions for hugepage
1686                  */
1687                 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
1688                                              ssize, local);
1689         } pte_iterate_hashed_end();
1690
1691         tm_flush_hash_page(local);
1692 }
1693
1694 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1695 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1696                          pmd_t *pmdp, unsigned int psize, int ssize,
1697                          unsigned long flags)
1698 {
1699         int i, max_hpte_count, valid;
1700         unsigned long s_addr;
1701         unsigned char *hpte_slot_array;
1702         unsigned long hidx, shift, vpn, hash, slot;
1703         int local = flags & HPTE_LOCAL_UPDATE;
1704
1705         s_addr = addr & HPAGE_PMD_MASK;
1706         hpte_slot_array = get_hpte_slot_array(pmdp);
1707         /*
1708          * IF we try to do a HUGE PTE update after a withdraw is done.
1709          * we will find the below NULL. This happens when we do
1710          * split_huge_page_pmd
1711          */
1712         if (!hpte_slot_array)
1713                 return;
1714
1715         if (mmu_hash_ops.hugepage_invalidate) {
1716                 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1717                                                  psize, ssize, local);
1718                 goto tm_abort;
1719         }
1720         /*
1721          * No bluk hpte removal support, invalidate each entry
1722          */
1723         shift = mmu_psize_defs[psize].shift;
1724         max_hpte_count = HPAGE_PMD_SIZE >> shift;
1725         for (i = 0; i < max_hpte_count; i++) {
1726                 /*
1727                  * 8 bits per each hpte entries
1728                  * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1729                  */
1730                 valid = hpte_valid(hpte_slot_array, i);
1731                 if (!valid)
1732                         continue;
1733                 hidx =  hpte_hash_index(hpte_slot_array, i);
1734
1735                 /* get the vpn */
1736                 addr = s_addr + (i * (1ul << shift));
1737                 vpn = hpt_vpn(addr, vsid, ssize);
1738                 hash = hpt_hash(vpn, shift, ssize);
1739                 if (hidx & _PTEIDX_SECONDARY)
1740                         hash = ~hash;
1741
1742                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1743                 slot += hidx & _PTEIDX_GROUP_IX;
1744                 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1745                                              MMU_PAGE_16M, ssize, local);
1746         }
1747 tm_abort:
1748         tm_flush_hash_page(local);
1749 }
1750 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1751
1752 void flush_hash_range(unsigned long number, int local)
1753 {
1754         if (mmu_hash_ops.flush_hash_range)
1755                 mmu_hash_ops.flush_hash_range(number, local);
1756         else {
1757                 int i;
1758                 struct ppc64_tlb_batch *batch =
1759                         this_cpu_ptr(&ppc64_tlb_batch);
1760
1761                 for (i = 0; i < number; i++)
1762                         flush_hash_page(batch->vpn[i], batch->pte[i],
1763                                         batch->psize, batch->ssize, local);
1764         }
1765 }
1766
1767 /*
1768  * low_hash_fault is called when we the low level hash code failed
1769  * to instert a PTE due to an hypervisor error
1770  */
1771 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1772 {
1773         enum ctx_state prev_state = exception_enter();
1774
1775         if (user_mode(regs)) {
1776 #ifdef CONFIG_PPC_SUBPAGE_PROT
1777                 if (rc == -2)
1778                         _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1779                 else
1780 #endif
1781                         _exception(SIGBUS, regs, BUS_ADRERR, address);
1782         } else
1783                 bad_page_fault(regs, address, SIGBUS);
1784
1785         exception_exit(prev_state);
1786 }
1787
1788 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1789                            unsigned long pa, unsigned long rflags,
1790                            unsigned long vflags, int psize, int ssize)
1791 {
1792         unsigned long hpte_group;
1793         long slot;
1794
1795 repeat:
1796         hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1797
1798         /* Insert into the hash table, primary slot */
1799         slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1800                                         psize, psize, ssize);
1801
1802         /* Primary is full, try the secondary */
1803         if (unlikely(slot == -1)) {
1804                 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
1805                 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1806                                                 vflags | HPTE_V_SECONDARY,
1807                                                 psize, psize, ssize);
1808                 if (slot == -1) {
1809                         if (mftb() & 0x1)
1810                                 hpte_group = (hash & htab_hash_mask) *
1811                                                 HPTES_PER_GROUP;
1812
1813                         mmu_hash_ops.hpte_remove(hpte_group);
1814                         goto repeat;
1815                 }
1816         }
1817
1818         return slot;
1819 }
1820
1821 #ifdef CONFIG_DEBUG_PAGEALLOC
1822 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1823 {
1824         unsigned long hash;
1825         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1826         unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1827         unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1828         long ret;
1829
1830         hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1831
1832         /* Don't create HPTE entries for bad address */
1833         if (!vsid)
1834                 return;
1835
1836         ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1837                                     HPTE_V_BOLTED,
1838                                     mmu_linear_psize, mmu_kernel_ssize);
1839
1840         BUG_ON (ret < 0);
1841         spin_lock(&linear_map_hash_lock);
1842         BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1843         linear_map_hash_slots[lmi] = ret | 0x80;
1844         spin_unlock(&linear_map_hash_lock);
1845 }
1846
1847 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1848 {
1849         unsigned long hash, hidx, slot;
1850         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1851         unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1852
1853         hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1854         spin_lock(&linear_map_hash_lock);
1855         BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1856         hidx = linear_map_hash_slots[lmi] & 0x7f;
1857         linear_map_hash_slots[lmi] = 0;
1858         spin_unlock(&linear_map_hash_lock);
1859         if (hidx & _PTEIDX_SECONDARY)
1860                 hash = ~hash;
1861         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1862         slot += hidx & _PTEIDX_GROUP_IX;
1863         mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1864                                      mmu_linear_psize,
1865                                      mmu_kernel_ssize, 0);
1866 }
1867
1868 void __kernel_map_pages(struct page *page, int numpages, int enable)
1869 {
1870         unsigned long flags, vaddr, lmi;
1871         int i;
1872
1873         local_irq_save(flags);
1874         for (i = 0; i < numpages; i++, page++) {
1875                 vaddr = (unsigned long)page_address(page);
1876                 lmi = __pa(vaddr) >> PAGE_SHIFT;
1877                 if (lmi >= linear_map_hash_count)
1878                         continue;
1879                 if (enable)
1880                         kernel_map_linear_page(vaddr, lmi);
1881                 else
1882                         kernel_unmap_linear_page(vaddr, lmi);
1883         }
1884         local_irq_restore(flags);
1885 }
1886 #endif /* CONFIG_DEBUG_PAGEALLOC */
1887
1888 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1889                                 phys_addr_t first_memblock_size)
1890 {
1891         /*
1892          * We don't currently support the first MEMBLOCK not mapping 0
1893          * physical on those processors
1894          */
1895         BUG_ON(first_memblock_base != 0);
1896
1897         /*
1898          * On virtualized systems the first entry is our RMA region aka VRMA,
1899          * non-virtualized 64-bit hash MMU systems don't have a limitation
1900          * on real mode access.
1901          *
1902          * For guests on platforms before POWER9, we clamp the it limit to 1G
1903          * to avoid some funky things such as RTAS bugs etc...
1904          */
1905         if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
1906                 ppc64_rma_size = first_memblock_size;
1907                 if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
1908                         ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
1909
1910                 /* Finally limit subsequent allocations */
1911                 memblock_set_current_limit(ppc64_rma_size);
1912         } else {
1913                 ppc64_rma_size = ULONG_MAX;
1914         }
1915 }
1916
1917 #ifdef CONFIG_DEBUG_FS
1918
1919 static int hpt_order_get(void *data, u64 *val)
1920 {
1921         *val = ppc64_pft_size;
1922         return 0;
1923 }
1924
1925 static int hpt_order_set(void *data, u64 val)
1926 {
1927         if (!mmu_hash_ops.resize_hpt)
1928                 return -ENODEV;
1929
1930         return mmu_hash_ops.resize_hpt(val);
1931 }
1932
1933 DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
1934
1935 static int __init hash64_debugfs(void)
1936 {
1937         if (!debugfs_create_file_unsafe("hpt_order", 0600, powerpc_debugfs_root,
1938                                         NULL, &fops_hpt_order)) {
1939                 pr_err("lpar: unable to create hpt_order debugsfs file\n");
1940         }
1941
1942         return 0;
1943 }
1944 machine_device_initcall(pseries, hash64_debugfs);
1945 #endif /* CONFIG_DEBUG_FS */
1946
1947 void __init print_system_hash_info(void)
1948 {
1949         pr_info("ppc64_pft_size    = 0x%llx\n", ppc64_pft_size);
1950
1951         if (htab_hash_mask)
1952                 pr_info("htab_hash_mask    = 0x%lx\n", htab_hash_mask);
1953         pr_info("kernel vmalloc start   = 0x%lx\n", KERN_VIRT_START);
1954         pr_info("kernel IO start        = 0x%lx\n", KERN_IO_START);
1955         pr_info("kernel vmemmap start   = 0x%lx\n", (unsigned long)vmemmap);
1956 }