2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/book3s/64/mmu-hash.h>
33 #include <asm/xive-regs.h>
35 /* Sign-extend HDEC if not on POWER9 */
36 #define EXTEND_HDEC(reg) \
39 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
41 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
43 /* Values in HSTATE_NAPPING(r13) */
44 #define NAPPING_CEDE 1
45 #define NAPPING_NOVCPU 2
47 /* Stack frame offsets for kvmppc_hv_entry */
49 #define STACK_SLOT_TRAP (SFS-4)
50 #define STACK_SLOT_TID (SFS-16)
51 #define STACK_SLOT_PSSCR (SFS-24)
52 #define STACK_SLOT_PID (SFS-32)
53 #define STACK_SLOT_IAMR (SFS-40)
54 #define STACK_SLOT_CIABR (SFS-48)
55 #define STACK_SLOT_DAWR (SFS-56)
56 #define STACK_SLOT_DAWRX (SFS-64)
57 #define STACK_SLOT_HFSCR (SFS-72)
60 * Call kvmppc_hv_entry in real mode.
61 * Must be called with interrupts hard-disabled.
65 * LR = return address to continue at after eventually re-enabling MMU
67 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
69 std r0, PPC_LR_STKOFF(r1)
72 std r10, HSTATE_HOST_MSR(r13)
73 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
78 mtmsrd r0,1 /* clear RI in MSR */
84 ld r4, HSTATE_KVM_VCPU(r13)
87 /* Back from guest - restore host state and return to caller */
90 /* Restore host DABR and DABRX */
91 ld r5,HSTATE_DABR(r13)
95 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
98 ld r3,PACA_SPRG_VDSO(r13)
99 mtspr SPRN_SPRG_VDSO_WRITE,r3
101 /* Reload the host's PMU registers */
102 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
103 lbz r4, LPPACA_PMCINUSE(r3)
105 beq 23f /* skip if not */
107 ld r3, HSTATE_MMCR0(r13)
108 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
111 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
112 lwz r3, HSTATE_PMC1(r13)
113 lwz r4, HSTATE_PMC2(r13)
114 lwz r5, HSTATE_PMC3(r13)
115 lwz r6, HSTATE_PMC4(r13)
116 lwz r8, HSTATE_PMC5(r13)
117 lwz r9, HSTATE_PMC6(r13)
124 ld r3, HSTATE_MMCR0(r13)
125 ld r4, HSTATE_MMCR1(r13)
126 ld r5, HSTATE_MMCRA(r13)
127 ld r6, HSTATE_SIAR(r13)
128 ld r7, HSTATE_SDAR(r13)
134 ld r8, HSTATE_MMCR2(r13)
135 ld r9, HSTATE_SIER(r13)
138 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
144 * Reload DEC. HDEC interrupts were disabled when
145 * we reloaded the host's LPCR value.
147 ld r3, HSTATE_DECEXP(r13)
153 /* hwthread_req may have got set by cede or no vcpu, so clear it */
155 stb r0, HSTATE_HWTHREAD_REQ(r13)
156 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
159 * For external interrupts we need to call the Linux
160 * handler to process the interrupt. We do that by jumping
161 * to absolute address 0x500 for external interrupts.
162 * The [h]rfid at the end of the handler will return to
163 * the book3s_hv_interrupts.S code. For other interrupts
164 * we do the rfid to get back to the book3s_hv_interrupts.S
167 ld r8, 112+PPC_LR_STKOFF(r1)
169 ld r7, HSTATE_HOST_MSR(r13)
171 /* Return the trap number on this thread as the return value */
175 * If we came back from the guest via a relocation-on interrupt,
176 * we will be in virtual mode at this point, which makes it a
177 * little easier to get back to the caller.
180 andi. r0, r0, MSR_IR /* in real mode? */
183 /* RFI into the highmem handler */
187 mtmsrd r6, 1 /* Clear RI in MSR */
192 /* Virtual-mode return */
197 kvmppc_primary_no_guest:
198 /* We handle this much like a ceded vcpu */
199 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
200 /* HDEC may be larger than DEC for arch >= v3.00, but since the */
201 /* HDEC value came from DEC in the first place, it will fit */
205 * Make sure the primary has finished the MMU switch.
206 * We should never get here on a secondary thread, but
207 * check it for robustness' sake.
209 ld r5, HSTATE_KVM_VCORE(r13)
210 65: lbz r0, VCORE_IN_GUEST(r5)
217 /* set our bit in napping_threads */
218 ld r5, HSTATE_KVM_VCORE(r13)
219 lbz r7, HSTATE_PTID(r13)
222 addi r6, r5, VCORE_NAPPING_THREADS
227 /* order napping_threads update vs testing entry_exit_map */
230 lwz r7, VCORE_ENTRY_EXIT(r5)
232 bge kvm_novcpu_exit /* another thread already exiting */
233 li r3, NAPPING_NOVCPU
234 stb r3, HSTATE_NAPPING(r13)
236 li r3, 0 /* Don't wake on privileged (OS) doorbell */
241 * Entered from kvm_start_guest if kvm_hstate.napping is set
247 ld r1, HSTATE_HOST_R1(r13)
248 ld r5, HSTATE_KVM_VCORE(r13)
250 stb r0, HSTATE_NAPPING(r13)
252 /* check the wake reason */
253 bl kvmppc_check_wake_reason
256 * Restore volatile registers since we could have called
257 * a C routine in kvmppc_check_wake_reason.
260 ld r5, HSTATE_KVM_VCORE(r13)
262 /* see if any other thread is already exiting */
263 lwz r0, VCORE_ENTRY_EXIT(r5)
267 /* clear our bit in napping_threads */
268 lbz r7, HSTATE_PTID(r13)
271 addi r6, r5, VCORE_NAPPING_THREADS
277 /* See if the wake reason means we need to exit */
281 /* See if our timeslice has expired (HDEC is negative) */
284 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
288 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
289 ld r4, HSTATE_KVM_VCPU(r13)
291 beq kvmppc_primary_no_guest
293 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
294 addi r3, r4, VCPU_TB_RMENTRY
295 bl kvmhv_start_timing
300 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
301 ld r4, HSTATE_KVM_VCPU(r13)
304 addi r3, r4, VCPU_TB_RMEXIT
305 bl kvmhv_accumulate_time
308 stw r12, STACK_SLOT_TRAP(r1)
309 bl kvmhv_commence_exit
311 lwz r12, STACK_SLOT_TRAP(r1)
312 b kvmhv_switch_to_host
315 * We come in here when wakened from nap mode.
316 * Relocation is off and most register values are lost.
317 * r13 points to the PACA.
318 * r3 contains the SRR1 wakeup value, SRR1 is trashed.
319 * This is not used by ISAv3.0B processors.
321 .globl kvm_start_guest
323 /* Set runlatch bit the minute you wake up from nap */
329 * Could avoid this and pass it through in r3. For now,
330 * code expects it to be in SRR1.
336 li r0,KVM_HWTHREAD_IN_KVM
337 stb r0,HSTATE_HWTHREAD_STATE(r13)
339 /* NV GPR values from power7_idle() will no longer be valid */
341 stb r0,PACA_NAPSTATELOST(r13)
343 /* were we napping due to cede? */
344 lbz r0,HSTATE_NAPPING(r13)
345 cmpwi r0,NAPPING_CEDE
347 cmpwi r0,NAPPING_NOVCPU
348 beq kvm_novcpu_wakeup
350 ld r1,PACAEMERGSP(r13)
351 subi r1,r1,STACK_FRAME_OVERHEAD
354 * We weren't napping due to cede, so this must be a secondary
355 * thread being woken up to run a guest, or being woken up due
356 * to a stray IPI. (Or due to some machine check or hypervisor
357 * maintenance interrupt while the core is in KVM.)
360 /* Check the wake reason in SRR1 to see why we got here */
361 bl kvmppc_check_wake_reason
363 * kvmppc_check_wake_reason could invoke a C routine, but we
364 * have no volatile registers to restore when we return.
370 /* get vcore pointer, NULL if we have nothing to run */
371 ld r5,HSTATE_KVM_VCORE(r13)
373 /* if we have no vcore to run, go back to sleep */
376 kvm_secondary_got_guest:
378 /* Set HSTATE_DSCR(r13) to something sensible */
379 ld r6, PACA_DSCR_DEFAULT(r13)
380 std r6, HSTATE_DSCR(r13)
382 /* On thread 0 of a subcore, set HDEC to max */
383 lbz r4, HSTATE_PTID(r13)
386 LOAD_REG_ADDR(r6, decrementer_max)
389 /* and set per-LPAR registers, if doing dynamic micro-threading */
390 ld r6, HSTATE_SPLIT_MODE(r13)
393 ld r0, KVM_SPLIT_RPR(r6)
395 ld r0, KVM_SPLIT_PMMAR(r6)
397 ld r0, KVM_SPLIT_LDBAR(r6)
401 /* Order load of vcpu after load of vcore */
403 ld r4, HSTATE_KVM_VCPU(r13)
406 /* Back from the guest, go back to nap */
407 /* Clear our vcpu and vcore pointers so we don't come back in early */
409 std r0, HSTATE_KVM_VCPU(r13)
411 * Once we clear HSTATE_KVM_VCORE(r13), the code in
412 * kvmppc_run_core() is going to assume that all our vcpu
413 * state is visible in memory. This lwsync makes sure
417 std r0, HSTATE_KVM_VCORE(r13)
420 * All secondaries exiting guest will fall through this path.
421 * Before proceeding, just check for HMI interrupt and
422 * invoke opal hmi handler. By now we are sure that the
423 * primary thread on this core/subcore has already made partition
424 * switch/TB resync and we are good to call opal hmi handler.
426 cmpwi r12, BOOK3S_INTERRUPT_HMI
429 li r3,0 /* NULL argument */
430 bl hmi_exception_realmode
432 * At this point we have finished executing in the guest.
433 * We need to wait for hwthread_req to become zero, since
434 * we may not turn on the MMU while hwthread_req is non-zero.
435 * While waiting we also need to check if we get given a vcpu to run.
440 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
441 lbz r3, HSTATE_HWTHREAD_REQ(r13)
445 li r0, KVM_HWTHREAD_IN_KERNEL
446 stb r0, HSTATE_HWTHREAD_STATE(r13)
447 /* need to recheck hwthread_req after a barrier, to avoid race */
449 lbz r3, HSTATE_HWTHREAD_REQ(r13)
453 * We jump to pnv_wakeup_loss, which will return to the caller
454 * of power7_nap in the powernv cpu offline loop. The value we
455 * put in r3 becomes the return value for power7_nap. pnv_wakeup_loss
456 * requires SRR1 in r12.
460 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
467 ld r5, HSTATE_KVM_VCORE(r13)
470 ld r3, HSTATE_SPLIT_MODE(r13)
473 lbz r0, KVM_SPLIT_DO_NAP(r3)
479 b kvm_secondary_got_guest
481 54: li r0, KVM_HWTHREAD_IN_KVM
482 stb r0, HSTATE_HWTHREAD_STATE(r13)
486 * Here the primary thread is trying to return the core to
487 * whole-core mode, so we need to nap.
491 * When secondaries are napping in kvm_unsplit_nap() with
492 * hwthread_req = 1, HMI goes ignored even though subcores are
493 * already exited the guest. Hence HMI keeps waking up secondaries
494 * from nap in a loop and secondaries always go back to nap since
495 * no vcore is assigned to them. This makes impossible for primary
496 * thread to get hold of secondary threads resulting into a soft
497 * lockup in KVM path.
499 * Let us check if HMI is pending and handle it before we go to nap.
501 cmpwi r12, BOOK3S_INTERRUPT_HMI
503 li r3, 0 /* NULL argument */
504 bl hmi_exception_realmode
507 * Ensure that secondary doesn't nap when it has
508 * its vcore pointer set.
510 sync /* matches smp_mb() before setting split_info.do_nap */
511 ld r0, HSTATE_KVM_VCORE(r13)
514 /* clear any pending message */
516 lis r6, (PPC_DBELL_SERVER << (63-36))@h
518 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
519 /* Set kvm_split_mode.napped[tid] = 1 */
520 ld r3, HSTATE_SPLIT_MODE(r13)
522 lhz r4, PACAPACAINDEX(r13)
523 clrldi r4, r4, 61 /* micro-threading => P8 => 8 threads/core */
524 addi r4, r4, KVM_SPLIT_NAPPED
526 /* Check the do_nap flag again after setting napped[] */
528 lbz r0, KVM_SPLIT_DO_NAP(r3)
531 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
533 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
540 /******************************************************************************
544 *****************************************************************************/
546 .global kvmppc_hv_entry
551 * R4 = vcpu pointer (or NULL)
556 * all other volatile GPRS = free
557 * Does not preserve non-volatile GPRs or CR fields
560 std r0, PPC_LR_STKOFF(r1)
563 /* Save R1 in the PACA */
564 std r1, HSTATE_HOST_R1(r13)
566 li r6, KVM_GUEST_MODE_HOST_HV
567 stb r6, HSTATE_IN_GUEST(r13)
569 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
570 /* Store initial timestamp */
573 addi r3, r4, VCPU_TB_RMENTRY
574 bl kvmhv_start_timing
578 /* Use cr7 as an indication of radix mode */
579 ld r5, HSTATE_KVM_VCORE(r13)
580 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
581 lbz r0, KVM_RADIX(r9)
584 /* Clear out SLB if hash */
592 * POWER7/POWER8 host -> guest partition switch code.
593 * We don't have to lock against concurrent tlbies,
594 * but we do have to coordinate across hardware threads.
596 /* Set bit in entry map iff exit map is zero. */
598 lbz r6, HSTATE_PTID(r13)
600 addi r8, r5, VCORE_ENTRY_EXIT
602 cmpwi r3, 0x100 /* any threads starting to exit? */
603 bge secondary_too_late /* if so we're too late to the party */
608 /* Primary thread switches to guest partition. */
614 li r0,LPID_RSVD /* switch to reserved LPID */
617 mtspr SPRN_SDR1,r6 /* switch to partition page table */
618 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
622 /* See if we need to flush the TLB */
623 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
626 * On POWER9, individual threads can come in here, but the
627 * TLB is shared between the 4 threads in a core, hence
628 * invalidating on one thread invalidates for all.
629 * Thus we make all 4 threads use the same bit here.
632 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
633 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
634 srdi r6,r6,6 /* doubleword number */
635 sldi r6,r6,3 /* address offset */
637 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
643 /* Flush the TLB of any entries for this LPID */
644 lwz r0,KVM_TLB_SETS(r9)
646 li r7,0x800 /* IS field = 0b10 */
648 li r0,0 /* RS for P9 version of tlbiel */
650 28: tlbiel r7 /* On P9, rs=0, RIC=0, PRS=0, R=0 */
654 29: PPC_TLBIEL(7,0,2,1,1) /* for radix, RIC=2, PRS=1, R=1 */
658 23: ldarx r7,0,r6 /* clear the bit after TLB flushed */
663 /* Add timebase offset onto timebase */
664 22: ld r8,VCORE_TB_OFFSET(r5)
667 mftb r6 /* current host timebase */
669 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
670 mftb r7 /* check if lower 24 bits overflowed */
675 addis r8,r8,0x100 /* if so, increment upper 40 bits */
678 /* Load guest PCR value to select appropriate compat mode */
679 37: ld r7, VCORE_PCR(r5)
686 /* DPDES and VTB are shared between threads */
687 ld r8, VCORE_DPDES(r5)
691 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
693 /* Mark the subcore state as inside guest */
694 bl kvmppc_subcore_enter_guest
696 ld r5, HSTATE_KVM_VCORE(r13)
697 ld r4, HSTATE_KVM_VCPU(r13)
699 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
701 /* Do we have a guest vcpu to run? */
703 beq kvmppc_primary_no_guest
706 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
707 lwz r5,VCPU_SLB_MAX(r4)
712 1: ld r8,VCPU_SLB_E(r6)
715 addi r6,r6,VCPU_SLB_SIZE
718 /* Increment yield count if they have a VPA */
722 li r6, LPPACA_YIELDCOUNT
727 stb r6, VCPU_VPA_DIRTY(r4)
730 /* Save purr/spurr */
733 std r5,HSTATE_PURR(r13)
734 std r6,HSTATE_SPURR(r13)
740 /* Save host values of some registers */
746 std r5, STACK_SLOT_TID(r1)
747 std r6, STACK_SLOT_PSSCR(r1)
748 std r7, STACK_SLOT_PID(r1)
749 std r8, STACK_SLOT_IAMR(r1)
751 std r5, STACK_SLOT_HFSCR(r1)
752 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
757 std r5, STACK_SLOT_CIABR(r1)
758 std r6, STACK_SLOT_DAWR(r1)
759 std r7, STACK_SLOT_DAWRX(r1)
760 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
763 /* Set partition DABR */
764 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
765 lwz r5,VCPU_DABRX(r4)
770 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
772 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
775 END_FTR_SECTION_IFSET(CPU_FTR_TM)
778 /* Load guest PMU registers */
779 /* R4 is live here (vcpu pointer) */
781 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
782 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
786 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
789 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
790 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
791 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
792 lwz r6, VCPU_PMC + 8(r4)
793 lwz r7, VCPU_PMC + 12(r4)
794 lwz r8, VCPU_PMC + 16(r4)
795 lwz r9, VCPU_PMC + 20(r4)
803 ld r5, VCPU_MMCR + 8(r4)
804 ld r6, VCPU_MMCR + 16(r4)
812 ld r5, VCPU_MMCR + 24(r4)
816 BEGIN_FTR_SECTION_NESTED(96)
817 lwz r7, VCPU_PMC + 24(r4)
818 lwz r8, VCPU_PMC + 28(r4)
819 ld r9, VCPU_MMCR + 32(r4)
823 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
824 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
828 /* Load up FP, VMX and VSX registers */
831 ld r14, VCPU_GPR(R14)(r4)
832 ld r15, VCPU_GPR(R15)(r4)
833 ld r16, VCPU_GPR(R16)(r4)
834 ld r17, VCPU_GPR(R17)(r4)
835 ld r18, VCPU_GPR(R18)(r4)
836 ld r19, VCPU_GPR(R19)(r4)
837 ld r20, VCPU_GPR(R20)(r4)
838 ld r21, VCPU_GPR(R21)(r4)
839 ld r22, VCPU_GPR(R22)(r4)
840 ld r23, VCPU_GPR(R23)(r4)
841 ld r24, VCPU_GPR(R24)(r4)
842 ld r25, VCPU_GPR(R25)(r4)
843 ld r26, VCPU_GPR(R26)(r4)
844 ld r27, VCPU_GPR(R27)(r4)
845 ld r28, VCPU_GPR(R28)(r4)
846 ld r29, VCPU_GPR(R29)(r4)
847 ld r30, VCPU_GPR(R30)(r4)
848 ld r31, VCPU_GPR(R31)(r4)
850 /* Switch DSCR to guest value */
855 /* Skip next section on POWER7 */
857 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
858 /* Load up POWER8-specific registers */
860 lwz r6, VCPU_PSPB(r4)
866 ld r6, VCPU_DAWRX(r4)
867 ld r7, VCPU_CIABR(r4)
874 ld r8, VCPU_EBBHR(r4)
877 ld r5, VCPU_EBBRR(r4)
878 ld r6, VCPU_BESCR(r4)
879 lwz r7, VCPU_GUEST_PID(r4)
887 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
889 /* POWER8-only registers */
890 ld r5, VCPU_TCSCR(r4)
892 ld r7, VCPU_CSIGR(r4)
899 /* POWER9-only registers */
901 ld r6, VCPU_PSSCR(r4)
902 oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */
903 ld r7, VCPU_HFSCR(r4)
907 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
911 * Set the decrementer to the guest decrementer.
913 ld r8,VCPU_DEC_EXPIRES(r4)
914 /* r8 is a host timebase value here, convert to guest TB */
915 ld r5,HSTATE_KVM_VCORE(r13)
916 ld r6,VCORE_TB_OFFSET(r5)
923 ld r5, VCPU_SPRG0(r4)
924 ld r6, VCPU_SPRG1(r4)
925 ld r7, VCPU_SPRG2(r4)
926 ld r8, VCPU_SPRG3(r4)
932 /* Load up DAR and DSISR */
934 lwz r6, VCPU_DSISR(r4)
938 /* Restore AMR and UAMOR, set AMOR to all 1s */
946 /* Restore state of CTRL run bit; assume 1 on entry */
954 /* Secondary threads wait for primary to have done partition switch */
955 ld r5, HSTATE_KVM_VCORE(r13)
956 lbz r6, HSTATE_PTID(r13)
959 lbz r0, VCORE_IN_GUEST(r5)
963 20: lwz r3, VCORE_ENTRY_EXIT(r5)
966 lbz r0, VCORE_IN_GUEST(r5)
976 /* Check if HDEC expires soon */
979 cmpdi r3, 512 /* 1 microsecond */
982 #ifdef CONFIG_KVM_XICS
983 /* We are entering the guest on that thread, push VCPU to XIVE */
984 ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
987 ld r11, VCPU_XIVE_SAVED_STATE(r4)
991 lwz r11, VCPU_XIVE_CAM_WORD(r4)
992 li r9, TM_QW1_OS + TM_WORD2
995 stw r9, VCPU_XIVE_PUSHED(r4)
997 #endif /* CONFIG_KVM_XICS */
999 deliver_guest_interrupt:
1006 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
1008 ld r11, VCPU_MSR(r4)
1009 ld r6, VCPU_SRR0(r4)
1010 ld r7, VCPU_SRR1(r4)
1014 /* r11 = vcpu->arch.msr & ~MSR_HV */
1015 rldicl r11, r11, 63 - MSR_HV_LG, 1
1016 rotldi r11, r11, 1 + MSR_HV_LG
1017 ori r11, r11, MSR_ME
1019 /* Check if we can deliver an external or decrementer interrupt now */
1020 ld r0, VCPU_PENDING_EXC(r4)
1021 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
1023 andi. r8, r11, MSR_EE
1025 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
1026 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
1030 li r0, BOOK3S_INTERRUPT_EXTERNAL
1034 /* On POWER9 check whether the guest has large decrementer enabled */
1035 andis. r8, r8, LPCR_LD@h
1037 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1040 li r0, BOOK3S_INTERRUPT_DECREMENTER
1043 12: mtspr SPRN_SRR0, r10
1045 mtspr SPRN_SRR1, r11
1047 bl kvmppc_msr_interrupt
1051 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1052 /* On POWER9, check for pending doorbell requests */
1053 lbz r0, VCPU_DBELL_REQ(r4)
1055 beq fast_guest_return
1056 ld r5, HSTATE_KVM_VCORE(r13)
1057 /* Set DPDES register so the CPU will take a doorbell interrupt */
1059 mtspr SPRN_DPDES, r0
1060 std r0, VCORE_DPDES(r5)
1061 /* Make sure other cpus see vcore->dpdes set before dbell req clear */
1063 /* Clear the pending doorbell request */
1065 stb r0, VCPU_DBELL_REQ(r4)
1070 * R10: value for HSRR0
1071 * R11: value for HSRR1
1076 stb r0,VCPU_CEDED(r4) /* cancel cede */
1077 mtspr SPRN_HSRR0,r10
1078 mtspr SPRN_HSRR1,r11
1080 /* Activate guest mode, so faults get handled by KVM */
1081 li r9, KVM_GUEST_MODE_GUEST_HV
1082 stb r9, HSTATE_IN_GUEST(r13)
1084 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1085 /* Accumulate timing */
1086 addi r3, r4, VCPU_TB_GUEST
1087 bl kvmhv_accumulate_time
1093 ld r5, VCPU_CFAR(r4)
1095 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1098 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1105 ld r1, VCPU_GPR(R1)(r4)
1106 ld r2, VCPU_GPR(R2)(r4)
1107 ld r3, VCPU_GPR(R3)(r4)
1108 ld r5, VCPU_GPR(R5)(r4)
1109 ld r6, VCPU_GPR(R6)(r4)
1110 ld r7, VCPU_GPR(R7)(r4)
1111 ld r8, VCPU_GPR(R8)(r4)
1112 ld r9, VCPU_GPR(R9)(r4)
1113 ld r10, VCPU_GPR(R10)(r4)
1114 ld r11, VCPU_GPR(R11)(r4)
1115 ld r12, VCPU_GPR(R12)(r4)
1116 ld r13, VCPU_GPR(R13)(r4)
1120 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1121 ld r0, VCPU_GPR(R0)(r4)
1122 ld r4, VCPU_GPR(R4)(r4)
1131 stw r12, VCPU_TRAP(r4)
1132 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1133 addi r3, r4, VCPU_TB_RMEXIT
1134 bl kvmhv_accumulate_time
1136 11: b kvmhv_switch_to_host
1143 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1144 12: stw r12, VCPU_TRAP(r4)
1146 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1147 addi r3, r4, VCPU_TB_RMEXIT
1148 bl kvmhv_accumulate_time
1152 /******************************************************************************
1156 *****************************************************************************/
1159 * We come here from the first-level interrupt handlers.
1161 .globl kvmppc_interrupt_hv
1162 kvmppc_interrupt_hv:
1164 * Register contents:
1165 * R12 = (guest CR << 32) | interrupt vector
1167 * guest R12 saved in shadow VCPU SCRATCH0
1168 * guest CTR saved in shadow VCPU SCRATCH1 if RELOCATABLE
1169 * guest R13 saved in SPRN_SCRATCH0
1171 std r9, HSTATE_SCRATCH2(r13)
1172 lbz r9, HSTATE_IN_GUEST(r13)
1173 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1174 beq kvmppc_bad_host_intr
1175 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1176 cmpwi r9, KVM_GUEST_MODE_GUEST
1177 ld r9, HSTATE_SCRATCH2(r13)
1178 beq kvmppc_interrupt_pr
1180 /* We're now back in the host but in guest MMU context */
1181 li r9, KVM_GUEST_MODE_HOST_HV
1182 stb r9, HSTATE_IN_GUEST(r13)
1184 ld r9, HSTATE_KVM_VCPU(r13)
1186 /* Save registers */
1188 std r0, VCPU_GPR(R0)(r9)
1189 std r1, VCPU_GPR(R1)(r9)
1190 std r2, VCPU_GPR(R2)(r9)
1191 std r3, VCPU_GPR(R3)(r9)
1192 std r4, VCPU_GPR(R4)(r9)
1193 std r5, VCPU_GPR(R5)(r9)
1194 std r6, VCPU_GPR(R6)(r9)
1195 std r7, VCPU_GPR(R7)(r9)
1196 std r8, VCPU_GPR(R8)(r9)
1197 ld r0, HSTATE_SCRATCH2(r13)
1198 std r0, VCPU_GPR(R9)(r9)
1199 std r10, VCPU_GPR(R10)(r9)
1200 std r11, VCPU_GPR(R11)(r9)
1201 ld r3, HSTATE_SCRATCH0(r13)
1202 std r3, VCPU_GPR(R12)(r9)
1203 /* CR is in the high half of r12 */
1207 ld r3, HSTATE_CFAR(r13)
1208 std r3, VCPU_CFAR(r9)
1209 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1211 ld r4, HSTATE_PPR(r13)
1212 std r4, VCPU_PPR(r9)
1213 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1215 /* Restore R1/R2 so we can handle faults */
1216 ld r1, HSTATE_HOST_R1(r13)
1219 mfspr r10, SPRN_SRR0
1220 mfspr r11, SPRN_SRR1
1221 std r10, VCPU_SRR0(r9)
1222 std r11, VCPU_SRR1(r9)
1223 /* trap is in the low half of r12, clear CR from the high half */
1225 andi. r0, r12, 2 /* need to read HSRR0/1? */
1227 mfspr r10, SPRN_HSRR0
1228 mfspr r11, SPRN_HSRR1
1230 1: std r10, VCPU_PC(r9)
1231 std r11, VCPU_MSR(r9)
1235 std r3, VCPU_GPR(R13)(r9)
1238 stw r12,VCPU_TRAP(r9)
1241 * Now that we have saved away SRR0/1 and HSRR0/1,
1242 * interrupts are recoverable in principle, so set MSR_RI.
1243 * This becomes important for relocation-on interrupts from
1244 * the guest, which we can get in radix mode on POWER9.
1249 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1250 addi r3, r9, VCPU_TB_RMINTR
1252 bl kvmhv_accumulate_time
1253 ld r5, VCPU_GPR(R5)(r9)
1254 ld r6, VCPU_GPR(R6)(r9)
1255 ld r7, VCPU_GPR(R7)(r9)
1256 ld r8, VCPU_GPR(R8)(r9)
1259 /* Save HEIR (HV emulation assist reg) in emul_inst
1260 if this is an HEI (HV emulation interrupt, e40) */
1261 li r3,KVM_INST_FETCH_FAILED
1262 stw r3,VCPU_LAST_INST(r9)
1263 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1266 11: stw r3,VCPU_HEIR(r9)
1268 /* these are volatile across C function calls */
1269 #ifdef CONFIG_RELOCATABLE
1270 ld r3, HSTATE_SCRATCH1(r13)
1276 std r3, VCPU_CTR(r9)
1277 std r4, VCPU_XER(r9)
1279 /* If this is a page table miss then see if it's theirs or ours */
1280 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1282 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1285 /* See if this is a leftover HDEC interrupt */
1286 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1291 bge fast_guest_return
1293 /* See if this is an hcall we can handle in real mode */
1294 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1295 beq hcall_try_real_mode
1297 /* Hypervisor doorbell - exit only if host IPI flag set */
1298 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1302 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1303 lbz r0, HSTATE_HOST_IPI(r13)
1308 /* If it's a hypervisor facility unavailable interrupt, save HFSCR */
1309 cmpwi r12, BOOK3S_INTERRUPT_H_FAC_UNAVAIL
1311 mfspr r3, SPRN_HFSCR
1312 std r3, VCPU_HFSCR(r9)
1315 /* External interrupt ? */
1316 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1317 bne+ guest_exit_cont
1319 /* External interrupt, first check for host_ipi. If this is
1320 * set, we know the host wants us out so let's do it now
1325 * Restore the active volatile registers after returning from
1328 ld r9, HSTATE_KVM_VCPU(r13)
1329 li r12, BOOK3S_INTERRUPT_EXTERNAL
1332 * kvmppc_read_intr return codes:
1334 * Exit to host (r3 > 0)
1335 * 1 An interrupt is pending that needs to be handled by the host
1336 * Exit guest and return to host by branching to guest_exit_cont
1338 * 2 Passthrough that needs completion in the host
1339 * Exit guest and return to host by branching to guest_exit_cont
1340 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1341 * to indicate to the host to complete handling the interrupt
1343 * Before returning to guest, we check if any CPU is heading out
1344 * to the host and if so, we head out also. If no CPUs are heading
1345 * check return values <= 0.
1347 * Return to guest (r3 <= 0)
1348 * 0 No external interrupt is pending
1349 * -1 A guest wakeup IPI (which has now been cleared)
1350 * In either case, we return to guest to deliver any pending
1353 * -2 A PCI passthrough external interrupt was handled
1354 * (interrupt was delivered directly to guest)
1355 * Return to guest to deliver any pending guest interrupts.
1361 /* Return code = 2 */
1362 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
1363 stw r12, VCPU_TRAP(r9)
1366 1: /* Return code <= 1 */
1370 /* Return code <= 0 */
1371 4: ld r5, HSTATE_KVM_VCORE(r13)
1372 lwz r0, VCORE_ENTRY_EXIT(r5)
1375 blt deliver_guest_interrupt
1377 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1378 #ifdef CONFIG_KVM_XICS
1379 /* We are exiting, pull the VP from the XIVE */
1380 lwz r0, VCPU_XIVE_PUSHED(r9)
1383 li r7, TM_SPC_PULL_OS_CTX
1386 andi. r0, r0, MSR_IR /* in real mode? */
1388 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
1391 /* First load to pull the context, we ignore the value */
1394 /* Second load to recover the context state (Words 0 and 1) */
1397 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1400 /* First load to pull the context, we ignore the value */
1403 /* Second load to recover the context state (Words 0 and 1) */
1405 3: std r11, VCPU_XIVE_SAVED_STATE(r9)
1406 /* Fixup some of the state for the next load */
1409 stw r10, VCPU_XIVE_PUSHED(r9)
1410 stb r10, (VCPU_XIVE_SAVED_STATE+3)(r9)
1411 stb r0, (VCPU_XIVE_SAVED_STATE+4)(r9)
1413 #endif /* CONFIG_KVM_XICS */
1414 /* Save more register state */
1417 std r6, VCPU_DAR(r9)
1418 stw r7, VCPU_DSISR(r9)
1419 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1420 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1422 std r6, VCPU_FAULT_DAR(r9)
1423 stw r7, VCPU_FAULT_DSISR(r9)
1425 /* See if it is a machine check */
1426 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1427 beq machine_check_realmode
1429 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1430 addi r3, r9, VCPU_TB_RMEXIT
1432 bl kvmhv_accumulate_time
1436 /* Increment exit count, poke other threads to exit */
1437 bl kvmhv_commence_exit
1439 ld r9, HSTATE_KVM_VCPU(r13)
1440 lwz r12, VCPU_TRAP(r9)
1442 /* Stop others sending VCPU interrupts to this physical CPU */
1444 stw r0, VCPU_CPU(r9)
1445 stw r0, VCPU_THREAD_CPU(r9)
1447 /* Save guest CTRL register, set runlatch to 1 */
1449 stw r6,VCPU_CTRL(r9)
1455 /* Check if we are running hash or radix and store it in cr2 */
1457 lbz r0, KVM_RADIX(r5)
1460 /* Read the guest SLB and save it away */
1462 bne cr2, 3f /* for radix, save 0 entries */
1463 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1468 andis. r0,r8,SLB_ESID_V@h
1470 add r8,r8,r6 /* put index in */
1472 std r8,VCPU_SLB_E(r7)
1473 std r3,VCPU_SLB_V(r7)
1474 addi r7,r7,VCPU_SLB_SIZE
1478 3: stw r5,VCPU_SLB_MAX(r9)
1481 * Save the guest PURR/SPURR
1486 ld r8,VCPU_SPURR(r9)
1487 std r5,VCPU_PURR(r9)
1488 std r6,VCPU_SPURR(r9)
1493 * Restore host PURR/SPURR and add guest times
1494 * so that the time in the guest gets accounted.
1496 ld r3,HSTATE_PURR(r13)
1497 ld r4,HSTATE_SPURR(r13)
1504 ld r3, HSTATE_KVM_VCORE(r13)
1507 /* On P9, if the guest has large decr enabled, don't sign extend */
1509 ld r4, VCORE_LPCR(r3)
1510 andis. r4, r4, LPCR_LD@h
1512 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1515 /* r5 is a guest timebase value here, convert to host TB */
1516 ld r4,VCORE_TB_OFFSET(r3)
1518 std r5,VCPU_DEC_EXPIRES(r9)
1522 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1523 /* Save POWER8-specific registers */
1527 std r5, VCPU_IAMR(r9)
1528 stw r6, VCPU_PSPB(r9)
1529 std r7, VCPU_FSCR(r9)
1533 std r7, VCPU_TAR(r9)
1534 mfspr r8, SPRN_EBBHR
1535 std r8, VCPU_EBBHR(r9)
1536 mfspr r5, SPRN_EBBRR
1537 mfspr r6, SPRN_BESCR
1540 std r5, VCPU_EBBRR(r9)
1541 std r6, VCPU_BESCR(r9)
1542 stw r7, VCPU_GUEST_PID(r9)
1543 std r8, VCPU_WORT(r9)
1545 mfspr r5, SPRN_TCSCR
1547 mfspr r7, SPRN_CSIGR
1549 std r5, VCPU_TCSCR(r9)
1550 std r6, VCPU_ACOP(r9)
1551 std r7, VCPU_CSIGR(r9)
1552 std r8, VCPU_TACR(r9)
1555 mfspr r6, SPRN_PSSCR
1556 std r5, VCPU_TID(r9)
1557 rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */
1559 std r6, VCPU_PSSCR(r9)
1560 /* Restore host HFSCR value */
1561 ld r7, STACK_SLOT_HFSCR(r1)
1562 mtspr SPRN_HFSCR, r7
1563 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
1565 * Restore various registers to 0, where non-zero values
1566 * set by the guest could disrupt the host.
1573 mtspr SPRN_TCSCR, r0
1574 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1577 mtspr SPRN_MMCRS, r0
1578 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1581 /* Save and reset AMR and UAMOR before turning on the MMU */
1585 std r6,VCPU_UAMOR(r9)
1588 mtspr SPRN_UAMOR, r6
1590 /* Switch DSCR back to host value */
1592 ld r7, HSTATE_DSCR(r13)
1593 std r8, VCPU_DSCR(r9)
1596 /* Save non-volatile GPRs */
1597 std r14, VCPU_GPR(R14)(r9)
1598 std r15, VCPU_GPR(R15)(r9)
1599 std r16, VCPU_GPR(R16)(r9)
1600 std r17, VCPU_GPR(R17)(r9)
1601 std r18, VCPU_GPR(R18)(r9)
1602 std r19, VCPU_GPR(R19)(r9)
1603 std r20, VCPU_GPR(R20)(r9)
1604 std r21, VCPU_GPR(R21)(r9)
1605 std r22, VCPU_GPR(R22)(r9)
1606 std r23, VCPU_GPR(R23)(r9)
1607 std r24, VCPU_GPR(R24)(r9)
1608 std r25, VCPU_GPR(R25)(r9)
1609 std r26, VCPU_GPR(R26)(r9)
1610 std r27, VCPU_GPR(R27)(r9)
1611 std r28, VCPU_GPR(R28)(r9)
1612 std r29, VCPU_GPR(R29)(r9)
1613 std r30, VCPU_GPR(R30)(r9)
1614 std r31, VCPU_GPR(R31)(r9)
1617 mfspr r3, SPRN_SPRG0
1618 mfspr r4, SPRN_SPRG1
1619 mfspr r5, SPRN_SPRG2
1620 mfspr r6, SPRN_SPRG3
1621 std r3, VCPU_SPRG0(r9)
1622 std r4, VCPU_SPRG1(r9)
1623 std r5, VCPU_SPRG2(r9)
1624 std r6, VCPU_SPRG3(r9)
1630 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1633 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1636 /* Increment yield count if they have a VPA */
1637 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1640 li r4, LPPACA_YIELDCOUNT
1645 stb r3, VCPU_VPA_DIRTY(r9)
1647 /* Save PMU registers if requested */
1648 /* r8 and cr0.eq are live here */
1651 * POWER8 seems to have a hardware bug where setting
1652 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1653 * when some counters are already negative doesn't seem
1654 * to cause a performance monitor alert (and hence interrupt).
1655 * The effect of this is that when saving the PMU state,
1656 * if there is no PMU alert pending when we read MMCR0
1657 * before freezing the counters, but one becomes pending
1658 * before we read the counters, we lose it.
1659 * To work around this, we need a way to freeze the counters
1660 * before reading MMCR0. Normally, freezing the counters
1661 * is done by writing MMCR0 (to set MMCR0[FC]) which
1662 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1663 * we can also freeze the counters using MMCR2, by writing
1664 * 1s to all the counter freeze condition bits (there are
1665 * 9 bits each for 6 counters).
1667 li r3, -1 /* set all freeze bits */
1669 mfspr r10, SPRN_MMCR2
1670 mtspr SPRN_MMCR2, r3
1672 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1674 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1675 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1676 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1677 mfspr r6, SPRN_MMCRA
1678 /* Clear MMCRA in order to disable SDAR updates */
1680 mtspr SPRN_MMCRA, r7
1682 beq 21f /* if no VPA, save PMU stuff anyway */
1683 lbz r7, LPPACA_PMCINUSE(r8)
1684 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1686 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1688 21: mfspr r5, SPRN_MMCR1
1691 std r4, VCPU_MMCR(r9)
1692 std r5, VCPU_MMCR + 8(r9)
1693 std r6, VCPU_MMCR + 16(r9)
1695 std r10, VCPU_MMCR + 24(r9)
1696 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1697 std r7, VCPU_SIAR(r9)
1698 std r8, VCPU_SDAR(r9)
1705 stw r3, VCPU_PMC(r9)
1706 stw r4, VCPU_PMC + 4(r9)
1707 stw r5, VCPU_PMC + 8(r9)
1708 stw r6, VCPU_PMC + 12(r9)
1709 stw r7, VCPU_PMC + 16(r9)
1710 stw r8, VCPU_PMC + 20(r9)
1713 std r5, VCPU_SIER(r9)
1714 BEGIN_FTR_SECTION_NESTED(96)
1715 mfspr r6, SPRN_SPMC1
1716 mfspr r7, SPRN_SPMC2
1717 mfspr r8, SPRN_MMCRS
1718 stw r6, VCPU_PMC + 24(r9)
1719 stw r7, VCPU_PMC + 28(r9)
1720 std r8, VCPU_MMCR + 32(r9)
1722 mtspr SPRN_MMCRS, r4
1723 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
1724 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1727 /* Restore host values of some registers */
1729 ld r5, STACK_SLOT_CIABR(r1)
1730 ld r6, STACK_SLOT_DAWR(r1)
1731 ld r7, STACK_SLOT_DAWRX(r1)
1732 mtspr SPRN_CIABR, r5
1734 mtspr SPRN_DAWRX, r7
1735 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1737 ld r5, STACK_SLOT_TID(r1)
1738 ld r6, STACK_SLOT_PSSCR(r1)
1739 ld r7, STACK_SLOT_PID(r1)
1740 ld r8, STACK_SLOT_IAMR(r1)
1742 mtspr SPRN_PSSCR, r6
1745 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1747 #ifdef CONFIG_PPC_RADIX_MMU
1749 * Are we running hash or radix ?
1753 /* Radix: Handle the case where the guest used an illegal PID */
1754 LOAD_REG_ADDR(r4, mmu_base_pid)
1755 lwz r3, VCPU_GUEST_PID(r9)
1761 * Illegal PID, the HW might have prefetched and cached in the TLB
1762 * some translations for the LPID 0 / guest PID combination which
1763 * Linux doesn't know about, so we need to flush that PID out of
1764 * the TLB. First we need to set LPIDR to 0 so tlbiel applies to
1765 * the right context.
1771 /* Then do a congruence class local flush */
1773 lwz r0,KVM_TLB_SETS(r6)
1775 li r7,0x400 /* IS field = 0b01 */
1777 sldi r0,r3,32 /* RS has PID */
1778 1: PPC_TLBIEL(7,0,2,1,1) /* RIC=2, PRS=1, R=1 */
1783 2: /* Flush the ERAT on radix P9 DD1 guest exit */
1786 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
1788 #endif /* CONFIG_PPC_RADIX_MMU */
1790 /* Hash: clear out SLB */
1797 * POWER7/POWER8 guest -> host partition switch code.
1798 * We don't have to lock against tlbies but we do
1799 * have to coordinate the hardware threads.
1801 kvmhv_switch_to_host:
1802 /* Secondary threads wait for primary to do partition switch */
1803 ld r5,HSTATE_KVM_VCORE(r13)
1804 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1805 lbz r3,HSTATE_PTID(r13)
1809 13: lbz r3,VCORE_IN_GUEST(r5)
1815 /* Primary thread waits for all the secondaries to exit guest */
1816 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1817 rlwinm r0,r3,32-8,0xff
1823 /* Did we actually switch to the guest at all? */
1824 lbz r6, VCORE_IN_GUEST(r5)
1828 /* Primary thread switches back to host partition */
1829 lwz r7,KVM_HOST_LPID(r4)
1831 ld r6,KVM_HOST_SDR1(r4)
1832 li r8,LPID_RSVD /* switch to reserved LPID */
1835 mtspr SPRN_SDR1,r6 /* switch to host page table */
1836 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1841 /* DPDES and VTB are shared between threads */
1842 mfspr r7, SPRN_DPDES
1844 std r7, VCORE_DPDES(r5)
1845 std r8, VCORE_VTB(r5)
1846 /* clear DPDES so we don't get guest doorbells in the host */
1848 mtspr SPRN_DPDES, r8
1849 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1851 /* If HMI, call kvmppc_realmode_hmi_handler() */
1852 cmpwi r12, BOOK3S_INTERRUPT_HMI
1854 bl kvmppc_realmode_hmi_handler
1856 li r12, BOOK3S_INTERRUPT_HMI
1858 * At this point kvmppc_realmode_hmi_handler would have resync-ed
1859 * the TB. Hence it is not required to subtract guest timebase
1860 * offset from timebase. So, skip it.
1862 * Also, do not call kvmppc_subcore_exit_guest() because it has
1863 * been invoked as part of kvmppc_realmode_hmi_handler().
1868 /* Subtract timebase offset from timebase */
1869 ld r8,VCORE_TB_OFFSET(r5)
1872 mftb r6 /* current guest timebase */
1874 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1875 mftb r7 /* check if lower 24 bits overflowed */
1880 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1883 17: bl kvmppc_subcore_exit_guest
1885 30: ld r5,HSTATE_KVM_VCORE(r13)
1886 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1889 ld r0, VCORE_PCR(r5)
1895 /* Signal secondary CPUs to continue */
1896 stb r0,VCORE_IN_GUEST(r5)
1897 19: lis r8,0x7fff /* MAX_INT@h */
1900 16: ld r8,KVM_HOST_LPCR(r4)
1904 /* load host SLB entries */
1905 BEGIN_MMU_FTR_SECTION
1907 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
1908 ld r8,PACA_SLBSHADOWPTR(r13)
1910 .rept SLB_NUM_BOLTED
1911 li r3, SLBSHADOW_SAVEAREA
1915 andis. r7,r5,SLB_ESID_V@h
1921 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1922 /* Finish timing, if we have a vcpu */
1923 ld r4, HSTATE_KVM_VCPU(r13)
1927 bl kvmhv_accumulate_time
1930 /* Unset guest mode */
1931 li r0, KVM_GUEST_MODE_NONE
1932 stb r0, HSTATE_IN_GUEST(r13)
1934 ld r0, SFS+PPC_LR_STKOFF(r1)
1940 * Check whether an HDSI is an HPTE not found fault or something else.
1941 * If it is an HPTE not found fault that is due to the guest accessing
1942 * a page that they have mapped but which we have paged out, then
1943 * we continue on with the guest exit path. In all other cases,
1944 * reflect the HDSI to the guest as a DSI.
1948 lbz r0, KVM_RADIX(r3)
1951 mfspr r6, SPRN_HDSISR
1952 bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */
1953 /* HPTE not found fault or protection fault? */
1954 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1955 beq 1f /* if not, send it to the guest */
1956 andi. r0, r11, MSR_DR /* data relocation enabled? */
1959 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
1961 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1963 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1964 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
1965 bne 7f /* if no SLB entry found */
1966 4: std r4, VCPU_FAULT_DAR(r9)
1967 stw r6, VCPU_FAULT_DSISR(r9)
1969 /* Search the hash table. */
1970 mr r3, r9 /* vcpu pointer */
1971 li r7, 1 /* data fault */
1972 bl kvmppc_hpte_hv_fault
1973 ld r9, HSTATE_KVM_VCPU(r13)
1975 ld r11, VCPU_MSR(r9)
1976 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1977 cmpdi r3, 0 /* retry the instruction */
1979 cmpdi r3, -1 /* handle in kernel mode */
1981 cmpdi r3, -2 /* MMIO emulation; need instr word */
1984 /* Synthesize a DSI (or DSegI) for the guest */
1985 ld r4, VCPU_FAULT_DAR(r9)
1987 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
1988 mtspr SPRN_DSISR, r6
1989 7: mtspr SPRN_DAR, r4
1990 mtspr SPRN_SRR0, r10
1991 mtspr SPRN_SRR1, r11
1993 bl kvmppc_msr_interrupt
1994 fast_interrupt_c_return:
1995 6: ld r7, VCPU_CTR(r9)
2002 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
2003 ld r5, KVM_VRMA_SLB_V(r5)
2006 /* If this is for emulated MMIO, load the instruction word */
2007 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
2009 /* Set guest mode to 'jump over instruction' so if lwz faults
2010 * we'll just continue at the next IP. */
2011 li r0, KVM_GUEST_MODE_SKIP
2012 stb r0, HSTATE_IN_GUEST(r13)
2014 /* Do the access with MSR:DR enabled */
2016 ori r4, r3, MSR_DR /* Enable paging for data */
2021 /* Store the result */
2022 stw r8, VCPU_LAST_INST(r9)
2024 /* Unset guest mode. */
2025 li r0, KVM_GUEST_MODE_HOST_HV
2026 stb r0, HSTATE_IN_GUEST(r13)
2030 std r4, VCPU_FAULT_DAR(r9)
2031 stw r6, VCPU_FAULT_DSISR(r9)
2034 std r5, VCPU_FAULT_GPA(r9)
2038 * Similarly for an HISI, reflect it to the guest as an ISI unless
2039 * it is an HPTE not found fault for a page that we have paged out.
2043 lbz r0, KVM_RADIX(r3)
2045 bne .Lradix_hisi /* for radix, just save ASDR */
2046 andis. r0, r11, SRR1_ISI_NOPT@h
2048 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
2051 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2053 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2055 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2056 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
2057 bne 7f /* if no SLB entry found */
2059 /* Search the hash table. */
2060 mr r3, r9 /* vcpu pointer */
2063 li r7, 0 /* instruction fault */
2064 bl kvmppc_hpte_hv_fault
2065 ld r9, HSTATE_KVM_VCPU(r13)
2067 ld r11, VCPU_MSR(r9)
2068 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
2069 cmpdi r3, 0 /* retry the instruction */
2070 beq fast_interrupt_c_return
2071 cmpdi r3, -1 /* handle in kernel mode */
2074 /* Synthesize an ISI (or ISegI) for the guest */
2076 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
2077 7: mtspr SPRN_SRR0, r10
2078 mtspr SPRN_SRR1, r11
2080 bl kvmppc_msr_interrupt
2081 b fast_interrupt_c_return
2083 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
2084 ld r5, KVM_VRMA_SLB_V(r6)
2088 * Try to handle an hcall in real mode.
2089 * Returns to the guest if we handle it, or continues on up to
2090 * the kernel if we can't (i.e. if we don't have a handler for
2091 * it, or if the handler returns H_TOO_HARD).
2093 * r5 - r8 contain hcall args,
2094 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
2096 hcall_try_real_mode:
2097 ld r3,VCPU_GPR(R3)(r9)
2099 /* sc 1 from userspace - reflect to guest syscall */
2100 bne sc_1_fast_return
2102 cmpldi r3,hcall_real_table_end - hcall_real_table
2104 /* See if this hcall is enabled for in-kernel handling */
2106 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
2107 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
2109 ld r0, KVM_ENABLED_HCALLS(r4)
2110 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
2114 /* Get pointer to handler, if any, and call it */
2115 LOAD_REG_ADDR(r4, hcall_real_table)
2121 mr r3,r9 /* get vcpu pointer */
2122 ld r4,VCPU_GPR(R4)(r9)
2125 beq hcall_real_fallback
2126 ld r4,HSTATE_KVM_VCPU(r13)
2127 std r3,VCPU_GPR(R3)(r4)
2135 li r10, BOOK3S_INTERRUPT_SYSCALL
2136 bl kvmppc_msr_interrupt
2140 /* We've attempted a real mode hcall, but it's punted it back
2141 * to userspace. We need to restore some clobbered volatiles
2142 * before resuming the pass-it-to-qemu path */
2143 hcall_real_fallback:
2144 li r12,BOOK3S_INTERRUPT_SYSCALL
2145 ld r9, HSTATE_KVM_VCPU(r13)
2149 .globl hcall_real_table
2151 .long 0 /* 0 - unused */
2152 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
2153 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
2154 .long DOTSYM(kvmppc_h_read) - hcall_real_table
2155 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
2156 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
2157 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
2158 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
2159 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
2160 .long 0 /* 0x24 - H_SET_SPRG0 */
2161 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
2176 #ifdef CONFIG_KVM_XICS
2177 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
2178 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
2179 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
2180 .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table
2181 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
2183 .long 0 /* 0x64 - H_EOI */
2184 .long 0 /* 0x68 - H_CPPR */
2185 .long 0 /* 0x6c - H_IPI */
2186 .long 0 /* 0x70 - H_IPOLL */
2187 .long 0 /* 0x74 - H_XIRR */
2215 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
2216 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
2232 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
2236 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2237 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
2238 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
2350 #ifdef CONFIG_KVM_XICS
2351 .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table
2353 .long 0 /* 0x2fc - H_XIRR_X*/
2355 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2356 .globl hcall_real_table_end
2357 hcall_real_table_end:
2359 _GLOBAL(kvmppc_h_set_xdabr)
2360 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2362 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2365 6: li r3, H_PARAMETER
2368 _GLOBAL(kvmppc_h_set_dabr)
2369 li r5, DABRX_USER | DABRX_KERNEL
2373 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2374 std r4,VCPU_DABR(r3)
2375 stw r5, VCPU_DABRX(r3)
2376 mtspr SPRN_DABRX, r5
2377 /* Work around P7 bug where DABR can get corrupted on mtspr */
2378 1: mtspr SPRN_DABR,r4
2386 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2387 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2388 rlwimi r5, r4, 2, DAWRX_WT
2390 std r4, VCPU_DAWR(r3)
2391 std r5, VCPU_DAWRX(r3)
2393 mtspr SPRN_DAWRX, r5
2397 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2399 std r11,VCPU_MSR(r3)
2401 stb r0,VCPU_CEDED(r3)
2402 sync /* order setting ceded vs. testing prodded */
2403 lbz r5,VCPU_PRODDED(r3)
2405 bne kvm_cede_prodded
2406 li r12,0 /* set trap to 0 to say hcall is handled */
2407 stw r12,VCPU_TRAP(r3)
2409 std r0,VCPU_GPR(R3)(r3)
2412 * Set our bit in the bitmask of napping threads unless all the
2413 * other threads are already napping, in which case we send this
2416 ld r5,HSTATE_KVM_VCORE(r13)
2417 lbz r6,HSTATE_PTID(r13)
2418 lwz r8,VCORE_ENTRY_EXIT(r5)
2422 addi r6,r5,VCORE_NAPPING_THREADS
2429 /* order napping_threads update vs testing entry_exit_map */
2432 stb r0,HSTATE_NAPPING(r13)
2433 lwz r7,VCORE_ENTRY_EXIT(r5)
2435 bge 33f /* another thread already exiting */
2438 * Although not specifically required by the architecture, POWER7
2439 * preserves the following registers in nap mode, even if an SMT mode
2440 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2441 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2443 /* Save non-volatile GPRs */
2444 std r14, VCPU_GPR(R14)(r3)
2445 std r15, VCPU_GPR(R15)(r3)
2446 std r16, VCPU_GPR(R16)(r3)
2447 std r17, VCPU_GPR(R17)(r3)
2448 std r18, VCPU_GPR(R18)(r3)
2449 std r19, VCPU_GPR(R19)(r3)
2450 std r20, VCPU_GPR(R20)(r3)
2451 std r21, VCPU_GPR(R21)(r3)
2452 std r22, VCPU_GPR(R22)(r3)
2453 std r23, VCPU_GPR(R23)(r3)
2454 std r24, VCPU_GPR(R24)(r3)
2455 std r25, VCPU_GPR(R25)(r3)
2456 std r26, VCPU_GPR(R26)(r3)
2457 std r27, VCPU_GPR(R27)(r3)
2458 std r28, VCPU_GPR(R28)(r3)
2459 std r29, VCPU_GPR(R29)(r3)
2460 std r30, VCPU_GPR(R30)(r3)
2461 std r31, VCPU_GPR(R31)(r3)
2466 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2468 ld r9, HSTATE_KVM_VCPU(r13)
2470 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2474 * Set DEC to the smaller of DEC and HDEC, so that we wake
2475 * no later than the end of our timeslice (HDEC interrupts
2476 * don't wake us from nap).
2482 /* On P9 check whether the guest has large decrementer mode enabled */
2483 ld r6, HSTATE_KVM_VCORE(r13)
2484 ld r6, VCORE_LPCR(r6)
2485 andis. r6, r6, LPCR_LD@h
2487 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2494 /* save expiry time of guest decrementer */
2496 ld r4, HSTATE_KVM_VCPU(r13)
2497 ld r5, HSTATE_KVM_VCORE(r13)
2498 ld r6, VCORE_TB_OFFSET(r5)
2499 subf r3, r6, r3 /* convert to host TB value */
2500 std r3, VCPU_DEC_EXPIRES(r4)
2502 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2503 ld r4, HSTATE_KVM_VCPU(r13)
2504 addi r3, r4, VCPU_TB_CEDE
2505 bl kvmhv_accumulate_time
2508 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2511 * Take a nap until a decrementer or external or doobell interrupt
2512 * occurs, with PECE1 and PECE0 set in LPCR.
2513 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2514 * Also clear the runlatch bit before napping.
2517 mfspr r0, SPRN_CTRLF
2519 mtspr SPRN_CTRLT, r0
2523 stb r0,HSTATE_HWTHREAD_REQ(r13)
2524 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
2526 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2528 ori r5, r5, LPCR_PECEDH
2529 rlwimi r5, r3, 0, LPCR_PECEDP
2530 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2532 kvm_nap_sequence: /* desired LPCR value in r5 */
2535 * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset)
2536 * enable state loss = 1 (allow SMT mode switch)
2537 * requested level = 0 (just stop dispatching)
2539 lis r3, (PSSCR_EC | PSSCR_ESL)@h
2540 mtspr SPRN_PSSCR, r3
2541 /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */
2542 li r4, LPCR_PECE_HVEE@higher
2545 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2549 std r0, HSTATE_SCRATCH0(r13)
2551 ld r0, HSTATE_SCRATCH0(r13)
2558 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
2567 /* get vcpu pointer */
2568 ld r4, HSTATE_KVM_VCPU(r13)
2570 /* Woken by external or decrementer interrupt */
2571 ld r1, HSTATE_HOST_R1(r13)
2573 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2574 addi r3, r4, VCPU_TB_RMINTR
2575 bl kvmhv_accumulate_time
2578 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2580 bl kvmppc_restore_tm
2581 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2584 /* load up FP state */
2587 /* Restore guest decrementer */
2588 ld r3, VCPU_DEC_EXPIRES(r4)
2589 ld r5, HSTATE_KVM_VCORE(r13)
2590 ld r6, VCORE_TB_OFFSET(r5)
2591 add r3, r3, r6 /* convert host TB to guest TB value */
2597 ld r14, VCPU_GPR(R14)(r4)
2598 ld r15, VCPU_GPR(R15)(r4)
2599 ld r16, VCPU_GPR(R16)(r4)
2600 ld r17, VCPU_GPR(R17)(r4)
2601 ld r18, VCPU_GPR(R18)(r4)
2602 ld r19, VCPU_GPR(R19)(r4)
2603 ld r20, VCPU_GPR(R20)(r4)
2604 ld r21, VCPU_GPR(R21)(r4)
2605 ld r22, VCPU_GPR(R22)(r4)
2606 ld r23, VCPU_GPR(R23)(r4)
2607 ld r24, VCPU_GPR(R24)(r4)
2608 ld r25, VCPU_GPR(R25)(r4)
2609 ld r26, VCPU_GPR(R26)(r4)
2610 ld r27, VCPU_GPR(R27)(r4)
2611 ld r28, VCPU_GPR(R28)(r4)
2612 ld r29, VCPU_GPR(R29)(r4)
2613 ld r30, VCPU_GPR(R30)(r4)
2614 ld r31, VCPU_GPR(R31)(r4)
2616 /* Check the wake reason in SRR1 to see why we got here */
2617 bl kvmppc_check_wake_reason
2620 * Restore volatile registers since we could have called a
2621 * C routine in kvmppc_check_wake_reason
2623 * r3 tells us whether we need to return to host or not
2624 * WARNING: it gets checked further down:
2625 * should not modify r3 until this check is done.
2627 ld r4, HSTATE_KVM_VCPU(r13)
2629 /* clear our bit in vcore->napping_threads */
2630 34: ld r5,HSTATE_KVM_VCORE(r13)
2631 lbz r7,HSTATE_PTID(r13)
2634 addi r6,r5,VCORE_NAPPING_THREADS
2640 stb r0,HSTATE_NAPPING(r13)
2642 /* See if the wake reason saved in r3 means we need to exit */
2643 stw r12, VCPU_TRAP(r4)
2648 /* see if any other thread is already exiting */
2649 lwz r0,VCORE_ENTRY_EXIT(r5)
2653 b kvmppc_cede_reentry /* if not go back to guest */
2655 /* cede when already previously prodded case */
2658 stb r0,VCPU_PRODDED(r3)
2659 sync /* order testing prodded vs. clearing ceded */
2660 stb r0,VCPU_CEDED(r3)
2664 /* we've ceded but we want to give control to the host */
2666 ld r9, HSTATE_KVM_VCPU(r13)
2669 /* Try to handle a machine check in real mode */
2670 machine_check_realmode:
2671 mr r3, r9 /* get vcpu pointer */
2672 bl kvmppc_realmode_machine_check
2674 ld r9, HSTATE_KVM_VCPU(r13)
2675 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2677 * For the guest that is FWNMI capable, deliver all the MCE errors
2678 * (handled/unhandled) by exiting the guest with KVM_EXIT_NMI exit
2679 * reason. This new approach injects machine check errors in guest
2680 * address space to guest with additional information in the form
2681 * of RTAS event, thus enabling guest kernel to suitably handle
2684 * For the guest that is not FWNMI capable (old QEMU) fallback
2685 * to old behaviour for backward compatibility:
2686 * Deliver unhandled/fatal (e.g. UE) MCE errors to guest either
2687 * through machine check interrupt (set HSRR0 to 0x200).
2688 * For handled errors (no-fatal), just go back to guest execution
2689 * with current HSRR0.
2690 * if we receive machine check with MSR(RI=0) then deliver it to
2691 * guest as machine check causing guest to crash.
2693 ld r11, VCPU_MSR(r9)
2694 rldicl. r0, r11, 64-MSR_HV_LG, 63 /* check if it happened in HV mode */
2695 bne mc_cont /* if so, exit to host */
2696 /* Check if guest is capable of handling NMI exit */
2697 ld r10, VCPU_KVM(r9)
2698 lbz r10, KVM_FWNMI(r10)
2699 cmpdi r10, 1 /* FWNMI capable? */
2700 beq mc_cont /* if so, exit with KVM_EXIT_NMI. */
2702 /* if not, fall through for backward compatibility. */
2703 andi. r10, r11, MSR_RI /* check for unrecoverable exception */
2704 beq 1f /* Deliver a machine check to guest */
2706 cmpdi r3, 0 /* Did we handle MCE ? */
2707 bne 2f /* Continue guest execution. */
2708 /* If not, deliver a machine check. SRR0/1 are already set */
2709 1: li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2710 bl kvmppc_msr_interrupt
2711 2: b fast_interrupt_c_return
2714 * Check the reason we woke from nap, and take appropriate action.
2716 * 0 if nothing needs to be done
2717 * 1 if something happened that needs to be handled by the host
2718 * -1 if there was a guest wakeup (IPI or msgsnd)
2719 * -2 if we handled a PCI passthrough interrupt (returned by
2720 * kvmppc_read_intr only)
2722 * Also sets r12 to the interrupt vector for any interrupt that needs
2723 * to be handled now by the host (0x500 for external interrupt), or zero.
2724 * Modifies all volatile registers (since it may call a C function).
2725 * This routine calls kvmppc_read_intr, a C function, if an external
2726 * interrupt is pending.
2728 kvmppc_check_wake_reason:
2731 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2733 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2734 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2735 cmpwi r6, 8 /* was it an external interrupt? */
2736 beq 7f /* if so, see what it was */
2739 cmpwi r6, 6 /* was it the decrementer? */
2742 cmpwi r6, 5 /* privileged doorbell? */
2744 cmpwi r6, 3 /* hypervisor doorbell? */
2746 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2747 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2749 li r3, 1 /* anything else, return 1 */
2752 /* hypervisor doorbell */
2753 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2756 * Clear the doorbell as we will invoke the handler
2757 * explicitly in the guest exit path.
2759 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2761 /* see if it's a host IPI */
2763 lbz r0, HSTATE_HOST_IPI(r13)
2766 /* if not, return -1 */
2770 /* Woken up due to Hypervisor maintenance interrupt */
2771 4: li r12, BOOK3S_INTERRUPT_HMI
2775 /* external interrupt - create a stack frame so we can call C */
2777 std r0, PPC_LR_STKOFF(r1)
2778 stdu r1, -PPC_MIN_STKFRM(r1)
2781 li r12, BOOK3S_INTERRUPT_EXTERNAL
2786 * Return code of 2 means PCI passthrough interrupt, but
2787 * we need to return back to host to complete handling the
2788 * interrupt. Trap reason is expected in r12 by guest
2791 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2793 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
2794 addi r1, r1, PPC_MIN_STKFRM
2799 * Save away FP, VMX and VSX registers.
2801 * N.B. r30 and r31 are volatile across this function,
2802 * thus it is not callable from C.
2809 #ifdef CONFIG_ALTIVEC
2811 oris r8,r8,MSR_VEC@h
2812 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2816 oris r8,r8,MSR_VSX@h
2817 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2820 addi r3,r3,VCPU_FPRS
2822 #ifdef CONFIG_ALTIVEC
2824 addi r3,r31,VCPU_VRS
2826 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2828 mfspr r6,SPRN_VRSAVE
2829 stw r6,VCPU_VRSAVE(r31)
2834 * Load up FP, VMX and VSX registers
2836 * N.B. r30 and r31 are volatile across this function,
2837 * thus it is not callable from C.
2844 #ifdef CONFIG_ALTIVEC
2846 oris r8,r8,MSR_VEC@h
2847 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2851 oris r8,r8,MSR_VSX@h
2852 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2855 addi r3,r4,VCPU_FPRS
2857 #ifdef CONFIG_ALTIVEC
2859 addi r3,r31,VCPU_VRS
2861 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2863 lwz r7,VCPU_VRSAVE(r31)
2864 mtspr SPRN_VRSAVE,r7
2869 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2871 * Save transactional state and TM-related registers.
2872 * Called with r9 pointing to the vcpu struct.
2873 * This can modify all checkpointed registers, but
2874 * restores r1, r2 and r9 (vcpu pointer) before exit.
2878 std r0, PPC_LR_STKOFF(r1)
2883 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
2887 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
2888 beq 1f /* TM not active in guest. */
2890 std r1, HSTATE_HOST_R1(r13)
2891 li r3, TM_CAUSE_KVM_RESCHED
2893 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
2897 /* All GPRs are volatile at this point. */
2900 /* Temporarily store r13 and r9 so we have some regs to play with */
2903 std r9, PACATMSCRATCH(r13)
2904 ld r9, HSTATE_KVM_VCPU(r13)
2906 /* Get a few more GPRs free. */
2907 std r29, VCPU_GPRS_TM(29)(r9)
2908 std r30, VCPU_GPRS_TM(30)(r9)
2909 std r31, VCPU_GPRS_TM(31)(r9)
2911 /* Save away PPR and DSCR soon so don't run with user values. */
2914 mfspr r30, SPRN_DSCR
2915 ld r29, HSTATE_DSCR(r13)
2916 mtspr SPRN_DSCR, r29
2918 /* Save all but r9, r13 & r29-r31 */
2921 .if (reg != 9) && (reg != 13)
2922 std reg, VCPU_GPRS_TM(reg)(r9)
2926 /* ... now save r13 */
2928 std r4, VCPU_GPRS_TM(13)(r9)
2929 /* ... and save r9 */
2930 ld r4, PACATMSCRATCH(r13)
2931 std r4, VCPU_GPRS_TM(9)(r9)
2933 /* Reload stack pointer and TOC. */
2934 ld r1, HSTATE_HOST_R1(r13)
2937 /* Set MSR RI now we have r1 and r13 back. */
2941 /* Save away checkpinted SPRs. */
2942 std r31, VCPU_PPR_TM(r9)
2943 std r30, VCPU_DSCR_TM(r9)
2950 std r5, VCPU_LR_TM(r9)
2951 stw r6, VCPU_CR_TM(r9)
2952 std r7, VCPU_CTR_TM(r9)
2953 std r8, VCPU_AMR_TM(r9)
2954 std r10, VCPU_TAR_TM(r9)
2955 std r11, VCPU_XER_TM(r9)
2957 /* Restore r12 as trap number. */
2958 lwz r12, VCPU_TRAP(r9)
2961 addi r3, r9, VCPU_FPRS_TM
2963 addi r3, r9, VCPU_VRS_TM
2965 mfspr r6, SPRN_VRSAVE
2966 stw r6, VCPU_VRSAVE_TM(r9)
2969 * We need to save these SPRs after the treclaim so that the software
2970 * error code is recorded correctly in the TEXASR. Also the user may
2971 * change these outside of a transaction, so they must always be
2974 mfspr r5, SPRN_TFHAR
2975 mfspr r6, SPRN_TFIAR
2976 mfspr r7, SPRN_TEXASR
2977 std r5, VCPU_TFHAR(r9)
2978 std r6, VCPU_TFIAR(r9)
2979 std r7, VCPU_TEXASR(r9)
2981 ld r0, PPC_LR_STKOFF(r1)
2986 * Restore transactional state and TM-related registers.
2987 * Called with r4 pointing to the vcpu struct.
2988 * This potentially modifies all checkpointed registers.
2989 * It restores r1, r2, r4 from the PACA.
2993 std r0, PPC_LR_STKOFF(r1)
2995 /* Turn on TM/FP/VSX/VMX so we can restore them. */
3001 oris r5, r5, (MSR_VEC | MSR_VSX)@h
3005 * The user may change these outside of a transaction, so they must
3006 * always be context switched.
3008 ld r5, VCPU_TFHAR(r4)
3009 ld r6, VCPU_TFIAR(r4)
3010 ld r7, VCPU_TEXASR(r4)
3011 mtspr SPRN_TFHAR, r5
3012 mtspr SPRN_TFIAR, r6
3013 mtspr SPRN_TEXASR, r7
3016 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
3017 beqlr /* TM not active in guest */
3018 std r1, HSTATE_HOST_R1(r13)
3020 /* Make sure the failure summary is set, otherwise we'll program check
3021 * when we trechkpt. It's possible that this might have been not set
3022 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
3025 oris r7, r7, (TEXASR_FS)@h
3026 mtspr SPRN_TEXASR, r7
3029 * We need to load up the checkpointed state for the guest.
3030 * We need to do this early as it will blow away any GPRs, VSRs and
3035 addi r3, r31, VCPU_FPRS_TM
3037 addi r3, r31, VCPU_VRS_TM
3040 lwz r7, VCPU_VRSAVE_TM(r4)
3041 mtspr SPRN_VRSAVE, r7
3043 ld r5, VCPU_LR_TM(r4)
3044 lwz r6, VCPU_CR_TM(r4)
3045 ld r7, VCPU_CTR_TM(r4)
3046 ld r8, VCPU_AMR_TM(r4)
3047 ld r9, VCPU_TAR_TM(r4)
3048 ld r10, VCPU_XER_TM(r4)
3057 * Load up PPR and DSCR values but don't put them in the actual SPRs
3058 * till the last moment to avoid running with userspace PPR and DSCR for
3061 ld r29, VCPU_DSCR_TM(r4)
3062 ld r30, VCPU_PPR_TM(r4)
3064 std r2, PACATMSCRATCH(r13) /* Save TOC */
3066 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
3070 /* Load GPRs r0-r28 */
3073 ld reg, VCPU_GPRS_TM(reg)(r31)
3077 mtspr SPRN_DSCR, r29
3080 /* Load final GPRs */
3081 ld 29, VCPU_GPRS_TM(29)(r31)
3082 ld 30, VCPU_GPRS_TM(30)(r31)
3083 ld 31, VCPU_GPRS_TM(31)(r31)
3085 /* TM checkpointed state is now setup. All GPRs are now volatile. */
3088 /* Now let's get back the state we need. */
3091 ld r29, HSTATE_DSCR(r13)
3092 mtspr SPRN_DSCR, r29
3093 ld r4, HSTATE_KVM_VCPU(r13)
3094 ld r1, HSTATE_HOST_R1(r13)
3095 ld r2, PACATMSCRATCH(r13)
3097 /* Set the MSR RI since we have our registers back. */
3101 ld r0, PPC_LR_STKOFF(r1)
3107 * We come here if we get any exception or interrupt while we are
3108 * executing host real mode code while in guest MMU context.
3109 * For now just spin, but we should do something better.
3111 kvmppc_bad_host_intr:
3115 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
3116 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
3117 * r11 has the guest MSR value (in/out)
3118 * r9 has a vcpu pointer (in)
3119 * r0 is used as a scratch register
3121 kvmppc_msr_interrupt:
3122 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
3123 cmpwi r0, 2 /* Check if we are in transactional state.. */
3124 ld r11, VCPU_INTR_MSR(r9)
3126 /* ... if transactional, change to suspended */
3128 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
3132 * This works around a hardware bug on POWER8E processors, where
3133 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
3134 * performance monitor interrupt. Instead, when we need to have
3135 * an interrupt pending, we have to arrange for a counter to overflow.
3139 mtspr SPRN_MMCR2, r3
3140 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
3141 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
3142 mtspr SPRN_MMCR0, r3
3149 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
3151 * Start timing an activity
3152 * r3 = pointer to time accumulation struct, r4 = vcpu
3155 ld r5, HSTATE_KVM_VCORE(r13)
3156 lbz r6, VCORE_IN_GUEST(r5)
3158 beq 5f /* if in guest, need to */
3159 ld r6, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
3162 std r3, VCPU_CUR_ACTIVITY(r4)
3163 std r5, VCPU_ACTIVITY_START(r4)
3167 * Accumulate time to one activity and start another.
3168 * r3 = pointer to new time accumulation struct, r4 = vcpu
3170 kvmhv_accumulate_time:
3171 ld r5, HSTATE_KVM_VCORE(r13)
3172 lbz r8, VCORE_IN_GUEST(r5)
3174 beq 4f /* if in guest, need to */
3175 ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
3176 4: ld r5, VCPU_CUR_ACTIVITY(r4)
3177 ld r6, VCPU_ACTIVITY_START(r4)
3178 std r3, VCPU_CUR_ACTIVITY(r4)
3181 std r7, VCPU_ACTIVITY_START(r4)
3185 ld r8, TAS_SEQCOUNT(r5)
3188 std r8, TAS_SEQCOUNT(r5)
3190 ld r7, TAS_TOTAL(r5)
3192 std r7, TAS_TOTAL(r5)
3198 3: std r3, TAS_MIN(r5)
3204 std r8, TAS_SEQCOUNT(r5)