3 * Common boot and setup code.
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <linux/export.h>
14 #include <linux/string.h>
15 #include <linux/sched.h>
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/reboot.h>
19 #include <linux/delay.h>
20 #include <linux/initrd.h>
21 #include <linux/seq_file.h>
22 #include <linux/ioport.h>
23 #include <linux/console.h>
24 #include <linux/utsname.h>
25 #include <linux/tty.h>
26 #include <linux/root_dev.h>
27 #include <linux/notifier.h>
28 #include <linux/cpu.h>
29 #include <linux/unistd.h>
30 #include <linux/serial.h>
31 #include <linux/serial_8250.h>
32 #include <linux/bootmem.h>
33 #include <linux/pci.h>
34 #include <linux/lockdep.h>
35 #include <linux/memblock.h>
36 #include <linux/memory.h>
37 #include <linux/nmi.h>
39 #include <asm/debugfs.h>
41 #include <asm/kdump.h>
43 #include <asm/processor.h>
44 #include <asm/pgtable.h>
47 #include <asm/machdep.h>
50 #include <asm/cputable.h>
51 #include <asm/dt_cpu_ftrs.h>
52 #include <asm/sections.h>
53 #include <asm/btext.h>
54 #include <asm/nvram.h>
55 #include <asm/setup.h>
57 #include <asm/iommu.h>
58 #include <asm/serial.h>
59 #include <asm/cache.h>
62 #include <asm/firmware.h>
65 #include <asm/kexec.h>
66 #include <asm/code-patching.h>
67 #include <asm/livepatch.h>
69 #include <asm/cputhreads.h>
70 #include <asm/hw_irq.h>
71 #include <asm/feature-fixups.h>
76 #define DBG(fmt...) udbg_printf(fmt)
81 int spinning_secondaries;
84 struct ppc64_caches ppc64_caches = {
94 EXPORT_SYMBOL_GPL(ppc64_caches);
96 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
97 void __init setup_tlb_core_data(void)
101 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
103 for_each_possible_cpu(cpu) {
104 int first = cpu_first_thread_sibling(cpu);
107 * If we boot via kdump on a non-primary thread,
108 * make sure we point at the thread that actually
111 if (cpu_first_thread_sibling(boot_cpuid) == first)
114 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd;
117 * If we have threads, we need either tlbsrx.
118 * or e6500 tablewalk mode, or else TLB handlers
119 * will be racy and could produce duplicate entries.
120 * Should we panic instead?
122 WARN_ONCE(smt_enabled_at_boot >= 2 &&
123 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
124 book3e_htw_mode != PPC_HTW_E6500,
125 "%s: unsupported MMU configuration\n", __func__);
132 static char *smt_enabled_cmdline;
134 /* Look for ibm,smt-enabled OF option */
135 void __init check_smt_enabled(void)
137 struct device_node *dn;
138 const char *smt_option;
140 /* Default to enabling all threads */
141 smt_enabled_at_boot = threads_per_core;
143 /* Allow the command line to overrule the OF option */
144 if (smt_enabled_cmdline) {
145 if (!strcmp(smt_enabled_cmdline, "on"))
146 smt_enabled_at_boot = threads_per_core;
147 else if (!strcmp(smt_enabled_cmdline, "off"))
148 smt_enabled_at_boot = 0;
153 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
155 smt_enabled_at_boot =
156 min(threads_per_core, smt);
159 dn = of_find_node_by_path("/options");
161 smt_option = of_get_property(dn, "ibm,smt-enabled",
165 if (!strcmp(smt_option, "on"))
166 smt_enabled_at_boot = threads_per_core;
167 else if (!strcmp(smt_option, "off"))
168 smt_enabled_at_boot = 0;
176 /* Look for smt-enabled= cmdline option */
177 static int __init early_smt_enabled(char *p)
179 smt_enabled_cmdline = p;
182 early_param("smt-enabled", early_smt_enabled);
184 #endif /* CONFIG_SMP */
186 /** Fix up paca fields required for the boot cpu */
187 static void __init fixup_boot_paca(void)
189 /* The boot cpu is started */
190 get_paca()->cpu_start = 1;
191 /* Allow percpu accesses to work until we setup percpu data */
192 get_paca()->data_offset = 0;
193 /* Mark interrupts disabled in PACA */
194 irq_soft_mask_set(IRQS_DISABLED);
197 static void __init configure_exceptions(void)
200 * Setup the trampolines from the lowmem exception vectors
201 * to the kdump kernel when not using a relocatable kernel.
203 setup_kdump_trampoline();
205 /* Under a PAPR hypervisor, we need hypercalls */
206 if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
207 /* Enable AIL if possible */
208 pseries_enable_reloc_on_exc();
211 * Tell the hypervisor that we want our exceptions to
212 * be taken in little endian mode.
214 * We don't call this for big endian as our calling convention
215 * makes us always enter in BE, and the call may fail under
216 * some circumstances with kdump.
218 #ifdef __LITTLE_ENDIAN__
219 pseries_little_endian_exceptions();
222 /* Set endian mode using OPAL */
223 if (firmware_has_feature(FW_FEATURE_OPAL))
224 opal_configure_cores();
226 /* AIL on native is done in cpu_ready_for_interrupts() */
230 static void cpu_ready_for_interrupts(void)
233 * Enable AIL if supported, and we are in hypervisor mode. This
234 * is called once for every processor.
236 * If we are not in hypervisor mode the job is done once for
237 * the whole partition in configure_exceptions().
239 if (cpu_has_feature(CPU_FTR_HVMODE) &&
240 cpu_has_feature(CPU_FTR_ARCH_207S)) {
241 unsigned long lpcr = mfspr(SPRN_LPCR);
242 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
246 * Fixup HFSCR:TM based on CPU features. The bit is set by our
247 * early asm init because at that point we haven't updated our
248 * CPU features from firmware and device-tree. Here we have,
251 if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP))
252 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
254 /* Set IR and DR in PACA MSR */
255 get_paca()->kernel_msr = MSR_KERNEL;
258 unsigned long spr_default_dscr = 0;
260 void __init record_spr_defaults(void)
262 if (early_cpu_has_feature(CPU_FTR_DSCR))
263 spr_default_dscr = mfspr(SPRN_DSCR);
267 * Early initialization entry point. This is called by head.S
268 * with MMU translation disabled. We rely on the "feature" of
269 * the CPU that ignores the top 2 bits of the address in real
270 * mode so we can access kernel globals normally provided we
271 * only toy with things in the RMO region. From here, we do
272 * some early parsing of the device-tree to setup out MEMBLOCK
273 * data structures, and allocate & initialize the hash table
274 * and segment tables so we can start running with translation
277 * It is this function which will call the probe() callback of
278 * the various platform types and copy the matching one to the
279 * global ppc_md structure. Your platform can eventually do
280 * some very early initializations from the probe() routine, but
281 * this is not recommended, be very careful as, for example, the
282 * device-tree is not accessible via normal means at this point.
285 void __init early_setup(unsigned long dt_ptr)
287 static __initdata struct paca_struct boot_paca;
289 /* -------- printk is _NOT_ safe to use here ! ------- */
291 /* Try new device tree based feature discovery ... */
292 if (!dt_cpu_ftrs_init(__va(dt_ptr)))
293 /* Otherwise use the old style CPU table */
294 identify_cpu(0, mfspr(SPRN_PVR));
296 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
297 initialise_paca(&boot_paca, 0);
298 setup_paca(&boot_paca);
301 /* -------- printk is now safe to use ------- */
303 /* Enable early debugging if any specified (see udbg.h) */
306 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
309 * Do early initialization using the flattened device
310 * tree, such as retrieving the physical memory map or
311 * calculating/retrieving the hash table size.
313 early_init_devtree(__va(dt_ptr));
315 /* Now we know the logical id of our boot cpu, setup the paca. */
316 if (boot_cpuid != 0) {
317 /* Poison paca_ptrs[0] again if it's not the boot cpu */
318 memset(&paca_ptrs[0], 0x88, sizeof(paca_ptrs[0]));
320 setup_paca(paca_ptrs[boot_cpuid]);
324 * Configure exception handlers. This include setting up trampolines
325 * if needed, setting exception endian mode, etc...
327 configure_exceptions();
329 /* Apply all the dynamic patching */
330 apply_feature_fixups();
331 setup_feature_keys();
333 /* Initialize the hash table or TLB handling */
337 * After firmware and early platform setup code has set things up,
338 * we note the SPR values for configurable control/performance
339 * registers, and use those as initial defaults.
341 record_spr_defaults();
344 * At this point, we can let interrupts switch to virtual mode
345 * (the MMU has been setup), so adjust the MSR in the PACA to
346 * have IR and DR set and enable AIL if it exists
348 cpu_ready_for_interrupts();
351 * We enable ftrace here, but since we only support DYNAMIC_FTRACE, it
352 * will only actually get enabled on the boot cpu much later once
353 * ftrace itself has been initialized.
355 this_cpu_enable_ftrace();
357 DBG(" <- early_setup()\n");
359 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
361 * This needs to be done *last* (after the above DBG() even)
363 * Right after we return from this function, we turn on the MMU
364 * which means the real-mode access trick that btext does will
365 * no longer work, it needs to switch to using a real MMU
366 * mapping. This call will ensure that it does
369 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
373 void early_setup_secondary(void)
375 /* Mark interrupts disabled in PACA */
376 irq_soft_mask_set(IRQS_DISABLED);
378 /* Initialize the hash table or TLB handling */
379 early_init_mmu_secondary();
382 * At this point, we can let interrupts switch to virtual mode
383 * (the MMU has been setup), so adjust the MSR in the PACA to
384 * have IR and DR set.
386 cpu_ready_for_interrupts();
389 #endif /* CONFIG_SMP */
391 void panic_smp_self_stop(void)
399 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
400 static bool use_spinloop(void)
402 if (IS_ENABLED(CONFIG_PPC_BOOK3S)) {
404 * See comments in head_64.S -- not all platforms insert
405 * secondaries at __secondary_hold and wait at the spin
408 if (firmware_has_feature(FW_FEATURE_OPAL))
414 * When book3e boots from kexec, the ePAPR spin table does
417 return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
420 void smp_release_cpus(void)
428 DBG(" -> smp_release_cpus()\n");
430 /* All secondary cpus are spinning on a common spinloop, release them
431 * all now so they can start to spin on their individual paca
432 * spinloops. For non SMP kernels, the secondary cpus never get out
433 * of the common spinloop.
436 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
438 *ptr = ppc_function_entry(generic_secondary_smp_init);
440 /* And wait a bit for them to catch up */
441 for (i = 0; i < 100000; i++) {
444 if (spinning_secondaries == 0)
448 DBG("spinning_secondaries = %d\n", spinning_secondaries);
450 DBG(" <- smp_release_cpus()\n");
452 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
455 * Initialize some remaining members of the ppc64_caches and systemcfg
457 * (at least until we get rid of them completely). This is mostly some
458 * cache informations about the CPU that will be used by cache flush
459 * routines and/or provided to userland
462 static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
467 info->line_size = lsize;
468 info->block_size = bsize;
469 info->log_block_size = __ilog2(bsize);
471 info->blocks_per_page = PAGE_SIZE / bsize;
473 info->blocks_per_page = 0;
476 info->assoc = 0xffff;
478 info->assoc = size / (sets * lsize);
481 static bool __init parse_cache_info(struct device_node *np,
483 struct ppc_cache_info *info)
485 static const char *ipropnames[] __initdata = {
488 "i-cache-block-size",
491 static const char *dpropnames[] __initdata = {
494 "d-cache-block-size",
497 const char **propnames = icache ? ipropnames : dpropnames;
498 const __be32 *sizep, *lsizep, *bsizep, *setsp;
499 u32 size, lsize, bsize, sets;
504 lsize = bsize = cur_cpu_spec->dcache_bsize;
505 sizep = of_get_property(np, propnames[0], NULL);
507 size = be32_to_cpu(*sizep);
508 setsp = of_get_property(np, propnames[1], NULL);
510 sets = be32_to_cpu(*setsp);
511 bsizep = of_get_property(np, propnames[2], NULL);
512 lsizep = of_get_property(np, propnames[3], NULL);
516 lsize = be32_to_cpu(*lsizep);
518 bsize = be32_to_cpu(*bsizep);
519 if (sizep == NULL || bsizep == NULL || lsizep == NULL)
523 * OF is weird .. it represents fully associative caches
524 * as "1 way" which doesn't make much sense and doesn't
525 * leave room for direct mapped. We'll assume that 0
526 * in OF means direct mapped for that reason.
533 init_cache_info(info, size, lsize, bsize, sets);
538 void __init initialize_cache_info(void)
540 struct device_node *cpu = NULL, *l2, *l3 = NULL;
543 DBG(" -> initialize_cache_info()\n");
546 * All shipping POWER8 machines have a firmware bug that
547 * puts incorrect information in the device-tree. This will
548 * be (hopefully) fixed for future chips but for now hard
549 * code the values if we are running on one of these
551 pvr = PVR_VER(mfspr(SPRN_PVR));
552 if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
553 pvr == PVR_POWER8NVL) {
554 /* size lsize blk sets */
555 init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32);
556 init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64);
557 init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512);
558 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192);
560 cpu = of_find_node_by_type(NULL, "cpu");
563 * We're assuming *all* of the CPUs have the same
564 * d-cache and i-cache sizes... -Peter
567 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
568 DBG("Argh, can't find dcache properties !\n");
570 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
571 DBG("Argh, can't find icache properties !\n");
574 * Try to find the L2 and L3 if any. Assume they are
575 * unified and use the D-side properties.
577 l2 = of_find_next_cache_node(cpu);
580 parse_cache_info(l2, false, &ppc64_caches.l2);
581 l3 = of_find_next_cache_node(l2);
585 parse_cache_info(l3, false, &ppc64_caches.l3);
590 /* For use by binfmt_elf */
591 dcache_bsize = ppc64_caches.l1d.block_size;
592 icache_bsize = ppc64_caches.l1i.block_size;
594 cur_cpu_spec->dcache_bsize = dcache_bsize;
595 cur_cpu_spec->icache_bsize = icache_bsize;
597 DBG(" <- initialize_cache_info()\n");
601 * This returns the limit below which memory accesses to the linear
602 * mapping are guarnateed not to cause an architectural exception (e.g.,
603 * TLB or SLB miss fault).
605 * This is used to allocate PACAs and various interrupt stacks that
606 * that are accessed early in interrupt handlers that must not cause
607 * re-entrant interrupts.
609 __init u64 ppc64_bolted_size(void)
611 #ifdef CONFIG_PPC_BOOK3E
612 /* Freescale BookE bolts the entire linear mapping */
613 /* XXX: BookE ppc64_rma_limit setup seems to disagree? */
614 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E))
615 return linear_map_top;
616 /* Other BookE, we assume the first GB is bolted */
619 /* BookS radix, does not take faults on linear mapping */
620 if (early_radix_enabled())
623 /* BookS hash, the first segment is bolted */
624 if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT))
625 return 1UL << SID_SHIFT_1T;
626 return 1UL << SID_SHIFT;
630 static void *__init alloc_stack(unsigned long limit, int cpu)
634 pa = memblock_alloc_base_nid(THREAD_SIZE, THREAD_SIZE, limit,
635 early_cpu_to_node(cpu), MEMBLOCK_NONE);
637 pa = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
639 panic("cannot allocate stacks");
645 void __init irqstack_early_init(void)
647 u64 limit = ppc64_bolted_size();
651 * Interrupt stacks must be in the first segment since we
652 * cannot afford to take SLB misses on them. They are not
653 * accessed in realmode.
655 for_each_possible_cpu(i) {
656 softirq_ctx[i] = alloc_stack(limit, i);
657 hardirq_ctx[i] = alloc_stack(limit, i);
661 #ifdef CONFIG_PPC_BOOK3E
662 void __init exc_lvl_early_init(void)
666 for_each_possible_cpu(i) {
669 sp = alloc_stack(ULONG_MAX, i);
671 paca_ptrs[i]->crit_kstack = sp + THREAD_SIZE;
673 sp = alloc_stack(ULONG_MAX, i);
675 paca_ptrs[i]->dbg_kstack = sp + THREAD_SIZE;
677 sp = alloc_stack(ULONG_MAX, i);
678 mcheckirq_ctx[i] = sp;
679 paca_ptrs[i]->mc_kstack = sp + THREAD_SIZE;
682 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
683 patch_exception(0x040, exc_debug_debug_book3e);
688 * Emergency stacks are used for a range of things, from asynchronous
689 * NMIs (system reset, machine check) to synchronous, process context.
690 * We set preempt_count to zero, even though that isn't necessarily correct. To
691 * get the right value we'd need to copy it from the previous thread_info, but
692 * doing that might fault causing more problems.
693 * TODO: what to do with accounting?
695 static void emerg_stack_init_thread_info(struct thread_info *ti, int cpu)
699 ti->preempt_count = 0;
702 klp_init_thread_info(ti);
706 * Stack space used when we detect a bad kernel stack pointer, and
707 * early in SMP boots before relocation is enabled. Exclusive emergency
708 * stack for machine checks.
710 void __init emergency_stack_init(void)
716 * Emergency stacks must be under 256MB, we cannot afford to take
717 * SLB misses on them. The ABI also requires them to be 128-byte
720 * Since we use these as temporary stacks during secondary CPU
721 * bringup, machine check, system reset, and HMI, we need to get
722 * at them in real mode. This means they must also be within the RMO
725 * The IRQ stacks allocated elsewhere in this file are zeroed and
726 * initialized in kernel/irq.c. These are initialized here in order
727 * to have emergency stacks available as early as possible.
729 limit = min(ppc64_bolted_size(), ppc64_rma_size);
731 for_each_possible_cpu(i) {
732 struct thread_info *ti;
734 ti = alloc_stack(limit, i);
735 memset(ti, 0, THREAD_SIZE);
736 emerg_stack_init_thread_info(ti, i);
737 paca_ptrs[i]->emergency_sp = (void *)ti + THREAD_SIZE;
739 #ifdef CONFIG_PPC_BOOK3S_64
740 /* emergency stack for NMI exception handling. */
741 ti = alloc_stack(limit, i);
742 memset(ti, 0, THREAD_SIZE);
743 emerg_stack_init_thread_info(ti, i);
744 paca_ptrs[i]->nmi_emergency_sp = (void *)ti + THREAD_SIZE;
746 /* emergency stack for machine check exception handling. */
747 ti = alloc_stack(limit, i);
748 memset(ti, 0, THREAD_SIZE);
749 emerg_stack_init_thread_info(ti, i);
750 paca_ptrs[i]->mc_emergency_sp = (void *)ti + THREAD_SIZE;
756 #define PCPU_DYN_SIZE ()
758 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
760 return __alloc_bootmem_node(NODE_DATA(early_cpu_to_node(cpu)), size, align,
761 __pa(MAX_DMA_ADDRESS));
764 static void __init pcpu_fc_free(void *ptr, size_t size)
766 free_bootmem(__pa(ptr), size);
769 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
771 if (early_cpu_to_node(from) == early_cpu_to_node(to))
772 return LOCAL_DISTANCE;
774 return REMOTE_DISTANCE;
777 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
778 EXPORT_SYMBOL(__per_cpu_offset);
780 void __init setup_per_cpu_areas(void)
782 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
789 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
790 * to group units. For larger mappings, use 1M atom which
791 * should be large enough to contain a number of units.
793 if (mmu_linear_psize == MMU_PAGE_4K)
794 atom_size = PAGE_SIZE;
798 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
799 pcpu_fc_alloc, pcpu_fc_free);
801 panic("cannot initialize percpu area (err=%d)", rc);
803 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
804 for_each_possible_cpu(cpu) {
805 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
806 paca_ptrs[cpu]->data_offset = __per_cpu_offset[cpu];
811 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
812 unsigned long memory_block_size_bytes(void)
814 if (ppc_md.memory_block_size)
815 return ppc_md.memory_block_size();
817 return MIN_MEMORY_BLOCK_SIZE;
821 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
822 struct ppc_pci_io ppc_pci_io;
823 EXPORT_SYMBOL(ppc_pci_io);
826 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
827 u64 hw_nmi_get_sample_period(int watchdog_thresh)
829 return ppc_proc_freq * watchdog_thresh;
834 * The perf based hardlockup detector breaks PMU event based branches, so
835 * disable it by default. Book3S has a soft-nmi hardlockup detector based
836 * on the decrementer interrupt, so it does not suffer from this problem.
838 * It is likely to get false positives in VM guests, so disable it there
841 static int __init disable_hardlockup_detector(void)
843 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
844 hardlockup_detector_disable();
846 if (firmware_has_feature(FW_FEATURE_LPAR))
847 hardlockup_detector_disable();
852 early_initcall(disable_hardlockup_detector);
854 #ifdef CONFIG_PPC_BOOK3S_64
855 static enum l1d_flush_type enabled_flush_types;
856 static void *l1d_flush_fallback_area;
857 static bool no_rfi_flush;
860 static int __init handle_no_rfi_flush(char *p)
862 pr_info("rfi-flush: disabled on command line.");
866 early_param("no_rfi_flush", handle_no_rfi_flush);
869 * The RFI flush is not KPTI, but because users will see doco that says to use
870 * nopti we hijack that option here to also disable the RFI flush.
872 static int __init handle_no_pti(char *p)
874 pr_info("rfi-flush: disabling due to 'nopti' on command line.\n");
875 handle_no_rfi_flush(NULL);
878 early_param("nopti", handle_no_pti);
880 static void do_nothing(void *unused)
883 * We don't need to do the flush explicitly, just enter+exit kernel is
884 * sufficient, the RFI exit handlers will do the right thing.
888 void rfi_flush_enable(bool enable)
891 do_rfi_flush_fixups(enabled_flush_types);
892 on_each_cpu(do_nothing, NULL, 1);
894 do_rfi_flush_fixups(L1D_FLUSH_NONE);
899 static void __ref init_fallback_flush(void)
904 /* Only allocate the fallback flush area once (at boot time). */
905 if (l1d_flush_fallback_area)
908 l1d_size = ppc64_caches.l1d.size;
911 * If there is no d-cache-size property in the device tree, l1d_size
912 * could be zero. That leads to the loop in the asm wrapping around to
913 * 2^64-1, and then walking off the end of the fallback area and
914 * eventually causing a page fault which is fatal. Just default to
915 * something vaguely sane.
918 l1d_size = (64 * 1024);
920 limit = min(ppc64_bolted_size(), ppc64_rma_size);
923 * Align to L1d size, and size it at 2x L1d size, to catch possible
924 * hardware prefetch runoff. We don't have a recipe for load patterns to
925 * reliably avoid the prefetcher.
927 l1d_flush_fallback_area = __va(memblock_alloc_base(l1d_size * 2, l1d_size, limit));
928 memset(l1d_flush_fallback_area, 0, l1d_size * 2);
930 for_each_possible_cpu(cpu) {
931 struct paca_struct *paca = paca_ptrs[cpu];
932 paca->rfi_flush_fallback_area = l1d_flush_fallback_area;
933 paca->l1d_flush_size = l1d_size;
937 void setup_rfi_flush(enum l1d_flush_type types, bool enable)
939 if (types & L1D_FLUSH_FALLBACK) {
940 pr_info("rfi-flush: fallback displacement flush available\n");
941 init_fallback_flush();
944 if (types & L1D_FLUSH_ORI)
945 pr_info("rfi-flush: ori type flush available\n");
947 if (types & L1D_FLUSH_MTTRIG)
948 pr_info("rfi-flush: mttrig type flush available\n");
950 enabled_flush_types = types;
953 rfi_flush_enable(enable);
956 #ifdef CONFIG_DEBUG_FS
957 static int rfi_flush_set(void *data, u64 val)
968 /* Only do anything if we're changing state */
969 if (enable != rfi_flush)
970 rfi_flush_enable(enable);
975 static int rfi_flush_get(void *data, u64 *val)
977 *val = rfi_flush ? 1 : 0;
981 DEFINE_SIMPLE_ATTRIBUTE(fops_rfi_flush, rfi_flush_get, rfi_flush_set, "%llu\n");
983 static __init int rfi_flush_debugfs_init(void)
985 debugfs_create_file("rfi_flush", 0600, powerpc_debugfs_root, NULL, &fops_rfi_flush);
988 device_initcall(rfi_flush_debugfs_init);
990 #endif /* CONFIG_PPC_BOOK3S_64 */