arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/sched/debug.h>
  20 #include <linux/sched/task.h>
  21 #include <linux/sched/task_stack.h>
  22 #include <linux/kernel.h>
  23 #include <linux/mm.h>
  24 #include <linux/smp.h>
  25 #include <linux/stddef.h>
  26 #include <linux/unistd.h>
  27 #include <linux/ptrace.h>
  28 #include <linux/slab.h>
  29 #include <linux/user.h>
  30 #include <linux/elf.h>
  31 #include <linux/prctl.h>
  32 #include <linux/init_task.h>
  33 #include <linux/export.h>
  34 #include <linux/kallsyms.h>
  35 #include <linux/mqueue.h>
  36 #include <linux/hardirq.h>
  37 #include <linux/utsname.h>
  38 #include <linux/ftrace.h>
  39 #include <linux/kernel_stat.h>
  40 #include <linux/personality.h>
  41 #include <linux/random.h>
  42 #include <linux/hw_breakpoint.h>
  43 #include <linux/uaccess.h>
  44 #include <linux/elf-randomize.h>
  45 #include <linux/pkeys.h>
  46 #include <linux/seq_buf.h>
  47
  48 #include <asm/pgtable.h>
  49 #include <asm/io.h>
  50 #include <asm/processor.h>
  51 #include <asm/mmu.h>
  52 #include <asm/prom.h>
  53 #include <asm/machdep.h>
  54 #include <asm/time.h>
  55 #include <asm/runlatch.h>
  56 #include <asm/syscalls.h>
  57 #include <asm/switch_to.h>
  58 #include <asm/tm.h>
  59 #include <asm/debug.h>
  60 #ifdef CONFIG_PPC64
  61 #include <asm/firmware.h>
  62 #include <asm/hw_irq.h>
  63 #endif
  64 #include <asm/code-patching.h>
  65 #include <asm/exec.h>
  66 #include <asm/livepatch.h>
  67 #include <asm/cpu_has_feature.h>
  68 #include <asm/asm-prototypes.h>
  69 #include <asm/stacktrace.h>
  70
  71 #include <linux/kprobes.h>
  72 #include <linux/kdebug.h>
  73
  74 /* Transactional Memory debug */
  75 #ifdef TM_DEBUG_SW
  76 #define TM_DEBUG(x...) printk(KERN_INFO x)
  77 #else
  78 #define TM_DEBUG(x...) do { } while(0)
  79 #endif
  80
  81 extern unsigned long _get_SP(void);
  82
  83 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  84 /*
  85  * Are we running in "Suspend disabled" mode? If so we have to block any
  86  * sigreturn that would get us into suspended state, and we also warn in some
  87  * other paths that we should never reach with suspend disabled.
  88  */
  89 bool tm_suspend_disabled __ro_after_init = false;
  90
  91 static void check_if_tm_restore_required(struct task_struct *tsk)
  92 {
  93         /*
  94          * If we are saving the current thread's registers, and the
  95          * thread is in a transactional state, set the TIF_RESTORE_TM
  96          * bit so that we know to restore the registers before
  97          * returning to userspace.
  98          */
  99         if (tsk == current && tsk->thread.regs &&
 100             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
 101             !test_thread_flag(TIF_RESTORE_TM)) {
 102                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
 103                 set_thread_flag(TIF_RESTORE_TM);
 104         }
 105 }
 106
 107 static bool tm_active_with_fp(struct task_struct *tsk)
 108 {
 109         return MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
 110                 (tsk->thread.ckpt_regs.msr & MSR_FP);
 111 }
 112
 113 static bool tm_active_with_altivec(struct task_struct *tsk)
 114 {
 115         return MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
 116                 (tsk->thread.ckpt_regs.msr & MSR_VEC);
 117 }
 118 #else
 119 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
 120 static inline bool tm_active_with_fp(struct task_struct *tsk) { return false; }
 121 static inline bool tm_active_with_altivec(struct task_struct *tsk) { return false; }
 122 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 123
 124 bool strict_msr_control;
 125 EXPORT_SYMBOL(strict_msr_control);
 126
 127 static int __init enable_strict_msr_control(char *str)
 128 {
 129         strict_msr_control = true;
 130         pr_info("Enabling strict facility control\n");
 131
 132         return 0;
 133 }
 134 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 135
 136 unsigned long msr_check_and_set(unsigned long bits)
 137 {
 138         unsigned long oldmsr = mfmsr();
 139         unsigned long newmsr;
 140
 141         newmsr = oldmsr | bits;
 142
 143 #ifdef CONFIG_VSX
 144         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 145                 newmsr |= MSR_VSX;
 146 #endif
 147
 148         if (oldmsr != newmsr)
 149                 mtmsr_isync(newmsr);
 150
 151         return newmsr;
 152 }
 153 EXPORT_SYMBOL_GPL(msr_check_and_set);
 154
 155 void __msr_check_and_clear(unsigned long bits)
 156 {
 157         unsigned long oldmsr = mfmsr();
 158         unsigned long newmsr;
 159
 160         newmsr = oldmsr & ~bits;
 161
 162 #ifdef CONFIG_VSX
 163         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 164                 newmsr &= ~MSR_VSX;
 165 #endif
 166
 167         if (oldmsr != newmsr)
 168                 mtmsr_isync(newmsr);
 169 }
 170 EXPORT_SYMBOL(__msr_check_and_clear);
 171
 172 #ifdef CONFIG_PPC_FPU
 173 static void __giveup_fpu(struct task_struct *tsk)
 174 {
 175         unsigned long msr;
 176
 177         save_fpu(tsk);
 178         msr = tsk->thread.regs->msr;
 179         msr &= ~MSR_FP;
 180 #ifdef CONFIG_VSX
 181         if (cpu_has_feature(CPU_FTR_VSX))
 182                 msr &= ~MSR_VSX;
 183 #endif
 184         tsk->thread.regs->msr = msr;
 185 }
 186
 187 void giveup_fpu(struct task_struct *tsk)
 188 {
 189         check_if_tm_restore_required(tsk);
 190
 191         msr_check_and_set(MSR_FP);
 192         __giveup_fpu(tsk);
 193         msr_check_and_clear(MSR_FP);
 194 }
 195 EXPORT_SYMBOL(giveup_fpu);
 196
 197 /*
 198  * Make sure the floating-point register state in the
 199  * the thread_struct is up to date for task tsk.
 200  */
 201 void flush_fp_to_thread(struct task_struct *tsk)
 202 {
 203         if (tsk->thread.regs) {
 204                 /*
 205                  * We need to disable preemption here because if we didn't,
 206                  * another process could get scheduled after the regs->msr
 207                  * test but before we have finished saving the FP registers
 208                  * to the thread_struct.  That process could take over the
 209                  * FPU, and then when we get scheduled again we would store
 210                  * bogus values for the remaining FP registers.
 211                  */
 212                 preempt_disable();
 213                 if (tsk->thread.regs->msr & MSR_FP) {
 214                         /*
 215                          * This should only ever be called for current or
 216                          * for a stopped child process.  Since we save away
 217                          * the FP register state on context switch,
 218                          * there is something wrong if a stopped child appears
 219                          * to still have its FP state in the CPU registers.
 220                          */
 221                         BUG_ON(tsk != current);
 222                         giveup_fpu(tsk);
 223                 }
 224                 preempt_enable();
 225         }
 226 }
 227 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 228
 229 void enable_kernel_fp(void)
 230 {
 231         unsigned long cpumsr;
 232
 233         WARN_ON(preemptible());
 234
 235         cpumsr = msr_check_and_set(MSR_FP);
 236
 237         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 238                 check_if_tm_restore_required(current);
 239                 /*
 240                  * If a thread has already been reclaimed then the
 241                  * checkpointed registers are on the CPU but have definitely
 242                  * been saved by the reclaim code. Don't need to and *cannot*
 243                  * giveup as this would save  to the 'live' structure not the
 244                  * checkpointed structure.
 245                  */
 246                 if (!MSR_TM_ACTIVE(cpumsr) &&
 247                      MSR_TM_ACTIVE(current->thread.regs->msr))
 248                         return;
 249                 __giveup_fpu(current);
 250         }
 251 }
 252 EXPORT_SYMBOL(enable_kernel_fp);
 253
 254 static int restore_fp(struct task_struct *tsk)
 255 {
 256         if (tsk->thread.load_fp || tm_active_with_fp(tsk)) {
 257                 load_fp_state(&current->thread.fp_state);
 258                 current->thread.load_fp++;
 259                 return 1;
 260         }
 261         return 0;
 262 }
 263 #else
 264 static int restore_fp(struct task_struct *tsk) { return 0; }
 265 #endif /* CONFIG_PPC_FPU */
 266
 267 #ifdef CONFIG_ALTIVEC
 268 #define loadvec(thr) ((thr).load_vec)
 269
 270 static void __giveup_altivec(struct task_struct *tsk)
 271 {
 272         unsigned long msr;
 273
 274         save_altivec(tsk);
 275         msr = tsk->thread.regs->msr;
 276         msr &= ~MSR_VEC;
 277 #ifdef CONFIG_VSX
 278         if (cpu_has_feature(CPU_FTR_VSX))
 279                 msr &= ~MSR_VSX;
 280 #endif
 281         tsk->thread.regs->msr = msr;
 282 }
 283
 284 void giveup_altivec(struct task_struct *tsk)
 285 {
 286         check_if_tm_restore_required(tsk);
 287
 288         msr_check_and_set(MSR_VEC);
 289         __giveup_altivec(tsk);
 290         msr_check_and_clear(MSR_VEC);
 291 }
 292 EXPORT_SYMBOL(giveup_altivec);
 293
 294 void enable_kernel_altivec(void)
 295 {
 296         unsigned long cpumsr;
 297
 298         WARN_ON(preemptible());
 299
 300         cpumsr = msr_check_and_set(MSR_VEC);
 301
 302         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 303                 check_if_tm_restore_required(current);
 304                 /*
 305                  * If a thread has already been reclaimed then the
 306                  * checkpointed registers are on the CPU but have definitely
 307                  * been saved by the reclaim code. Don't need to and *cannot*
 308                  * giveup as this would save  to the 'live' structure not the
 309                  * checkpointed structure.
 310                  */
 311                 if (!MSR_TM_ACTIVE(cpumsr) &&
 312                      MSR_TM_ACTIVE(current->thread.regs->msr))
 313                         return;
 314                 __giveup_altivec(current);
 315         }
 316 }
 317 EXPORT_SYMBOL(enable_kernel_altivec);
 318
 319 /*
 320  * Make sure the VMX/Altivec register state in the
 321  * the thread_struct is up to date for task tsk.
 322  */
 323 void flush_altivec_to_thread(struct task_struct *tsk)
 324 {
 325         if (tsk->thread.regs) {
 326                 preempt_disable();
 327                 if (tsk->thread.regs->msr & MSR_VEC) {
 328                         BUG_ON(tsk != current);
 329                         giveup_altivec(tsk);
 330                 }
 331                 preempt_enable();
 332         }
 333 }
 334 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 335
 336 static int restore_altivec(struct task_struct *tsk)
 337 {
 338         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 339                 (tsk->thread.load_vec || tm_active_with_altivec(tsk))) {
 340                 load_vr_state(&tsk->thread.vr_state);
 341                 tsk->thread.used_vr = 1;
 342                 tsk->thread.load_vec++;
 343
 344                 return 1;
 345         }
 346         return 0;
 347 }
 348 #else
 349 #define loadvec(thr) 0
 350 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
 351 #endif /* CONFIG_ALTIVEC */
 352
 353 #ifdef CONFIG_VSX
 354 static void __giveup_vsx(struct task_struct *tsk)
 355 {
 356         unsigned long msr = tsk->thread.regs->msr;
 357
 358         /*
 359          * We should never be ssetting MSR_VSX without also setting
 360          * MSR_FP and MSR_VEC
 361          */
 362         WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC)));
 363
 364         /* __giveup_fpu will clear MSR_VSX */
 365         if (msr & MSR_FP)
 366                 __giveup_fpu(tsk);
 367         if (msr & MSR_VEC)
 368                 __giveup_altivec(tsk);
 369 }
 370
 371 static void giveup_vsx(struct task_struct *tsk)
 372 {
 373         check_if_tm_restore_required(tsk);
 374
 375         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 376         __giveup_vsx(tsk);
 377         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 378 }
 379
 380 void enable_kernel_vsx(void)
 381 {
 382         unsigned long cpumsr;
 383
 384         WARN_ON(preemptible());
 385
 386         cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 387
 388         if (current->thread.regs &&
 389             (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
 390                 check_if_tm_restore_required(current);
 391                 /*
 392                  * If a thread has already been reclaimed then the
 393                  * checkpointed registers are on the CPU but have definitely
 394                  * been saved by the reclaim code. Don't need to and *cannot*
 395                  * giveup as this would save  to the 'live' structure not the
 396                  * checkpointed structure.
 397                  */
 398                 if (!MSR_TM_ACTIVE(cpumsr) &&
 399                      MSR_TM_ACTIVE(current->thread.regs->msr))
 400                         return;
 401                 __giveup_vsx(current);
 402         }
 403 }
 404 EXPORT_SYMBOL(enable_kernel_vsx);
 405
 406 void flush_vsx_to_thread(struct task_struct *tsk)
 407 {
 408         if (tsk->thread.regs) {
 409                 preempt_disable();
 410                 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
 411                         BUG_ON(tsk != current);
 412                         giveup_vsx(tsk);
 413                 }
 414                 preempt_enable();
 415         }
 416 }
 417 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 418
 419 static int restore_vsx(struct task_struct *tsk)
 420 {
 421         if (cpu_has_feature(CPU_FTR_VSX)) {
 422                 tsk->thread.used_vsr = 1;
 423                 return 1;
 424         }
 425
 426         return 0;
 427 }
 428 #else
 429 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
 430 #endif /* CONFIG_VSX */
 431
 432 #ifdef CONFIG_SPE
 433 void giveup_spe(struct task_struct *tsk)
 434 {
 435         check_if_tm_restore_required(tsk);
 436
 437         msr_check_and_set(MSR_SPE);
 438         __giveup_spe(tsk);
 439         msr_check_and_clear(MSR_SPE);
 440 }
 441 EXPORT_SYMBOL(giveup_spe);
 442
 443 void enable_kernel_spe(void)
 444 {
 445         WARN_ON(preemptible());
 446
 447         msr_check_and_set(MSR_SPE);
 448
 449         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 450                 check_if_tm_restore_required(current);
 451                 __giveup_spe(current);
 452         }
 453 }
 454 EXPORT_SYMBOL(enable_kernel_spe);
 455
 456 void flush_spe_to_thread(struct task_struct *tsk)
 457 {
 458         if (tsk->thread.regs) {
 459                 preempt_disable();
 460                 if (tsk->thread.regs->msr & MSR_SPE) {
 461                         BUG_ON(tsk != current);
 462                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 463                         giveup_spe(tsk);
 464                 }
 465                 preempt_enable();
 466         }
 467 }
 468 #endif /* CONFIG_SPE */
 469
 470 static unsigned long msr_all_available;
 471
 472 static int __init init_msr_all_available(void)
 473 {
 474 #ifdef CONFIG_PPC_FPU
 475         msr_all_available |= MSR_FP;
 476 #endif
 477 #ifdef CONFIG_ALTIVEC
 478         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 479                 msr_all_available |= MSR_VEC;
 480 #endif
 481 #ifdef CONFIG_VSX
 482         if (cpu_has_feature(CPU_FTR_VSX))
 483                 msr_all_available |= MSR_VSX;
 484 #endif
 485 #ifdef CONFIG_SPE
 486         if (cpu_has_feature(CPU_FTR_SPE))
 487                 msr_all_available |= MSR_SPE;
 488 #endif
 489
 490         return 0;
 491 }
 492 early_initcall(init_msr_all_available);
 493
 494 void giveup_all(struct task_struct *tsk)
 495 {
 496         unsigned long usermsr;
 497
 498         if (!tsk->thread.regs)
 499                 return;
 500
 501         usermsr = tsk->thread.regs->msr;
 502
 503         if ((usermsr & msr_all_available) == 0)
 504                 return;
 505
 506         msr_check_and_set(msr_all_available);
 507         check_if_tm_restore_required(tsk);
 508
 509         WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
 510
 511 #ifdef CONFIG_PPC_FPU
 512         if (usermsr & MSR_FP)
 513                 __giveup_fpu(tsk);
 514 #endif
 515 #ifdef CONFIG_ALTIVEC
 516         if (usermsr & MSR_VEC)
 517                 __giveup_altivec(tsk);
 518 #endif
 519 #ifdef CONFIG_SPE
 520         if (usermsr & MSR_SPE)
 521                 __giveup_spe(tsk);
 522 #endif
 523
 524         msr_check_and_clear(msr_all_available);
 525 }
 526 EXPORT_SYMBOL(giveup_all);
 527
 528 void restore_math(struct pt_regs *regs)
 529 {
 530         unsigned long msr;
 531
 532         if (!MSR_TM_ACTIVE(regs->msr) &&
 533                 !current->thread.load_fp && !loadvec(current->thread))
 534                 return;
 535
 536         msr = regs->msr;
 537         msr_check_and_set(msr_all_available);
 538
 539         /*
 540          * Only reload if the bit is not set in the user MSR, the bit BEING set
 541          * indicates that the registers are hot
 542          */
 543         if ((!(msr & MSR_FP)) && restore_fp(current))
 544                 msr |= MSR_FP | current->thread.fpexc_mode;
 545
 546         if ((!(msr & MSR_VEC)) && restore_altivec(current))
 547                 msr |= MSR_VEC;
 548
 549         if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
 550                         restore_vsx(current)) {
 551                 msr |= MSR_VSX;
 552         }
 553
 554         msr_check_and_clear(msr_all_available);
 555
 556         regs->msr = msr;
 557 }
 558
 559 static void save_all(struct task_struct *tsk)
 560 {
 561         unsigned long usermsr;
 562
 563         if (!tsk->thread.regs)
 564                 return;
 565
 566         usermsr = tsk->thread.regs->msr;
 567
 568         if ((usermsr & msr_all_available) == 0)
 569                 return;
 570
 571         msr_check_and_set(msr_all_available);
 572
 573         WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
 574
 575         if (usermsr & MSR_FP)
 576                 save_fpu(tsk);
 577
 578         if (usermsr & MSR_VEC)
 579                 save_altivec(tsk);
 580
 581         if (usermsr & MSR_SPE)
 582                 __giveup_spe(tsk);
 583
 584         msr_check_and_clear(msr_all_available);
 585         thread_pkey_regs_save(&tsk->thread);
 586 }
 587
 588 void flush_all_to_thread(struct task_struct *tsk)
 589 {
 590         if (tsk->thread.regs) {
 591                 preempt_disable();
 592                 BUG_ON(tsk != current);
 593                 save_all(tsk);
 594
 595 #ifdef CONFIG_SPE
 596                 if (tsk->thread.regs->msr & MSR_SPE)
 597                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 598 #endif
 599
 600                 preempt_enable();
 601         }
 602 }
 603 EXPORT_SYMBOL(flush_all_to_thread);
 604
 605 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 606 void do_send_trap(struct pt_regs *regs, unsigned long address,
 607                   unsigned long error_code, int breakpt)
 608 {
 609         current->thread.trap_nr = TRAP_HWBKPT;
 610         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 611                         11, SIGSEGV) == NOTIFY_STOP)
 612                 return;
 613
 614         /* Deliver the signal to userspace */
 615         force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */
 616                                     (void __user *)address);
 617 }
 618 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 619 void do_break (struct pt_regs *regs, unsigned long address,
 620                     unsigned long error_code)
 621 {
 622         current->thread.trap_nr = TRAP_HWBKPT;
 623         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 624                         11, SIGSEGV) == NOTIFY_STOP)
 625                 return;
 626
 627         if (debugger_break_match(regs))
 628                 return;
 629
 630         /* Clear the breakpoint */
 631         hw_breakpoint_disable();
 632
 633         /* Deliver the signal to userspace */
 634         force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)address, current);
 635 }
 636 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 637
 638 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 639
 640 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 641 /*
 642  * Set the debug registers back to their default "safe" values.
 643  */
 644 static void set_debug_reg_defaults(struct thread_struct *thread)
 645 {
 646         thread->debug.iac1 = thread->debug.iac2 = 0;
 647 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 648         thread->debug.iac3 = thread->debug.iac4 = 0;
 649 #endif
 650         thread->debug.dac1 = thread->debug.dac2 = 0;
 651 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 652         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 653 #endif
 654         thread->debug.dbcr0 = 0;
 655 #ifdef CONFIG_BOOKE
 656         /*
 657          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 658          */
 659         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 660                         DBCR1_IAC3US | DBCR1_IAC4US;
 661         /*
 662          * Force Data Address Compare User/Supervisor bits to be User-only
 663          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 664          */
 665         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 666 #else
 667         thread->debug.dbcr1 = 0;
 668 #endif
 669 }
 670
 671 static void prime_debug_regs(struct debug_reg *debug)
 672 {
 673         /*
 674          * We could have inherited MSR_DE from userspace, since
 675          * it doesn't get cleared on exception entry.  Make sure
 676          * MSR_DE is clear before we enable any debug events.
 677          */
 678         mtmsr(mfmsr() & ~MSR_DE);
 679
 680         mtspr(SPRN_IAC1, debug->iac1);
 681         mtspr(SPRN_IAC2, debug->iac2);
 682 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 683         mtspr(SPRN_IAC3, debug->iac3);
 684         mtspr(SPRN_IAC4, debug->iac4);
 685 #endif
 686         mtspr(SPRN_DAC1, debug->dac1);
 687         mtspr(SPRN_DAC2, debug->dac2);
 688 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 689         mtspr(SPRN_DVC1, debug->dvc1);
 690         mtspr(SPRN_DVC2, debug->dvc2);
 691 #endif
 692         mtspr(SPRN_DBCR0, debug->dbcr0);
 693         mtspr(SPRN_DBCR1, debug->dbcr1);
 694 #ifdef CONFIG_BOOKE
 695         mtspr(SPRN_DBCR2, debug->dbcr2);
 696 #endif
 697 }
 698 /*
 699  * Unless neither the old or new thread are making use of the
 700  * debug registers, set the debug registers from the values
 701  * stored in the new thread.
 702  */
 703 void switch_booke_debug_regs(struct debug_reg *new_debug)
 704 {
 705         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 706                 || (new_debug->dbcr0 & DBCR0_IDM))
 707                         prime_debug_regs(new_debug);
 708 }
 709 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 710 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 711 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 712 static void set_breakpoint(struct arch_hw_breakpoint *brk)
 713 {
 714         preempt_disable();
 715         __set_breakpoint(brk);
 716         preempt_enable();
 717 }
 718
 719 static void set_debug_reg_defaults(struct thread_struct *thread)
 720 {
 721         thread->hw_brk.address = 0;
 722         thread->hw_brk.type = 0;
 723         if (ppc_breakpoint_available())
 724                 set_breakpoint(&thread->hw_brk);
 725 }
 726 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 727 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 728
 729 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 730 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 731 {
 732         mtspr(SPRN_DAC1, dabr);
 733 #ifdef CONFIG_PPC_47x
 734         isync();
 735 #endif
 736         return 0;
 737 }
 738 #elif defined(CONFIG_PPC_BOOK3S)
 739 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 740 {
 741         mtspr(SPRN_DABR, dabr);
 742         if (cpu_has_feature(CPU_FTR_DABRX))
 743                 mtspr(SPRN_DABRX, dabrx);
 744         return 0;
 745 }
 746 #elif defined(CONFIG_PPC_8xx)
 747 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 748 {
 749         unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
 750         unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
 751         unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
 752
 753         if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
 754                 lctrl1 |= 0xa0000;
 755         else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
 756                 lctrl1 |= 0xf0000;
 757         else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
 758                 lctrl2 = 0;
 759
 760         mtspr(SPRN_LCTRL2, 0);
 761         mtspr(SPRN_CMPE, addr);
 762         mtspr(SPRN_CMPF, addr + 4);
 763         mtspr(SPRN_LCTRL1, lctrl1);
 764         mtspr(SPRN_LCTRL2, lctrl2);
 765
 766         return 0;
 767 }
 768 #else
 769 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 770 {
 771         return -EINVAL;
 772 }
 773 #endif
 774
 775 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 776 {
 777         unsigned long dabr, dabrx;
 778
 779         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 780         dabrx = ((brk->type >> 3) & 0x7);
 781
 782         if (ppc_md.set_dabr)
 783                 return ppc_md.set_dabr(dabr, dabrx);
 784
 785         return __set_dabr(dabr, dabrx);
 786 }
 787
 788 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 789 {
 790         unsigned long dawr, dawrx, mrd;
 791
 792         dawr = brk->address;
 793
 794         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 795                                    << (63 - 58); //* read/write bits */
 796         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 797                                    << (63 - 59); //* translate */
 798         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 799                                    >> 3; //* PRIM bits */
 800         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 801            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 802            0b111111=64DW.
 803            brk->len is in bytes.
 804            This aligns up to double word size, shifts and does the bias.
 805         */
 806         mrd = ((brk->len + 7) >> 3) - 1;
 807         dawrx |= (mrd & 0x3f) << (63 - 53);
 808
 809         if (ppc_md.set_dawr)
 810                 return ppc_md.set_dawr(dawr, dawrx);
 811         mtspr(SPRN_DAWR, dawr);
 812         mtspr(SPRN_DAWRX, dawrx);
 813         return 0;
 814 }
 815
 816 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 817 {
 818         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 819
 820         if (cpu_has_feature(CPU_FTR_DAWR))
 821                 // Power8 or later
 822                 set_dawr(brk);
 823         else if (!cpu_has_feature(CPU_FTR_ARCH_207S))
 824                 // Power7 or earlier
 825                 set_dabr(brk);
 826         else
 827                 // Shouldn't happen due to higher level checks
 828                 WARN_ON_ONCE(1);
 829 }
 830
 831 /* Check if we have DAWR or DABR hardware */
 832 bool ppc_breakpoint_available(void)
 833 {
 834         if (cpu_has_feature(CPU_FTR_DAWR))
 835                 return true; /* POWER8 DAWR */
 836         if (cpu_has_feature(CPU_FTR_ARCH_207S))
 837                 return false; /* POWER9 with DAWR disabled */
 838         /* DABR: Everything but POWER8 and POWER9 */
 839         return true;
 840 }
 841 EXPORT_SYMBOL_GPL(ppc_breakpoint_available);
 842
 843 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 844                               struct arch_hw_breakpoint *b)
 845 {
 846         if (a->address != b->address)
 847                 return false;
 848         if (a->type != b->type)
 849                 return false;
 850         if (a->len != b->len)
 851                 return false;
 852         return true;
 853 }
 854
 855 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 856
 857 static inline bool tm_enabled(struct task_struct *tsk)
 858 {
 859         return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
 860 }
 861
 862 static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause)
 863 {
 864         /*
 865          * Use the current MSR TM suspended bit to track if we have
 866          * checkpointed state outstanding.
 867          * On signal delivery, we'd normally reclaim the checkpointed
 868          * state to obtain stack pointer (see:get_tm_stackpointer()).
 869          * This will then directly return to userspace without going
 870          * through __switch_to(). However, if the stack frame is bad,
 871          * we need to exit this thread which calls __switch_to() which
 872          * will again attempt to reclaim the already saved tm state.
 873          * Hence we need to check that we've not already reclaimed
 874          * this state.
 875          * We do this using the current MSR, rather tracking it in
 876          * some specific thread_struct bit, as it has the additional
 877          * benefit of checking for a potential TM bad thing exception.
 878          */
 879         if (!MSR_TM_SUSPENDED(mfmsr()))
 880                 return;
 881
 882         giveup_all(container_of(thr, struct task_struct, thread));
 883
 884         tm_reclaim(thr, cause);
 885
 886         /*
 887          * If we are in a transaction and FP is off then we can't have
 888          * used FP inside that transaction. Hence the checkpointed
 889          * state is the same as the live state. We need to copy the
 890          * live state to the checkpointed state so that when the
 891          * transaction is restored, the checkpointed state is correct
 892          * and the aborted transaction sees the correct state. We use
 893          * ckpt_regs.msr here as that's what tm_reclaim will use to
 894          * determine if it's going to write the checkpointed state or
 895          * not. So either this will write the checkpointed registers,
 896          * or reclaim will. Similarly for VMX.
 897          */
 898         if ((thr->ckpt_regs.msr & MSR_FP) == 0)
 899                 memcpy(&thr->ckfp_state, &thr->fp_state,
 900                        sizeof(struct thread_fp_state));
 901         if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
 902                 memcpy(&thr->ckvr_state, &thr->vr_state,
 903                        sizeof(struct thread_vr_state));
 904 }
 905
 906 void tm_reclaim_current(uint8_t cause)
 907 {
 908         tm_enable();
 909         tm_reclaim_thread(&current->thread, cause);
 910 }
 911
 912 static inline void tm_reclaim_task(struct task_struct *tsk)
 913 {
 914         /* We have to work out if we're switching from/to a task that's in the
 915          * middle of a transaction.
 916          *
 917          * In switching we need to maintain a 2nd register state as
 918          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 919          * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
 920          * ckvr_state
 921          *
 922          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 923          */
 924         struct thread_struct *thr = &tsk->thread;
 925
 926         if (!thr->regs)
 927                 return;
 928
 929         if (!MSR_TM_ACTIVE(thr->regs->msr))
 930                 goto out_and_saveregs;
 931
 932         WARN_ON(tm_suspend_disabled);
 933
 934         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 935                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 936                  tsk->pid, thr->regs->nip,
 937                  thr->regs->ccr, thr->regs->msr,
 938                  thr->regs->trap);
 939
 940         tm_reclaim_thread(thr, TM_CAUSE_RESCHED);
 941
 942         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 943                  tsk->pid);
 944
 945 out_and_saveregs:
 946         /* Always save the regs here, even if a transaction's not active.
 947          * This context-switches a thread's TM info SPRs.  We do it here to
 948          * be consistent with the restore path (in recheckpoint) which
 949          * cannot happen later in _switch().
 950          */
 951         tm_save_sprs(thr);
 952 }
 953
 954 extern void __tm_recheckpoint(struct thread_struct *thread);
 955
 956 void tm_recheckpoint(struct thread_struct *thread)
 957 {
 958         unsigned long flags;
 959
 960         if (!(thread->regs->msr & MSR_TM))
 961                 return;
 962
 963         /* We really can't be interrupted here as the TEXASR registers can't
 964          * change and later in the trecheckpoint code, we have a userspace R1.
 965          * So let's hard disable over this region.
 966          */
 967         local_irq_save(flags);
 968         hard_irq_disable();
 969
 970         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 971          * before the trecheckpoint and no explosion occurs.
 972          */
 973         tm_restore_sprs(thread);
 974
 975         __tm_recheckpoint(thread);
 976
 977         local_irq_restore(flags);
 978 }
 979
 980 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 981 {
 982         if (!cpu_has_feature(CPU_FTR_TM))
 983                 return;
 984
 985         /* Recheckpoint the registers of the thread we're about to switch to.
 986          *
 987          * If the task was using FP, we non-lazily reload both the original and
 988          * the speculative FP register states.  This is because the kernel
 989          * doesn't see if/when a TM rollback occurs, so if we take an FP
 990          * unavailable later, we are unable to determine which set of FP regs
 991          * need to be restored.
 992          */
 993         if (!tm_enabled(new))
 994                 return;
 995
 996         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 997                 tm_restore_sprs(&new->thread);
 998                 return;
 999         }
1000         /* Recheckpoint to restore original checkpointed register state. */
1001         TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
1002                  new->pid, new->thread.regs->msr);
1003
1004         tm_recheckpoint(&new->thread);
1005
1006         /*
1007          * The checkpointed state has been restored but the live state has
1008          * not, ensure all the math functionality is turned off to trigger
1009          * restore_math() to reload.
1010          */
1011         new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
1012
1013         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1014                  "(kernel msr 0x%lx)\n",
1015                  new->pid, mfmsr());
1016 }
1017
1018 static inline void __switch_to_tm(struct task_struct *prev,
1019                 struct task_struct *new)
1020 {
1021         if (cpu_has_feature(CPU_FTR_TM)) {
1022                 if (tm_enabled(prev) || tm_enabled(new))
1023                         tm_enable();
1024
1025                 if (tm_enabled(prev)) {
1026                         prev->thread.load_tm++;
1027                         tm_reclaim_task(prev);
1028                         if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1029                                 prev->thread.regs->msr &= ~MSR_TM;
1030                 }
1031
1032                 tm_recheckpoint_new_task(new);
1033         }
1034 }
1035
1036 /*
1037  * This is called if we are on the way out to userspace and the
1038  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
1039  * FP and/or vector state and does so if necessary.
1040  * If userspace is inside a transaction (whether active or
1041  * suspended) and FP/VMX/VSX instructions have ever been enabled
1042  * inside that transaction, then we have to keep them enabled
1043  * and keep the FP/VMX/VSX state loaded while ever the transaction
1044  * continues.  The reason is that if we didn't, and subsequently
1045  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1046  * we don't know whether it's the same transaction, and thus we
1047  * don't know which of the checkpointed state and the transactional
1048  * state to use.
1049  */
1050 void restore_tm_state(struct pt_regs *regs)
1051 {
1052         unsigned long msr_diff;
1053
1054         /*
1055          * This is the only moment we should clear TIF_RESTORE_TM as
1056          * it is here that ckpt_regs.msr and pt_regs.msr become the same
1057          * again, anything else could lead to an incorrect ckpt_msr being
1058          * saved and therefore incorrect signal contexts.
1059          */
1060         clear_thread_flag(TIF_RESTORE_TM);
1061         if (!MSR_TM_ACTIVE(regs->msr))
1062                 return;
1063
1064         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1065         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1066
1067         /* Ensure that restore_math() will restore */
1068         if (msr_diff & MSR_FP)
1069                 current->thread.load_fp = 1;
1070 #ifdef CONFIG_ALTIVEC
1071         if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1072                 current->thread.load_vec = 1;
1073 #endif
1074         restore_math(regs);
1075
1076         regs->msr |= msr_diff;
1077 }
1078
1079 #else
1080 #define tm_recheckpoint_new_task(new)
1081 #define __switch_to_tm(prev, new)
1082 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1083
1084 static inline void save_sprs(struct thread_struct *t)
1085 {
1086 #ifdef CONFIG_ALTIVEC
1087         if (cpu_has_feature(CPU_FTR_ALTIVEC))
1088                 t->vrsave = mfspr(SPRN_VRSAVE);
1089 #endif
1090 #ifdef CONFIG_PPC_BOOK3S_64
1091         if (cpu_has_feature(CPU_FTR_DSCR))
1092                 t->dscr = mfspr(SPRN_DSCR);
1093
1094         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1095                 t->bescr = mfspr(SPRN_BESCR);
1096                 t->ebbhr = mfspr(SPRN_EBBHR);
1097                 t->ebbrr = mfspr(SPRN_EBBRR);
1098
1099                 t->fscr = mfspr(SPRN_FSCR);
1100
1101                 /*
1102                  * Note that the TAR is not available for use in the kernel.
1103                  * (To provide this, the TAR should be backed up/restored on
1104                  * exception entry/exit instead, and be in pt_regs.  FIXME,
1105                  * this should be in pt_regs anyway (for debug).)
1106                  */
1107                 t->tar = mfspr(SPRN_TAR);
1108         }
1109 #endif
1110
1111         thread_pkey_regs_save(t);
1112 }
1113
1114 static inline void restore_sprs(struct thread_struct *old_thread,
1115                                 struct thread_struct *new_thread)
1116 {
1117 #ifdef CONFIG_ALTIVEC
1118         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1119             old_thread->vrsave != new_thread->vrsave)
1120                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1121 #endif
1122 #ifdef CONFIG_PPC_BOOK3S_64
1123         if (cpu_has_feature(CPU_FTR_DSCR)) {
1124                 u64 dscr = get_paca()->dscr_default;
1125                 if (new_thread->dscr_inherit)
1126                         dscr = new_thread->dscr;
1127
1128                 if (old_thread->dscr != dscr)
1129                         mtspr(SPRN_DSCR, dscr);
1130         }
1131
1132         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1133                 if (old_thread->bescr != new_thread->bescr)
1134                         mtspr(SPRN_BESCR, new_thread->bescr);
1135                 if (old_thread->ebbhr != new_thread->ebbhr)
1136                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
1137                 if (old_thread->ebbrr != new_thread->ebbrr)
1138                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
1139
1140                 if (old_thread->fscr != new_thread->fscr)
1141                         mtspr(SPRN_FSCR, new_thread->fscr);
1142
1143                 if (old_thread->tar != new_thread->tar)
1144                         mtspr(SPRN_TAR, new_thread->tar);
1145         }
1146
1147         if (cpu_has_feature(CPU_FTR_P9_TIDR) &&
1148             old_thread->tidr != new_thread->tidr)
1149                 mtspr(SPRN_TIDR, new_thread->tidr);
1150 #endif
1151
1152         thread_pkey_regs_restore(new_thread, old_thread);
1153 }
1154
1155 #ifdef CONFIG_PPC_BOOK3S_64
1156 #define CP_SIZE 128
1157 static const u8 dummy_copy_buffer[CP_SIZE] __attribute__((aligned(CP_SIZE)));
1158 #endif
1159
1160 struct task_struct *__switch_to(struct task_struct *prev,
1161         struct task_struct *new)
1162 {
1163         struct thread_struct *new_thread, *old_thread;
1164         struct task_struct *last;
1165 #ifdef CONFIG_PPC_BOOK3S_64
1166         struct ppc64_tlb_batch *batch;
1167 #endif
1168
1169         new_thread = &new->thread;
1170         old_thread = &current->thread;
1171
1172         WARN_ON(!irqs_disabled());
1173
1174 #ifdef CONFIG_PPC_BOOK3S_64
1175         batch = this_cpu_ptr(&ppc64_tlb_batch);
1176         if (batch->active) {
1177                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1178                 if (batch->index)
1179                         __flush_tlb_pending(batch);
1180                 batch->active = 0;
1181         }
1182 #endif /* CONFIG_PPC_BOOK3S_64 */
1183
1184 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1185         switch_booke_debug_regs(&new->thread.debug);
1186 #else
1187 /*
1188  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1189  * schedule DABR
1190  */
1191 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1192         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1193                 __set_breakpoint(&new->thread.hw_brk);
1194 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1195 #endif
1196
1197         /*
1198          * We need to save SPRs before treclaim/trecheckpoint as these will
1199          * change a number of them.
1200          */
1201         save_sprs(&prev->thread);
1202
1203         /* Save FPU, Altivec, VSX and SPE state */
1204         giveup_all(prev);
1205
1206         __switch_to_tm(prev, new);
1207
1208         if (!radix_enabled()) {
1209                 /*
1210                  * We can't take a PMU exception inside _switch() since there
1211                  * is a window where the kernel stack SLB and the kernel stack
1212                  * are out of sync. Hard disable here.
1213                  */
1214                 hard_irq_disable();
1215         }
1216
1217         /*
1218          * Call restore_sprs() before calling _switch(). If we move it after
1219          * _switch() then we miss out on calling it for new tasks. The reason
1220          * for this is we manually create a stack frame for new tasks that
1221          * directly returns through ret_from_fork() or
1222          * ret_from_kernel_thread(). See copy_thread() for details.
1223          */
1224         restore_sprs(old_thread, new_thread);
1225
1226         last = _switch(old_thread, new_thread);
1227
1228 #ifdef CONFIG_PPC_BOOK3S_64
1229         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1230                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1231                 batch = this_cpu_ptr(&ppc64_tlb_batch);
1232                 batch->active = 1;
1233         }
1234
1235         if (current_thread_info()->task->thread.regs) {
1236                 restore_math(current_thread_info()->task->thread.regs);
1237
1238                 /*
1239                  * The copy-paste buffer can only store into foreign real
1240                  * addresses, so unprivileged processes can not see the
1241                  * data or use it in any way unless they have foreign real
1242                  * mappings. If the new process has the foreign real address
1243                  * mappings, we must issue a cp_abort to clear any state and
1244                  * prevent snooping, corruption or a covert channel.
1245                  */
1246                 if (current_thread_info()->task->thread.used_vas)
1247                         asm volatile(PPC_CP_ABORT);
1248         }
1249 #endif /* CONFIG_PPC_BOOK3S_64 */
1250
1251         return last;
1252 }
1253
1254 #define NR_INSN_TO_PRINT        16
1255
1256 static void show_instructions(struct pt_regs *regs)
1257 {
1258         int i;
1259         unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1260
1261         printk("Instruction dump:");
1262
1263         for (i = 0; i < NR_INSN_TO_PRINT; i++) {
1264                 int instr;
1265
1266                 if (!(i % 8))
1267                         pr_cont("\n");
1268
1269 #if !defined(CONFIG_BOOKE)
1270                 /* If executing with the IMMU off, adjust pc rather
1271                  * than print XXXXXXXX.
1272                  */
1273                 if (!(regs->msr & MSR_IR))
1274                         pc = (unsigned long)phys_to_virt(pc);
1275 #endif
1276
1277                 if (!__kernel_text_address(pc) ||
1278                     probe_kernel_address((const void *)pc, instr)) {
1279                         pr_cont("XXXXXXXX ");
1280                 } else {
1281                         if (regs->nip == pc)
1282                                 pr_cont("<%08x> ", instr);
1283                         else
1284                                 pr_cont("%08x ", instr);
1285                 }
1286
1287                 pc += sizeof(int);
1288         }
1289
1290         pr_cont("\n");
1291 }
1292
1293 void show_user_instructions(struct pt_regs *regs)
1294 {
1295         unsigned long pc;
1296         int n = NR_INSN_TO_PRINT;
1297         struct seq_buf s;
1298         char buf[96]; /* enough for 8 times 9 + 2 chars */
1299
1300         pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1301
1302         /*
1303          * Make sure the NIP points at userspace, not kernel text/data or
1304          * elsewhere.
1305          */
1306         if (!__access_ok(pc, NR_INSN_TO_PRINT * sizeof(int), USER_DS)) {
1307                 pr_info("%s[%d]: Bad NIP, not dumping instructions.\n",
1308                         current->comm, current->pid);
1309                 return;
1310         }
1311
1312         seq_buf_init(&s, buf, sizeof(buf));
1313
1314         while (n) {
1315                 int i;
1316
1317                 seq_buf_clear(&s);
1318
1319                 for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) {
1320                         int instr;
1321
1322                         if (probe_kernel_address((const void *)pc, instr)) {
1323                                 seq_buf_printf(&s, "XXXXXXXX ");
1324                                 continue;
1325                         }
1326                         seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr);
1327                 }
1328
1329                 if (!seq_buf_has_overflowed(&s))
1330                         pr_info("%s[%d]: code: %s\n", current->comm,
1331                                 current->pid, s.buffer);
1332         }
1333 }
1334
1335 struct regbit {
1336         unsigned long bit;
1337         const char *name;
1338 };
1339
1340 static struct regbit msr_bits[] = {
1341 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1342         {MSR_SF,        "SF"},
1343         {MSR_HV,        "HV"},
1344 #endif
1345         {MSR_VEC,       "VEC"},
1346         {MSR_VSX,       "VSX"},
1347 #ifdef CONFIG_BOOKE
1348         {MSR_CE,        "CE"},
1349 #endif
1350         {MSR_EE,        "EE"},
1351         {MSR_PR,        "PR"},
1352         {MSR_FP,        "FP"},
1353         {MSR_ME,        "ME"},
1354 #ifdef CONFIG_BOOKE
1355         {MSR_DE,        "DE"},
1356 #else
1357         {MSR_SE,        "SE"},
1358         {MSR_BE,        "BE"},
1359 #endif
1360         {MSR_IR,        "IR"},
1361         {MSR_DR,        "DR"},
1362         {MSR_PMM,       "PMM"},
1363 #ifndef CONFIG_BOOKE
1364         {MSR_RI,        "RI"},
1365         {MSR_LE,        "LE"},
1366 #endif
1367         {0,             NULL}
1368 };
1369
1370 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1371 {
1372         const char *s = "";
1373
1374         for (; bits->bit; ++bits)
1375                 if (val & bits->bit) {
1376                         pr_cont("%s%s", s, bits->name);
1377                         s = sep;
1378                 }
1379 }
1380
1381 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1382 static struct regbit msr_tm_bits[] = {
1383         {MSR_TS_T,      "T"},
1384         {MSR_TS_S,      "S"},
1385         {MSR_TM,        "E"},
1386         {0,             NULL}
1387 };
1388
1389 static void print_tm_bits(unsigned long val)
1390 {
1391 /*
1392  * This only prints something if at least one of the TM bit is set.
1393  * Inside the TM[], the output means:
1394  *   E: Enabled         (bit 32)
1395  *   S: Suspended       (bit 33)
1396  *   T: Transactional   (bit 34)
1397  */
1398         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1399                 pr_cont(",TM[");
1400                 print_bits(val, msr_tm_bits, "");
1401                 pr_cont("]");
1402         }
1403 }
1404 #else
1405 static void print_tm_bits(unsigned long val) {}
1406 #endif
1407
1408 static void print_msr_bits(unsigned long val)
1409 {
1410         pr_cont("<");
1411         print_bits(val, msr_bits, ",");
1412         print_tm_bits(val);
1413         pr_cont(">");
1414 }
1415
1416 #ifdef CONFIG_PPC64
1417 #define REG             "%016lx"
1418 #define REGS_PER_LINE   4
1419 #define LAST_VOLATILE   13
1420 #else
1421 #define REG             "%08lx"
1422 #define REGS_PER_LINE   8
1423 #define LAST_VOLATILE   12
1424 #endif
1425
1426 void show_regs(struct pt_regs * regs)
1427 {
1428         int i, trap;
1429
1430         show_regs_print_info(KERN_DEFAULT);
1431
1432         printk("NIP:  "REG" LR: "REG" CTR: "REG"\n",
1433                regs->nip, regs->link, regs->ctr);
1434         printk("REGS: %px TRAP: %04lx   %s  (%s)\n",
1435                regs, regs->trap, print_tainted(), init_utsname()->release);
1436         printk("MSR:  "REG" ", regs->msr);
1437         print_msr_bits(regs->msr);
1438         pr_cont("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1439         trap = TRAP(regs);
1440         if ((TRAP(regs) != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1441                 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1442         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1443 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1444                 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1445 #else
1446                 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1447 #endif
1448 #ifdef CONFIG_PPC64
1449         pr_cont("IRQMASK: %lx ", regs->softe);
1450 #endif
1451 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1452         if (MSR_TM_ACTIVE(regs->msr))
1453                 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1454 #endif
1455
1456         for (i = 0;  i < 32;  i++) {
1457                 if ((i % REGS_PER_LINE) == 0)
1458                         pr_cont("\nGPR%02d: ", i);
1459                 pr_cont(REG " ", regs->gpr[i]);
1460                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1461                         break;
1462         }
1463         pr_cont("\n");
1464 #ifdef CONFIG_KALLSYMS
1465         /*
1466          * Lookup NIP late so we have the best change of getting the
1467          * above info out without failing
1468          */
1469         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1470         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1471 #endif
1472         show_stack(current, (unsigned long *) regs->gpr[1]);
1473         if (!user_mode(regs))
1474                 show_instructions(regs);
1475 }
1476
1477 void flush_thread(void)
1478 {
1479 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1480         flush_ptrace_hw_breakpoint(current);
1481 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1482         set_debug_reg_defaults(&current->thread);
1483 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1484 }
1485
1486 #ifdef CONFIG_PPC_BOOK3S_64
1487 void arch_setup_new_exec(void)
1488 {
1489         if (radix_enabled())
1490                 return;
1491         hash__setup_new_exec();
1492 }
1493 #endif
1494
1495 int set_thread_uses_vas(void)
1496 {
1497 #ifdef CONFIG_PPC_BOOK3S_64
1498         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1499                 return -EINVAL;
1500
1501         current->thread.used_vas = 1;
1502
1503         /*
1504          * Even a process that has no foreign real address mapping can use
1505          * an unpaired COPY instruction (to no real effect). Issue CP_ABORT
1506          * to clear any pending COPY and prevent a covert channel.
1507          *
1508          * __switch_to() will issue CP_ABORT on future context switches.
1509          */
1510         asm volatile(PPC_CP_ABORT);
1511
1512 #endif /* CONFIG_PPC_BOOK3S_64 */
1513         return 0;
1514 }
1515
1516 #ifdef CONFIG_PPC64
1517 /**
1518  * Assign a TIDR (thread ID) for task @t and set it in the thread
1519  * structure. For now, we only support setting TIDR for 'current' task.
1520  *
1521  * Since the TID value is a truncated form of it PID, it is possible
1522  * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1523  * that 2 threads share the same TID and are waiting, one of the following
1524  * cases will happen:
1525  *
1526  * 1. The correct thread is running, the wrong thread is not
1527  * In this situation, the correct thread is woken and proceeds to pass it's
1528  * condition check.
1529  *
1530  * 2. Neither threads are running
1531  * In this situation, neither thread will be woken. When scheduled, the waiting
1532  * threads will execute either a wait, which will return immediately, followed
1533  * by a condition check, which will pass for the correct thread and fail
1534  * for the wrong thread, or they will execute the condition check immediately.
1535  *
1536  * 3. The wrong thread is running, the correct thread is not
1537  * The wrong thread will be woken, but will fail it's condition check and
1538  * re-execute wait. The correct thread, when scheduled, will execute either
1539  * it's condition check (which will pass), or wait, which returns immediately
1540  * when called the first time after the thread is scheduled, followed by it's
1541  * condition check (which will pass).
1542  *
1543  * 4. Both threads are running
1544  * Both threads will be woken. The wrong thread will fail it's condition check
1545  * and execute another wait, while the correct thread will pass it's condition
1546  * check.
1547  *
1548  * @t: the task to set the thread ID for
1549  */
1550 int set_thread_tidr(struct task_struct *t)
1551 {
1552         if (!cpu_has_feature(CPU_FTR_P9_TIDR))
1553                 return -EINVAL;
1554
1555         if (t != current)
1556                 return -EINVAL;
1557
1558         if (t->thread.tidr)
1559                 return 0;
1560
1561         t->thread.tidr = (u16)task_pid_nr(t);
1562         mtspr(SPRN_TIDR, t->thread.tidr);
1563
1564         return 0;
1565 }
1566 EXPORT_SYMBOL_GPL(set_thread_tidr);
1567
1568 #endif /* CONFIG_PPC64 */
1569
1570 void
1571 release_thread(struct task_struct *t)
1572 {
1573 }
1574
1575 /*
1576  * this gets called so that we can store coprocessor state into memory and
1577  * copy the current task into the new thread.
1578  */
1579 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1580 {
1581         flush_all_to_thread(src);
1582         /*
1583          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1584          * flush but it removes the checkpointed state from the current CPU and
1585          * transitions the CPU out of TM mode.  Hence we need to call
1586          * tm_recheckpoint_new_task() (on the same task) to restore the
1587          * checkpointed state back and the TM mode.
1588          *
1589          * Can't pass dst because it isn't ready. Doesn't matter, passing
1590          * dst is only important for __switch_to()
1591          */
1592         __switch_to_tm(src, src);
1593
1594         *dst = *src;
1595
1596         clear_task_ebb(dst);
1597
1598         return 0;
1599 }
1600
1601 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1602 {
1603 #ifdef CONFIG_PPC_BOOK3S_64
1604         unsigned long sp_vsid;
1605         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1606
1607         if (radix_enabled())
1608                 return;
1609
1610         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1611                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1612                         << SLB_VSID_SHIFT_1T;
1613         else
1614                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1615                         << SLB_VSID_SHIFT;
1616         sp_vsid |= SLB_VSID_KERNEL | llp;
1617         p->thread.ksp_vsid = sp_vsid;
1618 #endif
1619 }
1620
1621 /*
1622  * Copy a thread..
1623  */
1624
1625 /*
1626  * Copy architecture-specific thread state
1627  */
1628 int copy_thread(unsigned long clone_flags, unsigned long usp,
1629                 unsigned long kthread_arg, struct task_struct *p)
1630 {
1631         struct pt_regs *childregs, *kregs;
1632         extern void ret_from_fork(void);
1633         extern void ret_from_kernel_thread(void);
1634         void (*f)(void);
1635         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1636         struct thread_info *ti = task_thread_info(p);
1637
1638         klp_init_thread_info(ti);
1639
1640         /* Copy registers */
1641         sp -= sizeof(struct pt_regs);
1642         childregs = (struct pt_regs *) sp;
1643         if (unlikely(p->flags & PF_KTHREAD)) {
1644                 /* kernel thread */
1645                 memset(childregs, 0, sizeof(struct pt_regs));
1646                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1647                 /* function */
1648                 if (usp)
1649                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1650 #ifdef CONFIG_PPC64
1651                 clear_tsk_thread_flag(p, TIF_32BIT);
1652                 childregs->softe = IRQS_ENABLED;
1653 #endif
1654                 childregs->gpr[15] = kthread_arg;
1655                 p->thread.regs = NULL;  /* no user register state */
1656                 ti->flags |= _TIF_RESTOREALL;
1657                 f = ret_from_kernel_thread;
1658         } else {
1659                 /* user thread */
1660                 struct pt_regs *regs = current_pt_regs();
1661                 CHECK_FULL_REGS(regs);
1662                 *childregs = *regs;
1663                 if (usp)
1664                         childregs->gpr[1] = usp;
1665                 p->thread.regs = childregs;
1666                 childregs->gpr[3] = 0;  /* Result from fork() */
1667                 if (clone_flags & CLONE_SETTLS) {
1668 #ifdef CONFIG_PPC64
1669                         if (!is_32bit_task())
1670                                 childregs->gpr[13] = childregs->gpr[6];
1671                         else
1672 #endif
1673                                 childregs->gpr[2] = childregs->gpr[6];
1674                 }
1675
1676                 f = ret_from_fork;
1677         }
1678         childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1679         sp -= STACK_FRAME_OVERHEAD;
1680
1681         /*
1682          * The way this works is that at some point in the future
1683          * some task will call _switch to switch to the new task.
1684          * That will pop off the stack frame created below and start
1685          * the new task running at ret_from_fork.  The new task will
1686          * do some house keeping and then return from the fork or clone
1687          * system call, using the stack frame created above.
1688          */
1689         ((unsigned long *)sp)[0] = 0;
1690         sp -= sizeof(struct pt_regs);
1691         kregs = (struct pt_regs *) sp;
1692         sp -= STACK_FRAME_OVERHEAD;
1693         p->thread.ksp = sp;
1694 #ifdef CONFIG_PPC32
1695         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1696                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1697 #endif
1698 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1699         p->thread.ptrace_bps[0] = NULL;
1700 #endif
1701
1702         p->thread.fp_save_area = NULL;
1703 #ifdef CONFIG_ALTIVEC
1704         p->thread.vr_save_area = NULL;
1705 #endif
1706
1707         setup_ksp_vsid(p, sp);
1708
1709 #ifdef CONFIG_PPC64
1710         if (cpu_has_feature(CPU_FTR_DSCR)) {
1711                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1712                 p->thread.dscr = mfspr(SPRN_DSCR);
1713         }
1714         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1715                 childregs->ppr = DEFAULT_PPR;
1716
1717         p->thread.tidr = 0;
1718 #endif
1719         kregs->nip = ppc_function_entry(f);
1720         return 0;
1721 }
1722
1723 void preload_new_slb_context(unsigned long start, unsigned long sp);
1724
1725 /*
1726  * Set up a thread for executing a new program
1727  */
1728 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1729 {
1730 #ifdef CONFIG_PPC64
1731         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1732
1733 #ifdef CONFIG_PPC_BOOK3S_64
1734         preload_new_slb_context(start, sp);
1735 #endif
1736 #endif
1737
1738         /*
1739          * If we exec out of a kernel thread then thread.regs will not be
1740          * set.  Do it now.
1741          */
1742         if (!current->thread.regs) {
1743                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1744                 current->thread.regs = regs - 1;
1745         }
1746
1747 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1748         /*
1749          * Clear any transactional state, we're exec()ing. The cause is
1750          * not important as there will never be a recheckpoint so it's not
1751          * user visible.
1752          */
1753         if (MSR_TM_SUSPENDED(mfmsr()))
1754                 tm_reclaim_current(0);
1755 #endif
1756
1757         memset(regs->gpr, 0, sizeof(regs->gpr));
1758         regs->ctr = 0;
1759         regs->link = 0;
1760         regs->xer = 0;
1761         regs->ccr = 0;
1762         regs->gpr[1] = sp;
1763
1764         /*
1765          * We have just cleared all the nonvolatile GPRs, so make
1766          * FULL_REGS(regs) return true.  This is necessary to allow
1767          * ptrace to examine the thread immediately after exec.
1768          */
1769         regs->trap &= ~1UL;
1770
1771 #ifdef CONFIG_PPC32
1772         regs->mq = 0;
1773         regs->nip = start;
1774         regs->msr = MSR_USER;
1775 #else
1776         if (!is_32bit_task()) {
1777                 unsigned long entry;
1778
1779                 if (is_elf2_task()) {
1780                         /* Look ma, no function descriptors! */
1781                         entry = start;
1782
1783                         /*
1784                          * Ulrich says:
1785                          *   The latest iteration of the ABI requires that when
1786                          *   calling a function (at its global entry point),
1787                          *   the caller must ensure r12 holds the entry point
1788                          *   address (so that the function can quickly
1789                          *   establish addressability).
1790                          */
1791                         regs->gpr[12] = start;
1792                         /* Make sure that's restored on entry to userspace. */
1793                         set_thread_flag(TIF_RESTOREALL);
1794                 } else {
1795                         unsigned long toc;
1796
1797                         /* start is a relocated pointer to the function
1798                          * descriptor for the elf _start routine.  The first
1799                          * entry in the function descriptor is the entry
1800                          * address of _start and the second entry is the TOC
1801                          * value we need to use.
1802                          */
1803                         __get_user(entry, (unsigned long __user *)start);
1804                         __get_user(toc, (unsigned long __user *)start+1);
1805
1806                         /* Check whether the e_entry function descriptor entries
1807                          * need to be relocated before we can use them.
1808                          */
1809                         if (load_addr != 0) {
1810                                 entry += load_addr;
1811                                 toc   += load_addr;
1812                         }
1813                         regs->gpr[2] = toc;
1814                 }
1815                 regs->nip = entry;
1816                 regs->msr = MSR_USER64;
1817         } else {
1818                 regs->nip = start;
1819                 regs->gpr[2] = 0;
1820                 regs->msr = MSR_USER32;
1821         }
1822 #endif
1823 #ifdef CONFIG_VSX
1824         current->thread.used_vsr = 0;
1825 #endif
1826         current->thread.load_slb = 0;
1827         current->thread.load_fp = 0;
1828         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1829         current->thread.fp_save_area = NULL;
1830 #ifdef CONFIG_ALTIVEC
1831         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1832         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1833         current->thread.vr_save_area = NULL;
1834         current->thread.vrsave = 0;
1835         current->thread.used_vr = 0;
1836         current->thread.load_vec = 0;
1837 #endif /* CONFIG_ALTIVEC */
1838 #ifdef CONFIG_SPE
1839         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1840         current->thread.acc = 0;
1841         current->thread.spefscr = 0;
1842         current->thread.used_spe = 0;
1843 #endif /* CONFIG_SPE */
1844 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1845         current->thread.tm_tfhar = 0;
1846         current->thread.tm_texasr = 0;
1847         current->thread.tm_tfiar = 0;
1848         current->thread.load_tm = 0;
1849 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1850
1851         thread_pkey_regs_init(&current->thread);
1852 }
1853 EXPORT_SYMBOL(start_thread);
1854
1855 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1856                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1857
1858 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1859 {
1860         struct pt_regs *regs = tsk->thread.regs;
1861
1862         /* This is a bit hairy.  If we are an SPE enabled  processor
1863          * (have embedded fp) we store the IEEE exception enable flags in
1864          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1865          * mode (asyn, precise, disabled) for 'Classic' FP. */
1866         if (val & PR_FP_EXC_SW_ENABLE) {
1867 #ifdef CONFIG_SPE
1868                 if (cpu_has_feature(CPU_FTR_SPE)) {
1869                         /*
1870                          * When the sticky exception bits are set
1871                          * directly by userspace, it must call prctl
1872                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1873                          * in the existing prctl settings) or
1874                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1875                          * the bits being set).  <fenv.h> functions
1876                          * saving and restoring the whole
1877                          * floating-point environment need to do so
1878                          * anyway to restore the prctl settings from
1879                          * the saved environment.
1880                          */
1881                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1882                         tsk->thread.fpexc_mode = val &
1883                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1884                         return 0;
1885                 } else {
1886                         return -EINVAL;
1887                 }
1888 #else
1889                 return -EINVAL;
1890 #endif
1891         }
1892
1893         /* on a CONFIG_SPE this does not hurt us.  The bits that
1894          * __pack_fe01 use do not overlap with bits used for
1895          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1896          * on CONFIG_SPE implementations are reserved so writing to
1897          * them does not change anything */
1898         if (val > PR_FP_EXC_PRECISE)
1899                 return -EINVAL;
1900         tsk->thread.fpexc_mode = __pack_fe01(val);
1901         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1902                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1903                         | tsk->thread.fpexc_mode;
1904         return 0;
1905 }
1906
1907 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1908 {
1909         unsigned int val;
1910
1911         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1912 #ifdef CONFIG_SPE
1913                 if (cpu_has_feature(CPU_FTR_SPE)) {
1914                         /*
1915                          * When the sticky exception bits are set
1916                          * directly by userspace, it must call prctl
1917                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1918                          * in the existing prctl settings) or
1919                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1920                          * the bits being set).  <fenv.h> functions
1921                          * saving and restoring the whole
1922                          * floating-point environment need to do so
1923                          * anyway to restore the prctl settings from
1924                          * the saved environment.
1925                          */
1926                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1927                         val = tsk->thread.fpexc_mode;
1928                 } else
1929                         return -EINVAL;
1930 #else
1931                 return -EINVAL;
1932 #endif
1933         else
1934                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1935         return put_user(val, (unsigned int __user *) adr);
1936 }
1937
1938 int set_endian(struct task_struct *tsk, unsigned int val)
1939 {
1940         struct pt_regs *regs = tsk->thread.regs;
1941
1942         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1943             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1944                 return -EINVAL;
1945
1946         if (regs == NULL)
1947                 return -EINVAL;
1948
1949         if (val == PR_ENDIAN_BIG)
1950                 regs->msr &= ~MSR_LE;
1951         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1952                 regs->msr |= MSR_LE;
1953         else
1954                 return -EINVAL;
1955
1956         return 0;
1957 }
1958
1959 int get_endian(struct task_struct *tsk, unsigned long adr)
1960 {
1961         struct pt_regs *regs = tsk->thread.regs;
1962         unsigned int val;
1963
1964         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1965             !cpu_has_feature(CPU_FTR_REAL_LE))
1966                 return -EINVAL;
1967
1968         if (regs == NULL)
1969                 return -EINVAL;
1970
1971         if (regs->msr & MSR_LE) {
1972                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1973                         val = PR_ENDIAN_LITTLE;
1974                 else
1975                         val = PR_ENDIAN_PPC_LITTLE;
1976         } else
1977                 val = PR_ENDIAN_BIG;
1978
1979         return put_user(val, (unsigned int __user *)adr);
1980 }
1981
1982 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1983 {
1984         tsk->thread.align_ctl = val;
1985         return 0;
1986 }
1987
1988 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1989 {
1990         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1991 }
1992
1993 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1994                                   unsigned long nbytes)
1995 {
1996         unsigned long stack_page;
1997         unsigned long cpu = task_cpu(p);
1998
1999         /*
2000          * Avoid crashing if the stack has overflowed and corrupted
2001          * task_cpu(p), which is in the thread_info struct.
2002          */
2003         if (cpu < NR_CPUS && cpu_possible(cpu)) {
2004                 stack_page = (unsigned long) hardirq_ctx[cpu];
2005                 if (sp >= stack_page + sizeof(struct thread_struct)
2006                     && sp <= stack_page + THREAD_SIZE - nbytes)
2007                         return 1;
2008
2009                 stack_page = (unsigned long) softirq_ctx[cpu];
2010                 if (sp >= stack_page + sizeof(struct thread_struct)
2011                     && sp <= stack_page + THREAD_SIZE - nbytes)
2012                         return 1;
2013         }
2014         return 0;
2015 }
2016
2017 int validate_sp(unsigned long sp, struct task_struct *p,
2018                        unsigned long nbytes)
2019 {
2020         unsigned long stack_page = (unsigned long)task_stack_page(p);
2021
2022         if (sp >= stack_page + sizeof(struct thread_struct)
2023             && sp <= stack_page + THREAD_SIZE - nbytes)
2024                 return 1;
2025
2026         return valid_irq_stack(sp, p, nbytes);
2027 }
2028
2029 EXPORT_SYMBOL(validate_sp);
2030
2031 unsigned long get_wchan(struct task_struct *p)
2032 {
2033         unsigned long ip, sp;
2034         int count = 0;
2035
2036         if (!p || p == current || p->state == TASK_RUNNING)
2037                 return 0;
2038
2039         sp = p->thread.ksp;
2040         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
2041                 return 0;
2042
2043         do {
2044                 sp = *(unsigned long *)sp;
2045                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) ||
2046                     p->state == TASK_RUNNING)
2047                         return 0;
2048                 if (count > 0) {
2049                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
2050                         if (!in_sched_functions(ip))
2051                                 return ip;
2052                 }
2053         } while (count++ < 16);
2054         return 0;
2055 }
2056
2057 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
2058
2059 void show_stack(struct task_struct *tsk, unsigned long *stack)
2060 {
2061         unsigned long sp, ip, lr, newsp;
2062         int count = 0;
2063         int firstframe = 1;
2064 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2065         int curr_frame = current->curr_ret_stack;
2066         extern void return_to_handler(void);
2067         unsigned long rth = (unsigned long)return_to_handler;
2068 #endif
2069
2070         sp = (unsigned long) stack;
2071         if (tsk == NULL)
2072                 tsk = current;
2073         if (sp == 0) {
2074                 if (tsk == current)
2075                         sp = current_stack_pointer();
2076                 else
2077                         sp = tsk->thread.ksp;
2078         }
2079
2080         lr = 0;
2081         printk("Call Trace:\n");
2082         do {
2083                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
2084                         return;
2085
2086                 stack = (unsigned long *) sp;
2087                 newsp = stack[0];
2088                 ip = stack[STACK_FRAME_LR_SAVE];
2089                 if (!firstframe || ip != lr) {
2090                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
2091 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2092                         if ((ip == rth) && curr_frame >= 0) {
2093                                 pr_cont(" (%pS)",
2094                                        (void *)current->ret_stack[curr_frame].ret);
2095                                 curr_frame--;
2096                         }
2097 #endif
2098                         if (firstframe)
2099                                 pr_cont(" (unreliable)");
2100                         pr_cont("\n");
2101                 }
2102                 firstframe = 0;
2103
2104                 /*
2105                  * See if this is an exception frame.
2106                  * We look for the "regshere" marker in the current frame.
2107                  */
2108                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
2109                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
2110                         struct pt_regs *regs = (struct pt_regs *)
2111                                 (sp + STACK_FRAME_OVERHEAD);
2112                         lr = regs->link;
2113                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
2114                                regs->trap, (void *)regs->nip, (void *)lr);
2115                         firstframe = 1;
2116                 }
2117
2118                 sp = newsp;
2119         } while (count++ < kstack_depth_to_print);
2120 }
2121
2122 #ifdef CONFIG_PPC64
2123 /* Called with hard IRQs off */
2124 void notrace __ppc64_runlatch_on(void)
2125 {
2126         struct thread_info *ti = current_thread_info();
2127
2128         if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2129                 /*
2130                  * Least significant bit (RUN) is the only writable bit of
2131                  * the CTRL register, so we can avoid mfspr. 2.06 is not the
2132                  * earliest ISA where this is the case, but it's convenient.
2133                  */
2134                 mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
2135         } else {
2136                 unsigned long ctrl;
2137
2138                 /*
2139                  * Some architectures (e.g., Cell) have writable fields other
2140                  * than RUN, so do the read-modify-write.
2141                  */
2142                 ctrl = mfspr(SPRN_CTRLF);
2143                 ctrl |= CTRL_RUNLATCH;
2144                 mtspr(SPRN_CTRLT, ctrl);
2145         }
2146
2147         ti->local_flags |= _TLF_RUNLATCH;
2148 }
2149
2150 /* Called with hard IRQs off */
2151 void notrace __ppc64_runlatch_off(void)
2152 {
2153         struct thread_info *ti = current_thread_info();
2154
2155         ti->local_flags &= ~_TLF_RUNLATCH;
2156
2157         if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2158                 mtspr(SPRN_CTRLT, 0);
2159         } else {
2160                 unsigned long ctrl;
2161
2162                 ctrl = mfspr(SPRN_CTRLF);
2163                 ctrl &= ~CTRL_RUNLATCH;
2164                 mtspr(SPRN_CTRLT, ctrl);
2165         }
2166 }
2167 #endif /* CONFIG_PPC64 */
2168
2169 unsigned long arch_align_stack(unsigned long sp)
2170 {
2171         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2172                 sp -= get_random_int() & ~PAGE_MASK;
2173         return sp & ~0xf;
2174 }
2175
2176 static inline unsigned long brk_rnd(void)
2177 {
2178         unsigned long rnd = 0;
2179
2180         /* 8MB for 32bit, 1GB for 64bit */
2181         if (is_32bit_task())
2182                 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
2183         else
2184                 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
2185
2186         return rnd << PAGE_SHIFT;
2187 }
2188
2189 unsigned long arch_randomize_brk(struct mm_struct *mm)
2190 {
2191         unsigned long base = mm->brk;
2192         unsigned long ret;
2193
2194 #ifdef CONFIG_PPC_BOOK3S_64
2195         /*
2196          * If we are using 1TB segments and we are allowed to randomise
2197          * the heap, we can put it above 1TB so it is backed by a 1TB
2198          * segment. Otherwise the heap will be in the bottom 1TB
2199          * which always uses 256MB segments and this may result in a
2200          * performance penalty. We don't need to worry about radix. For
2201          * radix, mmu_highuser_ssize remains unchanged from 256MB.
2202          */
2203         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2204                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2205 #endif
2206
2207         ret = PAGE_ALIGN(base + brk_rnd());
2208
2209         if (ret < mm->brk)
2210                 return mm->brk;
2211
2212         return ret;
2213 }
2214