arch/powerpc/include/asm/opal.h

   1 /*
   2  * PowerNV OPAL definitions.
   3  *
   4  * Copyright 2011 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef __OPAL_H
  13 #define __OPAL_H
  14
  15 /****** Takeover interface ********/
  16
  17 /* PAPR H-Call used to querty the HAL existence and/or instanciate
  18  * it from within pHyp (tech preview only).
  19  *
  20  * This is exclusively used in prom_init.c
  21  */
  22
  23 #ifndef __ASSEMBLY__
  24
  25 struct opal_takeover_args {
  26         u64     k_image;                /* r4 */
  27         u64     k_size;                 /* r5 */
  28         u64     k_entry;                /* r6 */
  29         u64     k_entry2;               /* r7 */
  30         u64     hal_addr;               /* r8 */
  31         u64     rd_image;               /* r9 */
  32         u64     rd_size;                /* r10 */
  33         u64     rd_loc;                 /* r11 */
  34 };
  35
  36 /*
  37  * SG entry
  38  *
  39  * WARNING: The current implementation requires each entry
  40  * to represent a block that is 4k aligned *and* each block
  41  * size except the last one in the list to be as well.
  42  */
  43 struct opal_sg_entry {
  44         void    *data;
  45         long    length;
  46 };
  47
  48 /* sg list */
  49 struct opal_sg_list {
  50         unsigned long num_entries;
  51         struct opal_sg_list *next;
  52         struct opal_sg_entry entry[];
  53 };
  54
  55 /* We calculate number of sg entries based on PAGE_SIZE */
  56 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
  57
  58 extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
  59
  60 extern long opal_do_takeover(struct opal_takeover_args *args);
  61
  62 struct rtas_args;
  63 extern int opal_enter_rtas(struct rtas_args *args,
  64                            unsigned long data,
  65                            unsigned long entry);
  66
  67 #endif /* __ASSEMBLY__ */
  68
  69 /****** OPAL APIs ******/
  70
  71 /* Return codes */
  72 #define OPAL_SUCCESS            0
  73 #define OPAL_PARAMETER          -1
  74 #define OPAL_BUSY               -2
  75 #define OPAL_PARTIAL            -3
  76 #define OPAL_CONSTRAINED        -4
  77 #define OPAL_CLOSED             -5
  78 #define OPAL_HARDWARE           -6
  79 #define OPAL_UNSUPPORTED        -7
  80 #define OPAL_PERMISSION         -8
  81 #define OPAL_NO_MEM             -9
  82 #define OPAL_RESOURCE           -10
  83 #define OPAL_INTERNAL_ERROR     -11
  84 #define OPAL_BUSY_EVENT         -12
  85 #define OPAL_HARDWARE_FROZEN    -13
  86
  87 /* API Tokens (in r0) */
  88 #define OPAL_CONSOLE_WRITE                      1
  89 #define OPAL_CONSOLE_READ                       2
  90 #define OPAL_RTC_READ                           3
  91 #define OPAL_RTC_WRITE                          4
  92 #define OPAL_CEC_POWER_DOWN                     5
  93 #define OPAL_CEC_REBOOT                         6
  94 #define OPAL_READ_NVRAM                         7
  95 #define OPAL_WRITE_NVRAM                        8
  96 #define OPAL_HANDLE_INTERRUPT                   9
  97 #define OPAL_POLL_EVENTS                        10
  98 #define OPAL_PCI_SET_HUB_TCE_MEMORY             11
  99 #define OPAL_PCI_SET_PHB_TCE_MEMORY             12
 100 #define OPAL_PCI_CONFIG_READ_BYTE               13
 101 #define OPAL_PCI_CONFIG_READ_HALF_WORD          14
 102 #define OPAL_PCI_CONFIG_READ_WORD               15
 103 #define OPAL_PCI_CONFIG_WRITE_BYTE              16
 104 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD         17
 105 #define OPAL_PCI_CONFIG_WRITE_WORD              18
 106 #define OPAL_SET_XIVE                           19
 107 #define OPAL_GET_XIVE                           20
 108 #define OPAL_GET_COMPLETION_TOKEN_STATUS        21 /* obsolete */
 109 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER    22
 110 #define OPAL_PCI_EEH_FREEZE_STATUS              23
 111 #define OPAL_PCI_SHPC                           24
 112 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE         25
 113 #define OPAL_PCI_EEH_FREEZE_CLEAR               26
 114 #define OPAL_PCI_PHB_MMIO_ENABLE                27
 115 #define OPAL_PCI_SET_PHB_MEM_WINDOW             28
 116 #define OPAL_PCI_MAP_PE_MMIO_WINDOW             29
 117 #define OPAL_PCI_SET_PHB_TABLE_MEMORY           30
 118 #define OPAL_PCI_SET_PE                         31
 119 #define OPAL_PCI_SET_PELTV                      32
 120 #define OPAL_PCI_SET_MVE                        33
 121 #define OPAL_PCI_SET_MVE_ENABLE                 34
 122 #define OPAL_PCI_GET_XIVE_REISSUE               35
 123 #define OPAL_PCI_SET_XIVE_REISSUE               36
 124 #define OPAL_PCI_SET_XIVE_PE                    37
 125 #define OPAL_GET_XIVE_SOURCE                    38
 126 #define OPAL_GET_MSI_32                         39
 127 #define OPAL_GET_MSI_64                         40
 128 #define OPAL_START_CPU                          41
 129 #define OPAL_QUERY_CPU_STATUS                   42
 130 #define OPAL_WRITE_OPPANEL                      43
 131 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
 132 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
 133 #define OPAL_PCI_RESET                          49
 134 #define OPAL_PCI_GET_HUB_DIAG_DATA              50
 135 #define OPAL_PCI_GET_PHB_DIAG_DATA              51
 136 #define OPAL_PCI_FENCE_PHB                      52
 137 #define OPAL_PCI_REINIT                         53
 138 #define OPAL_PCI_MASK_PE_ERROR                  54
 139 #define OPAL_SET_SLOT_LED_STATUS                55
 140 #define OPAL_GET_EPOW_STATUS                    56
 141 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
 142 #define OPAL_RESERVED1                          58
 143 #define OPAL_RESERVED2                          59
 144 #define OPAL_PCI_NEXT_ERROR                     60
 145 #define OPAL_PCI_EEH_FREEZE_STATUS2             61
 146 #define OPAL_PCI_POLL                           62
 147 #define OPAL_PCI_MSI_EOI                        63
 148 #define OPAL_PCI_GET_PHB_DIAG_DATA2             64
 149 #define OPAL_XSCOM_READ                         65
 150 #define OPAL_XSCOM_WRITE                        66
 151 #define OPAL_LPC_READ                           67
 152 #define OPAL_LPC_WRITE                          68
 153 #define OPAL_RETURN_CPU                         69
 154 #define OPAL_FLASH_VALIDATE                     76
 155 #define OPAL_FLASH_MANAGE                       77
 156 #define OPAL_FLASH_UPDATE                       78
 157 #define OPAL_GET_MSG                            85
 158 #define OPAL_CHECK_ASYNC_COMPLETION             86
 159 #define OPAL_SYNC_HOST_REBOOT                   87
 160
 161 #ifndef __ASSEMBLY__
 162
 163 /* Other enums */
 164 enum OpalVendorApiTokens {
 165         OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
 166 };
 167
 168 enum OpalFreezeState {
 169         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
 170         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
 171         OPAL_EEH_STOPPED_DMA_FREEZE = 2,
 172         OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
 173         OPAL_EEH_STOPPED_RESET = 4,
 174         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
 175         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 176 };
 177
 178 enum OpalEehFreezeActionToken {
 179         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
 180         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
 181         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
 182 };
 183
 184 enum OpalPciStatusToken {
 185         OPAL_EEH_NO_ERROR       = 0,
 186         OPAL_EEH_IOC_ERROR      = 1,
 187         OPAL_EEH_PHB_ERROR      = 2,
 188         OPAL_EEH_PE_ERROR       = 3,
 189         OPAL_EEH_PE_MMIO_ERROR  = 4,
 190         OPAL_EEH_PE_DMA_ERROR   = 5
 191 };
 192
 193 enum OpalPciErrorSeverity {
 194         OPAL_EEH_SEV_NO_ERROR   = 0,
 195         OPAL_EEH_SEV_IOC_DEAD   = 1,
 196         OPAL_EEH_SEV_PHB_DEAD   = 2,
 197         OPAL_EEH_SEV_PHB_FENCED = 3,
 198         OPAL_EEH_SEV_PE_ER      = 4,
 199         OPAL_EEH_SEV_INF        = 5
 200 };
 201
 202 enum OpalShpcAction {
 203         OPAL_SHPC_GET_LINK_STATE = 0,
 204         OPAL_SHPC_GET_SLOT_STATE = 1
 205 };
 206
 207 enum OpalShpcLinkState {
 208         OPAL_SHPC_LINK_DOWN = 0,
 209         OPAL_SHPC_LINK_UP = 1
 210 };
 211
 212 enum OpalMmioWindowType {
 213         OPAL_M32_WINDOW_TYPE = 1,
 214         OPAL_M64_WINDOW_TYPE = 2,
 215         OPAL_IO_WINDOW_TYPE = 3
 216 };
 217
 218 enum OpalShpcSlotState {
 219         OPAL_SHPC_DEV_NOT_PRESENT = 0,
 220         OPAL_SHPC_DEV_PRESENT = 1
 221 };
 222
 223 enum OpalExceptionHandler {
 224         OPAL_MACHINE_CHECK_HANDLER = 1,
 225         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
 226         OPAL_SOFTPATCH_HANDLER = 3
 227 };
 228
 229 enum OpalPendingState {
 230         OPAL_EVENT_OPAL_INTERNAL        = 0x1,
 231         OPAL_EVENT_NVRAM                = 0x2,
 232         OPAL_EVENT_RTC                  = 0x4,
 233         OPAL_EVENT_CONSOLE_OUTPUT       = 0x8,
 234         OPAL_EVENT_CONSOLE_INPUT        = 0x10,
 235         OPAL_EVENT_ERROR_LOG_AVAIL      = 0x20,
 236         OPAL_EVENT_ERROR_LOG            = 0x40,
 237         OPAL_EVENT_EPOW                 = 0x80,
 238         OPAL_EVENT_LED_STATUS           = 0x100,
 239         OPAL_EVENT_PCI_ERROR            = 0x200,
 240         OPAL_EVENT_MSG_PENDING          = 0x800,
 241 };
 242
 243 enum OpalMessageType {
 244         OPAL_MSG_ASYNC_COMP             = 0,
 245         OPAL_MSG_MEM_ERR,
 246         OPAL_MSG_EPOW,
 247         OPAL_MSG_SHUTDOWN,
 248         OPAL_MSG_TYPE_MAX,
 249 };
 250
 251 /* Machine check related definitions */
 252 enum OpalMCE_Version {
 253         OpalMCE_V1 = 1,
 254 };
 255
 256 enum OpalMCE_Severity {
 257         OpalMCE_SEV_NO_ERROR = 0,
 258         OpalMCE_SEV_WARNING = 1,
 259         OpalMCE_SEV_ERROR_SYNC = 2,
 260         OpalMCE_SEV_FATAL = 3,
 261 };
 262
 263 enum OpalMCE_Disposition {
 264         OpalMCE_DISPOSITION_RECOVERED = 0,
 265         OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
 266 };
 267
 268 enum OpalMCE_Initiator {
 269         OpalMCE_INITIATOR_UNKNOWN = 0,
 270         OpalMCE_INITIATOR_CPU = 1,
 271 };
 272
 273 enum OpalMCE_ErrorType {
 274         OpalMCE_ERROR_TYPE_UNKNOWN = 0,
 275         OpalMCE_ERROR_TYPE_UE = 1,
 276         OpalMCE_ERROR_TYPE_SLB = 2,
 277         OpalMCE_ERROR_TYPE_ERAT = 3,
 278         OpalMCE_ERROR_TYPE_TLB = 4,
 279 };
 280
 281 enum OpalMCE_UeErrorType {
 282         OpalMCE_UE_ERROR_INDETERMINATE = 0,
 283         OpalMCE_UE_ERROR_IFETCH = 1,
 284         OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
 285         OpalMCE_UE_ERROR_LOAD_STORE = 3,
 286         OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
 287 };
 288
 289 enum OpalMCE_SlbErrorType {
 290         OpalMCE_SLB_ERROR_INDETERMINATE = 0,
 291         OpalMCE_SLB_ERROR_PARITY = 1,
 292         OpalMCE_SLB_ERROR_MULTIHIT = 2,
 293 };
 294
 295 enum OpalMCE_EratErrorType {
 296         OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
 297         OpalMCE_ERAT_ERROR_PARITY = 1,
 298         OpalMCE_ERAT_ERROR_MULTIHIT = 2,
 299 };
 300
 301 enum OpalMCE_TlbErrorType {
 302         OpalMCE_TLB_ERROR_INDETERMINATE = 0,
 303         OpalMCE_TLB_ERROR_PARITY = 1,
 304         OpalMCE_TLB_ERROR_MULTIHIT = 2,
 305 };
 306
 307 enum OpalThreadStatus {
 308         OPAL_THREAD_INACTIVE = 0x0,
 309         OPAL_THREAD_STARTED = 0x1,
 310         OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
 311 };
 312
 313 enum OpalPciBusCompare {
 314         OpalPciBusAny   = 0,    /* Any bus number match */
 315         OpalPciBus3Bits = 2,    /* Match top 3 bits of bus number */
 316         OpalPciBus4Bits = 3,    /* Match top 4 bits of bus number */
 317         OpalPciBus5Bits = 4,    /* Match top 5 bits of bus number */
 318         OpalPciBus6Bits = 5,    /* Match top 6 bits of bus number */
 319         OpalPciBus7Bits = 6,    /* Match top 7 bits of bus number */
 320         OpalPciBusAll   = 7,    /* Match bus number exactly */
 321 };
 322
 323 enum OpalDeviceCompare {
 324         OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
 325         OPAL_COMPARE_RID_DEVICE_NUMBER = 1
 326 };
 327
 328 enum OpalFuncCompare {
 329         OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
 330         OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
 331 };
 332
 333 enum OpalPeAction {
 334         OPAL_UNMAP_PE = 0,
 335         OPAL_MAP_PE = 1
 336 };
 337
 338 enum OpalPeltvAction {
 339         OPAL_REMOVE_PE_FROM_DOMAIN = 0,
 340         OPAL_ADD_PE_TO_DOMAIN = 1
 341 };
 342
 343 enum OpalMveEnableAction {
 344         OPAL_DISABLE_MVE = 0,
 345         OPAL_ENABLE_MVE = 1
 346 };
 347
 348 enum OpalPciResetScope {
 349         OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
 350         OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
 351         OPAL_PCI_IODA_TABLE_RESET = 6,
 352 };
 353
 354 enum OpalPciReinitScope {
 355         OPAL_REINIT_PCI_DEV = 1000
 356 };
 357
 358 enum OpalPciResetState {
 359         OPAL_DEASSERT_RESET = 0,
 360         OPAL_ASSERT_RESET = 1
 361 };
 362
 363 enum OpalPciMaskAction {
 364         OPAL_UNMASK_ERROR_TYPE = 0,
 365         OPAL_MASK_ERROR_TYPE = 1
 366 };
 367
 368 enum OpalSlotLedType {
 369         OPAL_SLOT_LED_ID_TYPE = 0,
 370         OPAL_SLOT_LED_FAULT_TYPE = 1
 371 };
 372
 373 enum OpalLedAction {
 374         OPAL_TURN_OFF_LED = 0,
 375         OPAL_TURN_ON_LED = 1,
 376         OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
 377 };
 378
 379 enum OpalEpowStatus {
 380         OPAL_EPOW_NONE = 0,
 381         OPAL_EPOW_UPS = 1,
 382         OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
 383         OPAL_EPOW_OVER_INTERNAL_TEMP = 3
 384 };
 385
 386 /*
 387  * Address cycle types for LPC accesses. These also correspond
 388  * to the content of the first cell of the "reg" property for
 389  * device nodes on the LPC bus
 390  */
 391 enum OpalLPCAddressType {
 392         OPAL_LPC_MEM    = 0,
 393         OPAL_LPC_IO     = 1,
 394         OPAL_LPC_FW     = 2,
 395 };
 396
 397 struct opal_msg {
 398         uint32_t msg_type;
 399         uint32_t reserved;
 400         uint64_t params[8];
 401 };
 402
 403 struct opal_machine_check_event {
 404         enum OpalMCE_Version    version:8;      /* 0x00 */
 405         uint8_t                 in_use;         /* 0x01 */
 406         enum OpalMCE_Severity   severity:8;     /* 0x02 */
 407         enum OpalMCE_Initiator  initiator:8;    /* 0x03 */
 408         enum OpalMCE_ErrorType  error_type:8;   /* 0x04 */
 409         enum OpalMCE_Disposition disposition:8; /* 0x05 */
 410         uint8_t                 reserved_1[2];  /* 0x06 */
 411         uint64_t                gpr3;           /* 0x08 */
 412         uint64_t                srr0;           /* 0x10 */
 413         uint64_t                srr1;           /* 0x18 */
 414         union {                                 /* 0x20 */
 415                 struct {
 416                         enum OpalMCE_UeErrorType ue_error_type:8;
 417                         uint8_t         effective_address_provided;
 418                         uint8_t         physical_address_provided;
 419                         uint8_t         reserved_1[5];
 420                         uint64_t        effective_address;
 421                         uint64_t        physical_address;
 422                         uint8_t         reserved_2[8];
 423                 } ue_error;
 424
 425                 struct {
 426                         enum OpalMCE_SlbErrorType slb_error_type:8;
 427                         uint8_t         effective_address_provided;
 428                         uint8_t         reserved_1[6];
 429                         uint64_t        effective_address;
 430                         uint8_t         reserved_2[16];
 431                 } slb_error;
 432
 433                 struct {
 434                         enum OpalMCE_EratErrorType erat_error_type:8;
 435                         uint8_t         effective_address_provided;
 436                         uint8_t         reserved_1[6];
 437                         uint64_t        effective_address;
 438                         uint8_t         reserved_2[16];
 439                 } erat_error;
 440
 441                 struct {
 442                         enum OpalMCE_TlbErrorType tlb_error_type:8;
 443                         uint8_t         effective_address_provided;
 444                         uint8_t         reserved_1[6];
 445                         uint64_t        effective_address;
 446                         uint8_t         reserved_2[16];
 447                 } tlb_error;
 448         } u;
 449 };
 450
 451 /* FSP memory errors handling */
 452 enum OpalMemErr_Version {
 453         OpalMemErr_V1 = 1,
 454 };
 455
 456 enum OpalMemErrType {
 457         OPAL_MEM_ERR_TYPE_RESILIENCE    = 0,
 458         OPAL_MEM_ERR_TYPE_DYN_DALLOC,
 459         OPAL_MEM_ERR_TYPE_SCRUB,
 460 };
 461
 462 /* Memory Reilience error type */
 463 enum OpalMemErr_ResilErrType {
 464         OPAL_MEM_RESILIENCE_CE          = 0,
 465         OPAL_MEM_RESILIENCE_UE,
 466         OPAL_MEM_RESILIENCE_UE_SCRUB,
 467 };
 468
 469 /* Dynamic Memory Deallocation type */
 470 enum OpalMemErr_DynErrType {
 471         OPAL_MEM_DYNAMIC_DEALLOC        = 0,
 472 };
 473
 474 /* OpalMemoryErrorData->flags */
 475 #define OPAL_MEM_CORRECTED_ERROR        0x0001
 476 #define OPAL_MEM_THRESHOLD_EXCEEDED     0x0002
 477 #define OPAL_MEM_ACK_REQUIRED           0x8000
 478
 479 struct OpalMemoryErrorData {
 480         enum OpalMemErr_Version version:8;      /* 0x00 */
 481         enum OpalMemErrType     type:8;         /* 0x01 */
 482         uint16_t                flags;          /* 0x02 */
 483         uint8_t                 reserved_1[4];  /* 0x04 */
 484
 485         union {
 486                 /* Memory Resilience corrected/uncorrected error info */
 487                 struct {
 488                         enum OpalMemErr_ResilErrType resil_err_type:8;
 489                         uint8_t         reserved_1[7];
 490                         uint64_t        physical_address_start;
 491                         uint64_t        physical_address_end;
 492                 } resilience;
 493                 /* Dynamic memory deallocation error info */
 494                 struct {
 495                         enum OpalMemErr_DynErrType dyn_err_type:8;
 496                         uint8_t         reserved_1[7];
 497                         uint64_t        physical_address_start;
 498                         uint64_t        physical_address_end;
 499                 } dyn_dealloc;
 500         } u;
 501 };
 502
 503 enum {
 504         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
 505         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
 506         OPAL_P7IOC_DIAG_TYPE_BI         = 2,
 507         OPAL_P7IOC_DIAG_TYPE_CI         = 3,
 508         OPAL_P7IOC_DIAG_TYPE_MISC       = 4,
 509         OPAL_P7IOC_DIAG_TYPE_I2C        = 5,
 510         OPAL_P7IOC_DIAG_TYPE_LAST       = 6
 511 };
 512
 513 struct OpalIoP7IOCErrorData {
 514         uint16_t type;
 515
 516         /* GEM */
 517         uint64_t gemXfir;
 518         uint64_t gemRfir;
 519         uint64_t gemRirqfir;
 520         uint64_t gemMask;
 521         uint64_t gemRwof;
 522
 523         /* LEM */
 524         uint64_t lemFir;
 525         uint64_t lemErrMask;
 526         uint64_t lemAction0;
 527         uint64_t lemAction1;
 528         uint64_t lemWof;
 529
 530         union {
 531                 struct OpalIoP7IOCRgcErrorData {
 532                         uint64_t rgcStatus;             /* 3E1C10 */
 533                         uint64_t rgcLdcp;               /* 3E1C18 */
 534                 }rgc;
 535                 struct OpalIoP7IOCBiErrorData {
 536                         uint64_t biLdcp0;               /* 3C0100, 3C0118 */
 537                         uint64_t biLdcp1;               /* 3C0108, 3C0120 */
 538                         uint64_t biLdcp2;               /* 3C0110, 3C0128 */
 539                         uint64_t biFenceStatus;         /* 3C0130, 3C0130 */
 540
 541                         uint8_t  biDownbound;           /* BI Downbound or Upbound */
 542                 }bi;
 543                 struct OpalIoP7IOCCiErrorData {
 544                         uint64_t ciPortStatus;          /* 3Dn008 */
 545                         uint64_t ciPortLdcp;            /* 3Dn010 */
 546
 547                         uint8_t  ciPort;                /* Index of CI port: 0/1 */
 548                 }ci;
 549         };
 550 };
 551
 552 /**
 553  * This structure defines the overlay which will be used to store PHB error
 554  * data upon request.
 555  */
 556 enum {
 557         OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
 558 };
 559
 560 enum {
 561         OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
 562         OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
 563 };
 564
 565 enum {
 566         OPAL_P7IOC_NUM_PEST_REGS = 128,
 567         OPAL_PHB3_NUM_PEST_REGS = 256
 568 };
 569
 570 struct OpalIoPhbErrorCommon {
 571         uint32_t version;
 572         uint32_t ioType;
 573         uint32_t len;
 574 };
 575
 576 struct OpalIoP7IOCPhbErrorData {
 577         struct OpalIoPhbErrorCommon common;
 578
 579         uint32_t brdgCtl;
 580
 581         // P7IOC utl regs
 582         uint32_t portStatusReg;
 583         uint32_t rootCmplxStatus;
 584         uint32_t busAgentStatus;
 585
 586         // P7IOC cfg regs
 587         uint32_t deviceStatus;
 588         uint32_t slotStatus;
 589         uint32_t linkStatus;
 590         uint32_t devCmdStatus;
 591         uint32_t devSecStatus;
 592
 593         // cfg AER regs
 594         uint32_t rootErrorStatus;
 595         uint32_t uncorrErrorStatus;
 596         uint32_t corrErrorStatus;
 597         uint32_t tlpHdr1;
 598         uint32_t tlpHdr2;
 599         uint32_t tlpHdr3;
 600         uint32_t tlpHdr4;
 601         uint32_t sourceId;
 602
 603         uint32_t rsv3;
 604
 605         // Record data about the call to allocate a buffer.
 606         uint64_t errorClass;
 607         uint64_t correlator;
 608
 609         //P7IOC MMIO Error Regs
 610         uint64_t p7iocPlssr;                // n120
 611         uint64_t p7iocCsr;                  // n110
 612         uint64_t lemFir;                    // nC00
 613         uint64_t lemErrorMask;              // nC18
 614         uint64_t lemWOF;                    // nC40
 615         uint64_t phbErrorStatus;            // nC80
 616         uint64_t phbFirstErrorStatus;       // nC88
 617         uint64_t phbErrorLog0;              // nCC0
 618         uint64_t phbErrorLog1;              // nCC8
 619         uint64_t mmioErrorStatus;           // nD00
 620         uint64_t mmioFirstErrorStatus;      // nD08
 621         uint64_t mmioErrorLog0;             // nD40
 622         uint64_t mmioErrorLog1;             // nD48
 623         uint64_t dma0ErrorStatus;           // nD80
 624         uint64_t dma0FirstErrorStatus;      // nD88
 625         uint64_t dma0ErrorLog0;             // nDC0
 626         uint64_t dma0ErrorLog1;             // nDC8
 627         uint64_t dma1ErrorStatus;           // nE00
 628         uint64_t dma1FirstErrorStatus;      // nE08
 629         uint64_t dma1ErrorLog0;             // nE40
 630         uint64_t dma1ErrorLog1;             // nE48
 631         uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
 632         uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
 633 };
 634
 635 struct OpalIoPhb3ErrorData {
 636         struct OpalIoPhbErrorCommon common;
 637
 638         uint32_t brdgCtl;
 639
 640         /* PHB3 UTL regs */
 641         uint32_t portStatusReg;
 642         uint32_t rootCmplxStatus;
 643         uint32_t busAgentStatus;
 644
 645         /* PHB3 cfg regs */
 646         uint32_t deviceStatus;
 647         uint32_t slotStatus;
 648         uint32_t linkStatus;
 649         uint32_t devCmdStatus;
 650         uint32_t devSecStatus;
 651
 652         /* cfg AER regs */
 653         uint32_t rootErrorStatus;
 654         uint32_t uncorrErrorStatus;
 655         uint32_t corrErrorStatus;
 656         uint32_t tlpHdr1;
 657         uint32_t tlpHdr2;
 658         uint32_t tlpHdr3;
 659         uint32_t tlpHdr4;
 660         uint32_t sourceId;
 661
 662         uint32_t rsv3;
 663
 664         /* Record data about the call to allocate a buffer */
 665         uint64_t errorClass;
 666         uint64_t correlator;
 667
 668         uint64_t nFir;                  /* 000 */
 669         uint64_t nFirMask;              /* 003 */
 670         uint64_t nFirWOF;               /* 008 */
 671
 672         /* PHB3 MMIO Error Regs */
 673         uint64_t phbPlssr;              /* 120 */
 674         uint64_t phbCsr;                /* 110 */
 675         uint64_t lemFir;                /* C00 */
 676         uint64_t lemErrorMask;          /* C18 */
 677         uint64_t lemWOF;                /* C40 */
 678         uint64_t phbErrorStatus;        /* C80 */
 679         uint64_t phbFirstErrorStatus;   /* C88 */
 680         uint64_t phbErrorLog0;          /* CC0 */
 681         uint64_t phbErrorLog1;          /* CC8 */
 682         uint64_t mmioErrorStatus;       /* D00 */
 683         uint64_t mmioFirstErrorStatus;  /* D08 */
 684         uint64_t mmioErrorLog0;         /* D40 */
 685         uint64_t mmioErrorLog1;         /* D48 */
 686         uint64_t dma0ErrorStatus;       /* D80 */
 687         uint64_t dma0FirstErrorStatus;  /* D88 */
 688         uint64_t dma0ErrorLog0;         /* DC0 */
 689         uint64_t dma0ErrorLog1;         /* DC8 */
 690         uint64_t dma1ErrorStatus;       /* E00 */
 691         uint64_t dma1FirstErrorStatus;  /* E08 */
 692         uint64_t dma1ErrorLog0;         /* E40 */
 693         uint64_t dma1ErrorLog1;         /* E48 */
 694         uint64_t pestA[OPAL_PHB3_NUM_PEST_REGS];
 695         uint64_t pestB[OPAL_PHB3_NUM_PEST_REGS];
 696 };
 697
 698 typedef struct oppanel_line {
 699         const char *    line;
 700         uint64_t        line_len;
 701 } oppanel_line_t;
 702
 703 /* /sys/firmware/opal */
 704 extern struct kobject *opal_kobj;
 705
 706 /* API functions */
 707 int64_t opal_console_write(int64_t term_number, __be64 *length,
 708                            const uint8_t *buffer);
 709 int64_t opal_console_read(int64_t term_number, __be64 *length,
 710                           uint8_t *buffer);
 711 int64_t opal_console_write_buffer_space(int64_t term_number,
 712                                         __be64 *length);
 713 int64_t opal_rtc_read(__be32 *year_month_day,
 714                       __be64 *hour_minute_second_millisecond);
 715 int64_t opal_rtc_write(uint32_t year_month_day,
 716                        uint64_t hour_minute_second_millisecond);
 717 int64_t opal_cec_power_down(uint64_t request);
 718 int64_t opal_cec_reboot(void);
 719 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 720 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 721 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
 722 int64_t opal_poll_events(__be64 *outstanding_event_mask);
 723 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
 724                                     uint64_t tce_mem_size);
 725 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
 726                                     uint64_t tce_mem_size);
 727 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
 728                                   uint64_t offset, uint8_t *data);
 729 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 730                                        uint64_t offset, __be16 *data);
 731 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
 732                                   uint64_t offset, __be32 *data);
 733 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
 734                                    uint64_t offset, uint8_t data);
 735 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 736                                         uint64_t offset, uint16_t data);
 737 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
 738                                    uint64_t offset, uint32_t data);
 739 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
 740 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
 741 int64_t opal_register_exception_handler(uint64_t opal_exception,
 742                                         uint64_t handler_address,
 743                                         uint64_t glue_cache_line);
 744 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
 745                                    uint8_t *freeze_state,
 746                                    __be16 *pci_error_type,
 747                                    __be64 *phb_status);
 748 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
 749                                   uint64_t eeh_action_token);
 750 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
 751
 752
 753
 754 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
 755                                  uint16_t window_num, uint16_t enable);
 756 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
 757                                     uint16_t window_num,
 758                                     uint64_t starting_real_address,
 759                                     uint64_t starting_pci_address,
 760                                     uint16_t segment_size);
 761 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
 762                                     uint16_t window_type, uint16_t window_num,
 763                                     uint16_t segment_num);
 764 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
 765                                       uint64_t ivt_addr, uint64_t ivt_len,
 766                                       uint64_t reject_array_addr,
 767                                       uint64_t peltv_addr);
 768 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
 769                         uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
 770                         uint8_t pe_action);
 771 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
 772                            uint8_t state);
 773 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
 774 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
 775                                 uint32_t state);
 776 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 777                                   uint8_t *p_bit, uint8_t *q_bit);
 778 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 779                                   uint8_t p_bit, uint8_t q_bit);
 780 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
 781 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
 782                              uint32_t xive_num);
 783 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
 784                              __be32 *interrupt_source_number);
 785 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
 786                         uint8_t msi_range, __be32 *msi_address,
 787                         __be32 *message_data);
 788 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
 789                         uint32_t xive_num, uint8_t msi_range,
 790                         __be64 *msi_address, __be32 *message_data);
 791 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
 792 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
 793 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
 794 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
 795                                    uint16_t tce_levels, uint64_t tce_table_addr,
 796                                    uint64_t tce_table_size, uint64_t tce_page_size);
 797 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
 798                                         uint16_t dma_window_number, uint64_t pci_start_addr,
 799                                         uint64_t pci_mem_size);
 800 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
 801
 802 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
 803                                    uint64_t diag_buffer_len);
 804 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
 805                                    uint64_t diag_buffer_len);
 806 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
 807                                     uint64_t diag_buffer_len);
 808 int64_t opal_pci_fence_phb(uint64_t phb_id);
 809 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
 810 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
 811 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
 812 int64_t opal_get_epow_status(__be64 *status);
 813 int64_t opal_set_system_attention_led(uint8_t led_action);
 814 int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
 815                             uint16_t *pci_error_type, uint16_t *severity);
 816 int64_t opal_pci_poll(uint64_t phb_id);
 817 int64_t opal_return_cpu(void);
 818
 819 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
 820 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
 821
 822 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 823                        uint32_t addr, uint32_t data, uint32_t sz);
 824 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 825                       uint32_t addr, __be32 *data, uint32_t sz);
 826 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
 827 int64_t opal_manage_flash(uint8_t op);
 828 int64_t opal_update_flash(uint64_t blk_list);
 829
 830 int64_t opal_get_msg(uint64_t buffer, size_t size);
 831 int64_t opal_check_completion(uint64_t buffer, size_t size, uint64_t token);
 832 int64_t opal_sync_host_reboot(void);
 833
 834 /* Internal functions */
 835 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
 836
 837 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 838 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
 839
 840 extern void hvc_opal_init_early(void);
 841
 842 /* Internal functions */
 843 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
 844                                    int depth, void *data);
 845
 846 extern int opal_notifier_register(struct notifier_block *nb);
 847 extern int opal_message_notifier_register(enum OpalMessageType msg_type,
 848                                                 struct notifier_block *nb);
 849 extern void opal_notifier_enable(void);
 850 extern void opal_notifier_disable(void);
 851 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
 852
 853 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 854 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
 855
 856 extern void hvc_opal_init_early(void);
 857
 858 struct rtc_time;
 859 extern int opal_set_rtc_time(struct rtc_time *tm);
 860 extern void opal_get_rtc_time(struct rtc_time *tm);
 861 extern unsigned long opal_get_boot_time(void);
 862 extern void opal_nvram_init(void);
 863 extern void opal_flash_init(void);
 864
 865 extern int opal_machine_check(struct pt_regs *regs);
 866
 867 extern void opal_shutdown(void);
 868
 869 extern void opal_lpc_init(void);
 870
 871 #endif /* __ASSEMBLY__ */
 872
 873 #endif /* __OPAL_H */