1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_H
3 #define _ASM_POWERPC_NOHASH_64_PGTABLE_H
5 * This file contains the functions and defines necessary to modify and use
6 * the ppc64 hashed page table.
9 #ifdef CONFIG_PPC_64K_PAGES
10 #include <asm/nohash/64/pgtable-64k.h>
12 #include <asm/nohash/64/pgtable-4k.h>
14 #include <asm/barrier.h>
16 #define FIRST_USER_ADDRESS 0UL
19 * Size of EA range mapped by our pagetables.
21 #define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
22 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
23 #define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
25 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
26 #define PMD_CACHE_INDEX (PMD_INDEX_SIZE + 1)
28 #define PMD_CACHE_INDEX PMD_INDEX_SIZE
30 #define PUD_CACHE_INDEX PUD_INDEX_SIZE
33 * Define the address range of the kernel non-linear virtual area
35 #define KERN_VIRT_START ASM_CONST(0x8000000000000000)
36 #define KERN_VIRT_SIZE ASM_CONST(0x0000100000000000)
39 * The vmalloc space starts at the beginning of that region, and
40 * occupies half of it on hash CPUs and a quarter of it on Book3E
41 * (we keep a quarter for the virtual memmap)
43 #define VMALLOC_START KERN_VIRT_START
44 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 2)
45 #define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
48 * The second half of the kernel virtual space is used for IO mappings,
49 * it's itself carved into the PIO region (ISA and PHB IO space) and
52 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
53 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
54 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
56 #define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
57 #define FULL_IO_SIZE 0x80000000ul
58 #define ISA_IO_BASE (KERN_IO_START)
59 #define ISA_IO_END (KERN_IO_START + 0x10000ul)
60 #define PHB_IO_BASE (ISA_IO_END)
61 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
62 #define IOREMAP_BASE (PHB_IO_END)
63 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
69 #define REGION_SHIFT 60UL
70 #define REGION_MASK (0xfUL << REGION_SHIFT)
71 #define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT)
73 #define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START))
74 #define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET))
75 #define VMEMMAP_REGION_ID (0xfUL) /* Server only */
76 #define USER_REGION_ID (0UL)
79 * Defines the address of the vmemap area, in its own region on
80 * hash table CPUs and after the vmalloc space on Book3E
82 #define VMEMMAP_BASE VMALLOC_END
83 #define VMEMMAP_END KERN_IO_START
84 #define vmemmap ((struct page *)VMEMMAP_BASE)
88 * Include the PTE bits definitions
90 #include <asm/nohash/pte-book3e.h>
91 #include <asm/pte-common.h>
94 /* pte_clear moved to later in this file */
96 #define PMD_BAD_BITS (PTE_TABLE_SIZE-1)
97 #define PUD_BAD_BITS (PMD_TABLE_SIZE-1)
99 static inline void pmd_set(pmd_t *pmdp, unsigned long val)
104 static inline void pmd_clear(pmd_t *pmdp)
109 static inline pte_t pmd_pte(pmd_t pmd)
111 return __pte(pmd_val(pmd));
114 #define pmd_none(pmd) (!pmd_val(pmd))
115 #define pmd_bad(pmd) (!is_kernel_addr(pmd_val(pmd)) \
116 || (pmd_val(pmd) & PMD_BAD_BITS))
117 #define pmd_present(pmd) (!pmd_none(pmd))
118 #define pmd_page_vaddr(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS)
119 extern struct page *pmd_page(pmd_t pmd);
121 static inline void pud_set(pud_t *pudp, unsigned long val)
126 static inline void pud_clear(pud_t *pudp)
131 #define pud_none(pud) (!pud_val(pud))
132 #define pud_bad(pud) (!is_kernel_addr(pud_val(pud)) \
133 || (pud_val(pud) & PUD_BAD_BITS))
134 #define pud_present(pud) (pud_val(pud) != 0)
135 #define pud_page_vaddr(pud) (pud_val(pud) & ~PUD_MASKED_BITS)
137 extern struct page *pud_page(pud_t pud);
139 static inline pte_t pud_pte(pud_t pud)
141 return __pte(pud_val(pud));
144 static inline pud_t pte_pud(pte_t pte)
146 return __pud(pte_val(pte));
148 #define pud_write(pud) pte_write(pud_pte(pud))
149 #define pgd_write(pgd) pte_write(pgd_pte(pgd))
151 static inline void pgd_set(pgd_t *pgdp, unsigned long val)
157 * Find an entry in a page-table-directory. We combine the address region
158 * (the high order N bits) and the pgd portion of the address.
160 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
162 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
164 #define pmd_offset(pudp,addr) \
165 (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
167 #define pte_offset_kernel(dir,addr) \
168 (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
170 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
171 #define pte_unmap(pte) do { } while(0)
173 /* to find an entry in a kernel page-table-directory */
174 /* This now only contains the vmalloc pages */
175 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
176 extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
177 pte_t *ptep, unsigned long pte, int huge);
179 /* Atomic PTE updates */
180 static inline unsigned long pte_update(struct mm_struct *mm,
182 pte_t *ptep, unsigned long clr,
186 #ifdef PTE_ATOMIC_UPDATES
187 unsigned long old, tmp;
189 __asm__ __volatile__(
190 "1: ldarx %0,0,%3 # pte_update\n\
197 : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
198 : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY), "r" (set)
201 unsigned long old = pte_val(*ptep);
202 *ptep = __pte((old & ~clr) | set);
204 /* huge pages use the old page table lock */
206 assert_pte_locked(mm, addr);
208 #ifdef CONFIG_PPC_BOOK3S_64
209 if (old & _PAGE_HASHPTE)
210 hpte_need_flush(mm, addr, ptep, old, huge);
216 static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
217 unsigned long addr, pte_t *ptep)
221 if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
223 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
224 return (old & _PAGE_ACCESSED) != 0;
226 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
227 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
230 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
234 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
235 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
239 if ((pte_val(*ptep) & _PAGE_RW) == 0)
242 pte_update(mm, addr, ptep, _PAGE_RW, 0, 0);
245 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
246 unsigned long addr, pte_t *ptep)
248 if ((pte_val(*ptep) & _PAGE_RW) == 0)
251 pte_update(mm, addr, ptep, _PAGE_RW, 0, 1);
255 * We currently remove entries from the hashtable regardless of whether
256 * the entry was young or dirty. The generic routines only flush if the
257 * entry was young or dirty which is not good enough.
259 * We should be more intelligent about this but for the moment we override
260 * these functions and force a tlb flush unconditionally
262 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
263 #define ptep_clear_flush_young(__vma, __address, __ptep) \
265 int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
270 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
271 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
272 unsigned long addr, pte_t *ptep)
274 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
278 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
281 pte_update(mm, addr, ptep, ~0UL, 0, 0);
285 /* Set the dirty and/or accessed bits atomically in a linux PTE, this
286 * function doesn't need to flush the hash entry
288 static inline void __ptep_set_access_flags(struct mm_struct *mm,
289 pte_t *ptep, pte_t entry,
290 unsigned long address)
292 unsigned long bits = pte_val(entry) &
293 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
295 #ifdef PTE_ATOMIC_UPDATES
296 unsigned long old, tmp;
298 __asm__ __volatile__(
305 :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
306 :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
309 unsigned long old = pte_val(*ptep);
310 *ptep = __pte(old | bits);
314 #define __HAVE_ARCH_PTE_SAME
315 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
317 #define pte_ERROR(e) \
318 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
319 #define pmd_ERROR(e) \
320 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
321 #define pgd_ERROR(e) \
322 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
324 /* Encode and de-code a swap entry */
325 #define MAX_SWAPFILES_CHECK() do { \
326 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
328 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
329 * We filter HPTEFLAGS on set_pte. \
331 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
334 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
336 #define SWP_TYPE_BITS 5
337 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
338 & ((1UL << SWP_TYPE_BITS) - 1))
339 #define __swp_offset(x) ((x).val >> PTE_RPN_SHIFT)
340 #define __swp_entry(type, offset) ((swp_entry_t) { \
341 ((type) << _PAGE_BIT_SWAP_TYPE) \
342 | ((offset) << PTE_RPN_SHIFT) })
344 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) })
345 #define __swp_entry_to_pte(x) __pte((x).val)
347 extern int map_kernel_page(unsigned long ea, unsigned long pa,
348 unsigned long flags);
349 extern int __meminit vmemmap_create_mapping(unsigned long start,
350 unsigned long page_size,
352 extern void vmemmap_remove_mapping(unsigned long start,
353 unsigned long page_size);
354 #endif /* __ASSEMBLY__ */
356 #endif /* _ASM_POWERPC_NOHASH_64_PGTABLE_H */