4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
8 * Modifications for the OpenRISC architecture:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
18 #include <linux/linkage.h>
19 #include <linux/threads.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/serial_reg.h>
23 #include <asm/processor.h>
26 #include <asm/pgtable.h>
27 #include <asm/thread_info.h>
28 #include <asm/cache.h>
29 #include <asm/spr_defs.h>
30 #include <asm/asm-offsets.h>
31 #include <linux/of_fdt.h>
33 #define tophys(rd,rs) \
34 l.movhi rd,hi(-KERNELBASE) ;\
37 #define CLEAR_GPR(gpr) \
40 #define LOAD_SYMBOL_2_GPR(gpr,symbol) \
41 l.movhi gpr,hi(symbol) ;\
42 l.ori gpr,gpr,lo(symbol)
45 #define UART_BASE_ADD 0x90000000
47 #define EXCEPTION_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_SM)
48 #define SYSCALL_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_IEE | SPR_SR_TEE | SPR_SR_SM)
50 /* ============================================[ tmp store locations ]=== */
52 #define SPR_SHADOW_GPR(x) ((x) + SPR_GPR_BASE + 32)
55 * emergency_print temporary stores
57 #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
58 #define EMERGENCY_PRINT_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(14)
59 #define EMERGENCY_PRINT_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(14)
61 #define EMERGENCY_PRINT_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(15)
62 #define EMERGENCY_PRINT_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(15)
64 #define EMERGENCY_PRINT_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(16)
65 #define EMERGENCY_PRINT_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(16)
67 #define EMERGENCY_PRINT_STORE_GPR7 l.mtspr r0,r7,SPR_SHADOW_GPR(7)
68 #define EMERGENCY_PRINT_LOAD_GPR7 l.mfspr r7,r0,SPR_SHADOW_GPR(7)
70 #define EMERGENCY_PRINT_STORE_GPR8 l.mtspr r0,r8,SPR_SHADOW_GPR(8)
71 #define EMERGENCY_PRINT_LOAD_GPR8 l.mfspr r8,r0,SPR_SHADOW_GPR(8)
73 #define EMERGENCY_PRINT_STORE_GPR9 l.mtspr r0,r9,SPR_SHADOW_GPR(9)
74 #define EMERGENCY_PRINT_LOAD_GPR9 l.mfspr r9,r0,SPR_SHADOW_GPR(9)
76 #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
77 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
78 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
80 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
81 #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
83 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
84 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
86 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
87 #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
89 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
90 #define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0)
92 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
93 #define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
98 * TLB miss handlers temorary stores
100 #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
101 #define EXCEPTION_STORE_GPR2 l.mtspr r0,r2,SPR_SHADOW_GPR(2)
102 #define EXCEPTION_LOAD_GPR2 l.mfspr r2,r0,SPR_SHADOW_GPR(2)
104 #define EXCEPTION_STORE_GPR3 l.mtspr r0,r3,SPR_SHADOW_GPR(3)
105 #define EXCEPTION_LOAD_GPR3 l.mfspr r3,r0,SPR_SHADOW_GPR(3)
107 #define EXCEPTION_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(4)
108 #define EXCEPTION_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(4)
110 #define EXCEPTION_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(5)
111 #define EXCEPTION_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(5)
113 #define EXCEPTION_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(6)
114 #define EXCEPTION_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(6)
116 #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
117 #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
118 #define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
120 #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
121 #define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
123 #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
124 #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
126 #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
127 #define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0)
129 #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
130 #define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
135 * EXCEPTION_HANDLE temporary stores
138 #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
139 #define EXCEPTION_T_STORE_GPR30 l.mtspr r0,r30,SPR_SHADOW_GPR(30)
140 #define EXCEPTION_T_LOAD_GPR30(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(30)
142 #define EXCEPTION_T_STORE_GPR10 l.mtspr r0,r10,SPR_SHADOW_GPR(10)
143 #define EXCEPTION_T_LOAD_GPR10(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(10)
145 #define EXCEPTION_T_STORE_SP l.mtspr r0,r1,SPR_SHADOW_GPR(1)
146 #define EXCEPTION_T_LOAD_SP(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(1)
148 #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
149 #define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
150 #define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
152 #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
153 #define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
155 #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
156 #define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
159 /* =========================================================[ macros ]=== */
162 #define GET_CURRENT_PGD(reg,t1) \
163 LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\
164 l.mfspr t1,r0,SPR_COREID ;\
170 #define GET_CURRENT_PGD(reg,t1) \
171 LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\
176 /* Load r10 from current_thread_info_set - clobbers r1 and r30 */
178 #define GET_CURRENT_THREAD_INFO \
179 LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\
181 l.mfspr r10,r0,SPR_COREID ;\
184 /* r10: current_thread_info */ ;\
187 #define GET_CURRENT_THREAD_INFO \
188 LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\
190 /* r10: current_thread_info */ ;\
195 * DSCR: this is a common hook for handling exceptions. it will save
196 * the needed registers, set up stack and pointer to current
197 * then jump to the handler while enabling MMU
199 * PRMS: handler - a function to jump to. it has to save the
200 * remaining registers to kernel stack, call
201 * appropriate arch-independant exception handler
202 * and finaly jump to ret_from_except
204 * PREQ: unchanged state from the time exception happened
206 * POST: SAVED the following registers original value
207 * to the new created exception frame pointed to by r1
209 * r1 - ksp pointing to the new (exception) frame
210 * r4 - EEAR exception EA
211 * r10 - current pointing to current_thread_info struct
212 * r12 - syscall 0, since we didn't come from syscall
213 * r30 - handler address of the handler we'll jump to
215 * handler has to save remaining registers to the exception
216 * ksp frame *before* tainting them!
218 * NOTE: this function is not reentrant per se. reentrancy is guaranteed
219 * by processor disabling all exceptions/interrupts when exception
222 * OPTM: no need to make it so wasteful to extract ksp when in user mode
225 #define EXCEPTION_HANDLE(handler) \
226 EXCEPTION_T_STORE_GPR30 ;\
227 l.mfspr r30,r0,SPR_ESR_BASE ;\
228 l.andi r30,r30,SPR_SR_SM ;\
230 EXCEPTION_T_STORE_GPR10 ;\
231 l.bnf 2f /* kernel_mode */ ;\
232 EXCEPTION_T_STORE_SP /* delay slot */ ;\
233 1: /* user_mode: */ ;\
234 GET_CURRENT_THREAD_INFO ;\
236 l.lwz r1,(TI_KSP)(r30) ;\
237 /* fall through */ ;\
238 2: /* kernel_mode: */ ;\
239 /* create new stack frame, save only needed gprs */ ;\
240 /* r1: KSP, r10: current, r4: EEAR, r31: __pa(KSP) */ ;\
241 /* r12: temp, syscall indicator */ ;\
242 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
243 /* r1 is KSP, r30 is __pa(KSP) */ ;\
245 l.sw PT_GPR12(r30),r12 ;\
246 /* r4 use for tmp before EA */ ;\
247 l.mfspr r12,r0,SPR_EPCR_BASE ;\
248 l.sw PT_PC(r30),r12 ;\
249 l.mfspr r12,r0,SPR_ESR_BASE ;\
250 l.sw PT_SR(r30),r12 ;\
252 EXCEPTION_T_LOAD_GPR30(r12) ;\
253 l.sw PT_GPR30(r30),r12 ;\
254 /* save r10 as was prior to exception */ ;\
255 EXCEPTION_T_LOAD_GPR10(r12) ;\
256 l.sw PT_GPR10(r30),r12 ;\
257 /* save PT_SP as was prior to exception */ ;\
258 EXCEPTION_T_LOAD_SP(r12) ;\
259 l.sw PT_SP(r30),r12 ;\
260 /* save exception r4, set r4 = EA */ ;\
261 l.sw PT_GPR4(r30),r4 ;\
262 l.mfspr r4,r0,SPR_EEAR_BASE ;\
263 /* r12 == 1 if we come from syscall */ ;\
265 /* ----- turn on MMU ----- */ ;\
266 /* Carry DSX into exception SR */ ;\
267 l.mfspr r30,r0,SPR_SR ;\
268 l.andi r30,r30,SPR_SR_DSX ;\
269 l.ori r30,r30,(EXCEPTION_SR) ;\
270 l.mtspr r0,r30,SPR_ESR_BASE ;\
271 /* r30: EA address of handler */ ;\
272 LOAD_SYMBOL_2_GPR(r30,handler) ;\
273 l.mtspr r0,r30,SPR_EPCR_BASE ;\
280 * #ifdef CONFIG_JUMP_UPON_UNHANDLED_EXCEPTION
281 * #define UNHANDLED_EXCEPTION(handler) \
283 * l.mtspr r0,r3,SPR_SR ;\
284 * l.movhi r3,hi(0xf0000100) ;\
285 * l.ori r3,r3,lo(0xf0000100) ;\
292 /* DSCR: this is the same as EXCEPTION_HANDLE(), we are just
293 * a bit more carefull (if we have a PT_SP or current pointer
294 * corruption) and set them up from 'current_set'
297 #define UNHANDLED_EXCEPTION(handler) \
298 EXCEPTION_T_STORE_GPR30 ;\
299 EXCEPTION_T_STORE_GPR10 ;\
300 EXCEPTION_T_STORE_SP ;\
301 /* temporary store r3, r9 into r1, r10 */ ;\
304 /* the string referenced by r3 must be low enough */ ;\
305 l.jal _emergency_print ;\
306 l.ori r3,r0,lo(_string_unhandled_exception) ;\
307 l.mfspr r3,r0,SPR_NPC ;\
308 l.jal _emergency_print_nr ;\
309 l.andi r3,r3,0x1f00 ;\
310 /* the string referenced by r3 must be low enough */ ;\
311 l.jal _emergency_print ;\
312 l.ori r3,r0,lo(_string_epc_prefix) ;\
313 l.jal _emergency_print_nr ;\
314 l.mfspr r3,r0,SPR_EPCR_BASE ;\
315 l.jal _emergency_print ;\
316 l.ori r3,r0,lo(_string_nl) ;\
317 /* end of printing */ ;\
320 /* extract current, ksp from current_set */ ;\
321 LOAD_SYMBOL_2_GPR(r1,_unhandled_stack_top) ;\
322 LOAD_SYMBOL_2_GPR(r10,init_thread_union) ;\
323 /* create new stack frame, save only needed gprs */ ;\
324 /* r1: KSP, r10: current, r31: __pa(KSP) */ ;\
325 /* r12: temp, syscall indicator, r13 temp */ ;\
326 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
327 /* r1 is KSP, r30 is __pa(KSP) */ ;\
329 l.sw PT_GPR12(r30),r12 ;\
330 l.mfspr r12,r0,SPR_EPCR_BASE ;\
331 l.sw PT_PC(r30),r12 ;\
332 l.mfspr r12,r0,SPR_ESR_BASE ;\
333 l.sw PT_SR(r30),r12 ;\
335 EXCEPTION_T_LOAD_GPR30(r12) ;\
336 l.sw PT_GPR30(r30),r12 ;\
337 /* save r10 as was prior to exception */ ;\
338 EXCEPTION_T_LOAD_GPR10(r12) ;\
339 l.sw PT_GPR10(r30),r12 ;\
340 /* save PT_SP as was prior to exception */ ;\
341 EXCEPTION_T_LOAD_SP(r12) ;\
342 l.sw PT_SP(r30),r12 ;\
343 l.sw PT_GPR13(r30),r13 ;\
345 /* save exception r4, set r4 = EA */ ;\
346 l.sw PT_GPR4(r30),r4 ;\
347 l.mfspr r4,r0,SPR_EEAR_BASE ;\
348 /* r12 == 1 if we come from syscall */ ;\
350 /* ----- play a MMU trick ----- */ ;\
351 l.ori r30,r0,(EXCEPTION_SR) ;\
352 l.mtspr r0,r30,SPR_ESR_BASE ;\
353 /* r31: EA address of handler */ ;\
354 LOAD_SYMBOL_2_GPR(r30,handler) ;\
355 l.mtspr r0,r30,SPR_EPCR_BASE ;\
358 /* =====================================================[ exceptions] === */
360 /* ---[ 0x100: RESET exception ]----------------------------------------- */
362 /* Jump to .init code at _start which lives in the .head section
363 * and will be discarded after boot.
365 LOAD_SYMBOL_2_GPR(r15, _start)
366 tophys (r13,r15) /* MMU disabled */
370 /* ---[ 0x200: BUS exception ]------------------------------------------- */
373 EXCEPTION_HANDLE(_bus_fault_handler)
375 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
377 _dispatch_do_dpage_fault:
378 // totaly disable timer interrupt
379 // l.mtspr r0,r0,SPR_TTMR
380 // DEBUG_TLB_PROBE(0x300)
381 // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x300)
382 EXCEPTION_HANDLE(_data_page_fault_handler)
384 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
386 _dispatch_do_ipage_fault:
387 // totaly disable timer interrupt
388 // l.mtspr r0,r0,SPR_TTMR
389 // DEBUG_TLB_PROBE(0x400)
390 // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x400)
391 EXCEPTION_HANDLE(_insn_page_fault_handler)
393 /* ---[ 0x500: Timer exception ]----------------------------------------- */
395 EXCEPTION_HANDLE(_timer_handler)
397 /* ---[ 0x600: Alignment exception ]-------------------------------------- */
399 EXCEPTION_HANDLE(_alignment_handler)
401 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
403 EXCEPTION_HANDLE(_illegal_instruction_handler)
405 /* ---[ 0x800: External interrupt exception ]---------------------------- */
407 EXCEPTION_HANDLE(_external_irq_handler)
409 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
411 l.j boot_dtlb_miss_handler
414 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
416 l.j boot_itlb_miss_handler
419 /* ---[ 0xb00: Range exception ]----------------------------------------- */
421 UNHANDLED_EXCEPTION(_vector_0xb00)
423 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
425 EXCEPTION_HANDLE(_sys_call_handler)
427 /* ---[ 0xd00: Trap exception ]------------------------------------------ */
429 UNHANDLED_EXCEPTION(_vector_0xd00)
431 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
433 // UNHANDLED_EXCEPTION(_vector_0xe00)
434 EXCEPTION_HANDLE(_trap_handler)
436 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
438 UNHANDLED_EXCEPTION(_vector_0xf00)
440 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
442 UNHANDLED_EXCEPTION(_vector_0x1000)
444 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
446 UNHANDLED_EXCEPTION(_vector_0x1100)
448 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
450 UNHANDLED_EXCEPTION(_vector_0x1200)
452 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
454 UNHANDLED_EXCEPTION(_vector_0x1300)
456 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
458 UNHANDLED_EXCEPTION(_vector_0x1400)
460 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
462 UNHANDLED_EXCEPTION(_vector_0x1500)
464 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
466 UNHANDLED_EXCEPTION(_vector_0x1600)
468 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
470 UNHANDLED_EXCEPTION(_vector_0x1700)
472 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
474 UNHANDLED_EXCEPTION(_vector_0x1800)
476 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
478 UNHANDLED_EXCEPTION(_vector_0x1900)
480 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
482 UNHANDLED_EXCEPTION(_vector_0x1a00)
484 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
486 UNHANDLED_EXCEPTION(_vector_0x1b00)
488 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
490 UNHANDLED_EXCEPTION(_vector_0x1c00)
492 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
494 UNHANDLED_EXCEPTION(_vector_0x1d00)
496 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
498 UNHANDLED_EXCEPTION(_vector_0x1e00)
500 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
502 UNHANDLED_EXCEPTION(_vector_0x1f00)
505 /* ===================================================[ kernel start ]=== */
509 /* This early stuff belongs in HEAD, but some of the functions below definitely
515 /* Init r0 to zero as per spec */
518 /* save kernel parameters */
519 l.or r25,r0,r3 /* pointer to fdt */
522 * ensure a deterministic start
560 l.mfspr r26,r0,SPR_COREID
566 * set up initial ksp and current
568 /* setup kernel stack */
569 LOAD_SYMBOL_2_GPR(r1,init_thread_union + THREAD_SIZE)
570 LOAD_SYMBOL_2_GPR(r10,init_thread_union) // setup current
578 * .data contains initialized data,
579 * .bss contains uninitialized data - clear it up
582 LOAD_SYMBOL_2_GPR(r24, __bss_start)
583 LOAD_SYMBOL_2_GPR(r26, _end)
606 /* The MMU needs to be enabled before or32_early_setup is called */
611 * SR[5] = 0, SR[6] = 0, 6th and 7th bit of SR set to 0
613 l.mfspr r30,r0,SPR_SR
614 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
615 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
617 l.mtspr r0,r30,SPR_SR
635 // reset the simulation counters
638 /* check fdt header magic word */
639 l.lwz r3,0(r25) /* load magic from fdt into r3 */
640 l.movhi r4,hi(OF_DT_HEADER)
641 l.ori r4,r4,lo(OF_DT_HEADER)
645 /* magic number mismatch, set fdt pointer to null */
648 /* pass fdt pointer to or32_early_setup in r3 */
650 LOAD_SYMBOL_2_GPR(r24, or32_early_setup)
656 * clear all GPRS to increase determinism
690 * jump to kernel entry (start_kernel)
692 LOAD_SYMBOL_2_GPR(r30, start_kernel)
698 * I N V A L I D A T E T L B e n t r i e s
700 LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
701 LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
702 l.addi r7,r0,128 /* Maximum number of sets */
718 /* Doze the cpu until we are asked to run */
719 /* If we dont have power management skip doze */
720 l.mfspr r25,r0,SPR_UPR
721 l.andi r25,r25,SPR_UPR_PMP
723 l.bf secondary_check_release
726 /* Setup special secondary exception handler */
727 LOAD_SYMBOL_2_GPR(r3, _secondary_evbar)
729 l.mtspr r0,r25,SPR_EVBAR
731 /* Enable Interrupts */
732 l.mfspr r25,r0,SPR_SR
733 l.ori r25,r25,SPR_SR_IEE
734 l.mtspr r0,r25,SPR_SR
736 /* Unmask interrupts interrupts */
737 l.mfspr r25,r0,SPR_PICMR
739 l.mtspr r0,r25,SPR_PICMR
742 l.mfspr r25,r0,SPR_PMR
743 LOAD_SYMBOL_2_GPR(r3, SPR_PMR_DME)
745 l.mtspr r0,r25,SPR_PMR
747 /* Wakeup - Restore exception handler */
748 l.mtspr r0,r0,SPR_EVBAR
750 secondary_check_release:
752 * Check if we actually got the release signal, if not go-back to
755 l.mfspr r25,r0,SPR_COREID
756 LOAD_SYMBOL_2_GPR(r3, secondary_release)
762 /* fall through to secondary_init */
766 * set up initial ksp and current
768 LOAD_SYMBOL_2_GPR(r10, secondary_thread_info)
771 l.addi r1,r10,THREAD_SIZE
787 l.mfspr r30,r0,SPR_SR
788 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
789 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
792 * This is a bit tricky, we need to switch over from physical addresses
793 * to virtual addresses on the fly.
794 * To do that, we first set up ESR with the IME and DME bits set.
795 * Then EPCR is set to secondary_start and then a l.rfe is issued to
798 l.mtspr r0,r30,SPR_ESR_BASE
799 LOAD_SYMBOL_2_GPR(r30, secondary_start)
800 l.mtspr r0,r30,SPR_EPCR_BASE
804 LOAD_SYMBOL_2_GPR(r30, secondary_start_kernel)
810 /* ========================================[ cache ]=== */
812 /* alignment here so we don't change memory offsets with
813 * memory controller defined
818 /* Check if IC present and skip enabling otherwise */
819 l.mfspr r24,r0,SPR_UPR
820 l.andi r26,r24,SPR_UPR_ICP
828 l.xori r5,r5,SPR_SR_ICE
832 /* Establish cache block size
835 r14 contain block size
837 l.mfspr r24,r0,SPR_ICCFGR
838 l.andi r26,r24,SPR_ICCFGR_CBS
843 /* Establish number of cache sets
844 r16 contains number of cache sets
845 r28 contains log(# of cache sets)
847 l.andi r26,r24,SPR_ICCFGR_NCS
857 // l.addi r5,r0,IC_SIZE
859 l.mtspr r0,r6,SPR_ICBIR
863 // l.addi r6,r6,IC_LINE
867 l.ori r6,r6,SPR_SR_ICE
884 /* Check if DC present and skip enabling otherwise */
885 l.mfspr r24,r0,SPR_UPR
886 l.andi r26,r24,SPR_UPR_DCP
894 l.xori r5,r5,SPR_SR_DCE
898 /* Establish cache block size
901 r14 contain block size
903 l.mfspr r24,r0,SPR_DCCFGR
904 l.andi r26,r24,SPR_DCCFGR_CBS
909 /* Establish number of cache sets
910 r16 contains number of cache sets
911 r28 contains log(# of cache sets)
913 l.andi r26,r24,SPR_DCCFGR_NCS
922 l.mtspr r0,r6,SPR_DCBIR
929 l.ori r6,r6,SPR_SR_DCE
935 /* ===============================================[ page table masks ]=== */
937 #define DTLB_UP_CONVERT_MASK 0x3fa
938 #define ITLB_UP_CONVERT_MASK 0x3a
940 /* for SMP we'd have (this is a bit subtle, CC must be always set
941 * for SMP, but since we have _PAGE_PRESENT bit always defined
942 * we can just modify the mask)
944 #define DTLB_SMP_CONVERT_MASK 0x3fb
945 #define ITLB_SMP_CONVERT_MASK 0x3b
947 /* ---[ boot dtlb miss handler ]----------------------------------------- */
949 boot_dtlb_miss_handler:
951 /* mask for DTLB_MR register: - (0) sets V (valid) bit,
952 * - (31-12) sets bits belonging to VPN (31-12)
954 #define DTLB_MR_MASK 0xfffff001
956 /* mask for DTLB_TR register: - (2) sets CI (cache inhibit) bit,
957 * - (4) sets A (access) bit,
958 * - (5) sets D (dirty) bit,
959 * - (8) sets SRE (superuser read) bit
960 * - (9) sets SWE (superuser write) bit
961 * - (31-12) sets bits belonging to VPN (31-12)
963 #define DTLB_TR_MASK 0xfffff332
965 /* These are for masking out the VPN/PPN value from the MR/TR registers...
966 * it's not the same as the PFN */
967 #define VPN_MASK 0xfffff000
968 #define PPN_MASK 0xfffff000
974 l.mfspr r6,r0,SPR_ESR_BASE //
975 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
976 l.sfeqi r6,0 // r6 == 0x1 --> SM
977 l.bf exit_with_no_dtranslation //
981 /* this could be optimized by moving storing of
982 * non r6 registers here, and jumping r6 restore
983 * if not in supervisor mode
991 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
993 immediate_translation:
996 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
998 l.mfspr r6, r0, SPR_DMMUCFGR
999 l.andi r6, r6, SPR_DMMUCFGR_NTS
1000 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
1002 l.sll r5, r5, r6 // r5 = number DMMU sets
1003 l.addi r6, r5, -1 // r6 = nsets mask
1004 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1006 l.or r6,r6,r4 // r6 <- r4
1007 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1008 l.movhi r5,hi(DTLB_MR_MASK) // r5 <- ffff:0000.x000
1009 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
1010 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry
1011 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR
1013 /* set up DTLB with no translation for EA <= 0xbfffffff */
1014 LOAD_SYMBOL_2_GPR(r6,0xbfffffff)
1015 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
1017 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1019 tophys(r3,r4) // r3 <- PA
1021 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1022 l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000
1023 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
1024 l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry
1025 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
1033 l.rfe // SR <- ESR, PC <- EPC
1035 exit_with_no_dtranslation:
1036 /* EA out of memory or not in supervisor mode */
1039 l.j _dispatch_bus_fault
1041 /* ---[ boot itlb miss handler ]----------------------------------------- */
1043 boot_itlb_miss_handler:
1045 /* mask for ITLB_MR register: - sets V (valid) bit,
1046 * - sets bits belonging to VPN (15-12)
1048 #define ITLB_MR_MASK 0xfffff001
1050 /* mask for ITLB_TR register: - sets A (access) bit,
1051 * - sets SXE (superuser execute) bit
1052 * - sets bits belonging to VPN (15-12)
1054 #define ITLB_TR_MASK 0xfffff050
1057 #define VPN_MASK 0xffffe000
1058 #define PPN_MASK 0xffffe000
1063 EXCEPTION_STORE_GPR2
1064 EXCEPTION_STORE_GPR3
1065 EXCEPTION_STORE_GPR4
1066 EXCEPTION_STORE_GPR5
1067 EXCEPTION_STORE_GPR6
1070 l.mfspr r6,r0,SPR_ESR_BASE //
1071 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
1072 l.sfeqi r6,0 // r6 == 0x1 --> SM
1073 l.bf exit_with_no_itranslation
1078 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
1083 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
1085 l.mfspr r6, r0, SPR_IMMUCFGR
1086 l.andi r6, r6, SPR_IMMUCFGR_NTS
1087 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
1089 l.sll r5, r5, r6 // r5 = number IMMU sets from IMMUCFGR
1090 l.addi r6, r5, -1 // r6 = nsets mask
1091 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1093 l.or r6,r6,r4 // r6 <- r4
1094 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1095 l.movhi r5,hi(ITLB_MR_MASK) // r5 <- ffff:0000.x000
1096 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
1097 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry
1098 l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR
1101 * set up ITLB with no translation for EA <= 0x0fffffff
1103 * we need this for head.S mapping (EA = PA). if we move all functions
1104 * which run with mmu enabled into entry.S, we might be able to eliminate this.
1107 LOAD_SYMBOL_2_GPR(r6,0x0fffffff)
1108 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
1110 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1112 tophys(r3,r4) // r3 <- PA
1114 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1115 l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000
1116 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
1117 l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry
1118 l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR
1126 l.rfe // SR <- ESR, PC <- EPC
1128 exit_with_no_itranslation:
1131 l.j _dispatch_bus_fault
1134 /* ====================================================================== */
1136 * Stuff below here shouldn't go into .head section... maybe this stuff
1137 * can be moved to entry.S ???
1140 /* ==============================================[ DTLB miss handler ]=== */
1144 * Exception handlers are entered with MMU off so the following handler
1145 * needs to use physical addressing
1150 ENTRY(dtlb_miss_handler)
1151 EXCEPTION_STORE_GPR2
1152 EXCEPTION_STORE_GPR3
1153 EXCEPTION_STORE_GPR4
1155 * get EA of the miss
1157 l.mfspr r2,r0,SPR_EEAR_BASE
1159 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
1161 GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r4 is temp
1162 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1163 l.slli r4,r4,0x2 // to get address << 2
1164 l.add r3,r4,r3 // r4 is pgd_index(daddr)
1166 * if (pmd_none(*pmd))
1170 l.lwz r3,0x0(r4) // get *pmd value
1173 l.addi r3,r0,0xffffe000 // PAGE_MASK
1177 * pte = *pte_offset(pmd, daddr);
1179 l.lwz r4,0x0(r4) // get **pmd value
1180 l.and r4,r4,r3 // & PAGE_MASK
1181 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1182 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1183 l.slli r3,r3,0x2 // to get address << 2
1185 l.lwz r3,0x0(r3) // this is pte at last
1187 * if (!pte_present(pte))
1190 l.sfne r4,r0 // is pte present
1191 l.bnf d_pte_not_present
1192 l.addi r4,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
1194 * fill DTLB TR register
1196 l.and r4,r3,r4 // apply the mask
1197 // Determine number of DMMU sets
1198 l.mfspr r2, r0, SPR_DMMUCFGR
1199 l.andi r2, r2, SPR_DMMUCFGR_NTS
1200 l.srli r2, r2, SPR_DMMUCFGR_NTS_OFF
1202 l.sll r3, r3, r2 // r3 = number DMMU sets DMMUCFGR
1203 l.addi r2, r3, -1 // r2 = nsets mask
1204 l.mfspr r3, r0, SPR_EEAR_BASE
1205 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1206 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1208 l.mtspr r2,r4,SPR_DTLBTR_BASE(0)
1210 * fill DTLB MR register
1212 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1213 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
1214 l.mtspr r2,r4,SPR_DTLBMR_BASE(0)
1225 EXCEPTION_HANDLE(_dtlb_miss_page_fault_handler)
1227 /* ==============================================[ ITLB miss handler ]=== */
1228 ENTRY(itlb_miss_handler)
1229 EXCEPTION_STORE_GPR2
1230 EXCEPTION_STORE_GPR3
1231 EXCEPTION_STORE_GPR4
1233 * get EA of the miss
1235 l.mfspr r2,r0,SPR_EEAR_BASE
1238 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
1241 GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r5 is temp
1242 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1243 l.slli r4,r4,0x2 // to get address << 2
1244 l.add r3,r4,r3 // r4 is pgd_index(daddr)
1246 * if (pmd_none(*pmd))
1250 l.lwz r3,0x0(r4) // get *pmd value
1253 l.addi r3,r0,0xffffe000 // PAGE_MASK
1257 * pte = *pte_offset(pmd, iaddr);
1260 l.lwz r4,0x0(r4) // get **pmd value
1261 l.and r4,r4,r3 // & PAGE_MASK
1262 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1263 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1264 l.slli r3,r3,0x2 // to get address << 2
1266 l.lwz r3,0x0(r3) // this is pte at last
1268 * if (!pte_present(pte))
1272 l.sfne r4,r0 // is pte present
1273 l.bnf i_pte_not_present
1274 l.addi r4,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
1276 * fill ITLB TR register
1278 l.and r4,r3,r4 // apply the mask
1279 l.andi r3,r3,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
1281 l.bf itlb_tr_fill //_workaround
1282 // Determine number of IMMU sets
1283 l.mfspr r2, r0, SPR_IMMUCFGR
1284 l.andi r2, r2, SPR_IMMUCFGR_NTS
1285 l.srli r2, r2, SPR_IMMUCFGR_NTS_OFF
1287 l.sll r3, r3, r2 // r3 = number IMMU sets IMMUCFGR
1288 l.addi r2, r3, -1 // r2 = nsets mask
1289 l.mfspr r3, r0, SPR_EEAR_BASE
1290 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1291 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1295 * we should not just blindly set executable flags,
1296 * but it does help with ping. the clean way would be to find out
1297 * (and fix it) why stack doesn't have execution permissions
1300 itlb_tr_fill_workaround:
1301 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1303 l.mtspr r2,r4,SPR_ITLBTR_BASE(0)
1305 * fill DTLB MR register
1307 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1308 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
1309 l.mtspr r2,r4,SPR_ITLBMR_BASE(0)
1321 EXCEPTION_HANDLE(_itlb_miss_page_fault_handler)
1323 /* ==============================================[ boot tlb handlers ]=== */
1326 /* =================================================[ debugging aids ]=== */
1331 _immu_trampoline_top:
1333 #define TRAMP_SLOT_0 (0x0)
1334 #define TRAMP_SLOT_1 (0x4)
1335 #define TRAMP_SLOT_2 (0x8)
1336 #define TRAMP_SLOT_3 (0xc)
1337 #define TRAMP_SLOT_4 (0x10)
1338 #define TRAMP_SLOT_5 (0x14)
1339 #define TRAMP_FRAME_SIZE (0x18)
1341 ENTRY(_immu_trampoline_workaround)
1343 // r6 is physical EEA
1346 LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
1347 tophys (r3,r5) // r3 is trampoline (physical)
1349 LOAD_SYMBOL_2_GPR(r4,0x15000000)
1350 l.sw TRAMP_SLOT_0(r3),r4
1351 l.sw TRAMP_SLOT_1(r3),r4
1352 l.sw TRAMP_SLOT_4(r3),r4
1353 l.sw TRAMP_SLOT_5(r3),r4
1356 l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address)
1357 l.sw TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data
1358 l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address)
1359 l.sw TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data
1361 l.srli r5,r4,26 // check opcode for write access
1364 l.sfeqi r5,0x11 // l.jr
1366 l.sfeqi r5,1 // l.jal
1368 l.sfeqi r5,0x12 // l.jalr
1370 l.sfeqi r5,3 // l.bnf
1372 l.sfeqi r5,4 // l.bf
1376 l.j 99b // should never happen
1380 // r3 is trampoline address (physical)
1381 // r4 is instruction
1382 // r6 is physical(EEA)
1388 /* 19 20 aa aa l.movhi r9,0xaaaa
1389 * a9 29 bb bb l.ori r9,0xbbbb
1391 * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1394 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1396 // l.movhi r9,0xaaaa
1397 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1398 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1400 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1403 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1404 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1406 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1408 /* falthrough, need to set up new jump offset */
1412 l.slli r6,r4,6 // original offset shifted left 6 - 2
1413 // l.srli r6,r6,6 // original offset shifted right 2
1415 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1416 // l.srli r4,r4,6 // old jump position: shifted right 2
1418 l.addi r5,r3,0xc // new jump position (physical)
1419 l.slli r5,r5,4 // new jump position: shifted left 4
1421 // calculate new jump offset
1422 // new_off = old_off + (old_jump - new_jump)
1424 l.sub r5,r4,r5 // old_jump - new_jump
1425 l.add r5,r6,r5 // orig_off + (old_jump - new_jump)
1426 l.srli r5,r5,6 // new offset shifted right 2
1428 // r5 is new jump offset
1429 // l.j has opcode 0x0...
1430 l.sw TRAMP_SLOT_2(r3),r5 // write it back
1435 /* ----------------------------- */
1439 /* 19 20 aa aa l.movhi r9,0xaaaa
1440 * a9 29 bb bb l.ori r9,0xbbbb
1442 * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1445 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1447 // l.movhi r9,0xaaaa
1448 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1449 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1451 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1454 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1455 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1457 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1459 l.lhz r5,(TRAMP_SLOT_2+0x0)(r3) // load hi part of jump instruction
1460 l.andi r5,r5,0x3ff // clear out opcode part
1461 l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr
1462 l.sh (TRAMP_SLOT_2+0x0)(r3),r5 // write it back
1470 /* ----------------------------- */
1474 l.slli r6,r4,6 // original offset shifted left 6 - 2
1475 // l.srli r6,r6,6 // original offset shifted right 2
1477 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1478 // l.srli r4,r4,6 // old jump position: shifted right 2
1480 l.addi r5,r3,0xc // new jump position (physical)
1481 l.slli r5,r5,4 // new jump position: shifted left 4
1483 // calculate new jump offset
1484 // new_off = old_off + (old_jump - new_jump)
1486 l.add r6,r6,r4 // (orig_off + old_jump)
1487 l.sub r6,r6,r5 // (orig_off + old_jump) - new_jump
1488 l.srli r6,r6,6 // new offset shifted right 2
1490 // r6 is new jump offset
1491 l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction
1493 l.andi r4,r4,0xfc00 // get opcode part
1495 l.or r6,r4,r6 // l.b(n)f new offset
1496 l.sw TRAMP_SLOT_2(r3),r6 // write it back
1498 /* we need to add l.j to EEA + 0x8 */
1499 tophys (r4,r2) // may not be needed (due to shifts down_
1500 l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8)
1501 // jump position = r5 + 0x8 (0x8 compensated)
1502 l.sub r4,r4,r5 // jump offset = target - new_position + 0x8
1504 l.slli r4,r4,4 // the amount of info in imediate of jump
1505 l.srli r4,r4,6 // jump instruction with offset
1506 l.sw TRAMP_SLOT_4(r3),r4 // write it to 4th slot
1511 // set up new EPC to point to our trampoline code
1512 LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
1513 l.mtspr r0,r5,SPR_EPCR_BASE
1515 // immu_trampoline is (4x) CACHE_LINE aligned
1516 // and only 6 instructions long,
1517 // so we need to invalidate only 2 lines
1519 /* Establish cache block size
1522 r14 contain block size
1524 l.mfspr r21,r0,SPR_ICCFGR
1525 l.andi r21,r21,SPR_ICCFGR_CBS
1530 l.mtspr r0,r5,SPR_ICBIR
1532 l.mtspr r0,r5,SPR_ICBIR
1539 * DSCR: prints a string referenced by r3.
1541 * PRMS: r3 - address of the first character of null
1542 * terminated string to be printed
1544 * PREQ: UART at UART_BASE_ADD has to be initialized
1546 * POST: caller should be aware that r3, r9 are changed
1548 ENTRY(_emergency_print)
1549 EMERGENCY_PRINT_STORE_GPR4
1550 EMERGENCY_PRINT_STORE_GPR5
1551 EMERGENCY_PRINT_STORE_GPR6
1552 EMERGENCY_PRINT_STORE_GPR7
1560 l.movhi r4,hi(UART_BASE_ADD)
1578 /* next character */
1583 EMERGENCY_PRINT_LOAD_GPR7
1584 EMERGENCY_PRINT_LOAD_GPR6
1585 EMERGENCY_PRINT_LOAD_GPR5
1586 EMERGENCY_PRINT_LOAD_GPR4
1590 ENTRY(_emergency_print_nr)
1591 EMERGENCY_PRINT_STORE_GPR4
1592 EMERGENCY_PRINT_STORE_GPR5
1593 EMERGENCY_PRINT_STORE_GPR6
1594 EMERGENCY_PRINT_STORE_GPR7
1595 EMERGENCY_PRINT_STORE_GPR8
1597 l.addi r8,r0,32 // shift register
1599 1: /* remove leading zeros */
1604 /* don't skip the last zero if number == 0x0 */
1628 l.movhi r4,hi(UART_BASE_ADD)
1646 /* next character */
1651 EMERGENCY_PRINT_LOAD_GPR8
1652 EMERGENCY_PRINT_LOAD_GPR7
1653 EMERGENCY_PRINT_LOAD_GPR6
1654 EMERGENCY_PRINT_LOAD_GPR5
1655 EMERGENCY_PRINT_LOAD_GPR4
1661 * This should be used for debugging only.
1662 * It messes up the Linux early serial output
1663 * somehow, so use it sparingly and essentially
1664 * only if you need to debug something that goes wrong
1665 * before Linux gets the early serial going.
1667 * Furthermore, you'll have to make sure you set the
1668 * UART_DEVISOR correctly according to the system
1676 #define SYS_CLK 20000000
1677 //#define SYS_CLK 1843200
1678 #define OR32_CONSOLE_BAUD 115200
1679 #define UART_DIVISOR SYS_CLK/(16*OR32_CONSOLE_BAUD)
1681 ENTRY(_early_uart_init)
1682 l.movhi r3,hi(UART_BASE_ADD)
1696 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1697 l.sb UART_DLM(r3),r4
1698 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
1699 l.sb UART_DLL(r3),r4
1706 .global _secondary_evbar
1710 /* Just disable interrupts and Return */
1711 l.ori r3,r0,SPR_SR_SM
1712 l.mtspr r0,r3,SPR_ESR_BASE
1717 _string_unhandled_exception:
1718 .string "\n\rRunarunaround: Unhandled exception 0x\0"
1721 .string ": EPC=0x\0"
1727 /* ========================================[ page aligned structures ]=== */
1730 * .data section should be page aligned
1731 * (look into arch/openrisc/kernel/vmlinux.lds.S)
1735 .global empty_zero_page
1739 .global swapper_pg_dir
1743 .global _unhandled_stack
1746 _unhandled_stack_top:
1748 /* ============================================================[ EOF ]=== */