arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c

   1 /*
   2  * Toshiba rbtx4927 specific setup
   3  *
   4  * Author: MontaVista Software, Inc.
   5  *         source@mvista.com
   6  *
   7  * Copyright 2001-2002 MontaVista Software Inc.
   8  *
   9  * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
  10  * Copyright (C) 2000 RidgeRun, Inc.
  11  * Author: RidgeRun, Inc.
  12  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  13  *
  14  * Copyright 2001 MontaVista Software Inc.
  15  * Author: jsun@mvista.com or jsun@junsun.net
  16  *
  17  * Copyright 2002 MontaVista Software Inc.
  18  * Author: Michael Pruznick, michael_pruznick@mvista.com
  19  *
  20  * Copyright (C) 2000-2001 Toshiba Corporation
  21  *
  22  * Copyright (C) 2004 MontaVista Software Inc.
  23  * Author: Manish Lachwani, mlachwani@mvista.com
  24  *
  25  *  This program is free software; you can redistribute it and/or modify it
  26  *  under the terms of the GNU General Public License as published by the
  27  *  Free Software Foundation; either version 2 of the License, or (at your
  28  *  option) any later version.
  29  *
  30  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  31  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  32  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  33  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  34  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  35  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  36  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  38  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  39  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  *  You should have received a copy of the GNU General Public License along
  42  *  with this program; if not, write to the Free Software Foundation, Inc.,
  43  *  675 Mass Ave, Cambridge, MA 02139, USA.
  44  */
  45 #include <linux/init.h>
  46 #include <linux/kernel.h>
  47 #include <linux/types.h>
  48 #include <linux/mm.h>
  49 #include <linux/swap.h>
  50 #include <linux/ioport.h>
  51 #include <linux/sched.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/pci.h>
  54 #include <linux/timex.h>
  55 #include <linux/pm.h>
  56 #include <linux/platform_device.h>
  57
  58 #include <asm/bootinfo.h>
  59 #include <asm/page.h>
  60 #include <asm/io.h>
  61 #include <asm/irq.h>
  62 #include <asm/irq_regs.h>
  63 #include <asm/processor.h>
  64 #include <asm/reboot.h>
  65 #include <asm/time.h>
  66 #include <asm/txx9tmr.h>
  67 #include <linux/bootmem.h>
  68 #include <linux/blkdev.h>
  69 #ifdef CONFIG_TOSHIBA_FPCIB0
  70 #include <asm/tx4927/smsc_fdc37m81x.h>
  71 #endif
  72 #include <asm/tx4927/toshiba_rbtx4927.h>
  73 #ifdef CONFIG_PCI
  74 #include <asm/tx4927/tx4927_pci.h>
  75 #endif
  76 #ifdef CONFIG_BLK_DEV_IDEPCI
  77 #include <linux/hdreg.h>
  78 #include <linux/ide.h>
  79 #endif
  80 #ifdef CONFIG_SERIAL_TXX9
  81 #include <linux/tty.h>
  82 #include <linux/serial.h>
  83 #include <linux/serial_core.h>
  84 #endif
  85
  86 #undef TOSHIBA_RBTX4927_SETUP_DEBUG
  87
  88 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
  89 #define TOSHIBA_RBTX4927_SETUP_NONE        0x00000000
  90
  91 #define TOSHIBA_RBTX4927_SETUP_INFO        ( 1 <<  0 )
  92 #define TOSHIBA_RBTX4927_SETUP_WARN        ( 1 <<  1 )
  93 #define TOSHIBA_RBTX4927_SETUP_EROR        ( 1 <<  2 )
  94
  95 #define TOSHIBA_RBTX4927_SETUP_EFWFU       ( 1 <<  3 )
  96 #define TOSHIBA_RBTX4927_SETUP_SETUP       ( 1 <<  4 )
  97 #define TOSHIBA_RBTX4927_SETUP_PCIBIOS     ( 1 <<  7 )
  98 #define TOSHIBA_RBTX4927_SETUP_PCI1        ( 1 <<  8 )
  99 #define TOSHIBA_RBTX4927_SETUP_PCI2        ( 1 <<  9 )
 100 #define TOSHIBA_RBTX4927_SETUP_PCI66       ( 1 << 10 )
 101
 102 #define TOSHIBA_RBTX4927_SETUP_ALL         0xffffffff
 103 #endif
 104
 105 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 106 static const u32 toshiba_rbtx4927_setup_debug_flag =
 107     (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
 108      TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
 109      TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
 110      | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
 111      TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
 112 #endif
 113
 114 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 115 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
 116         if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
 117         { \
 118            char tmp[100]; \
 119            sprintf( tmp, str ); \
 120            printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
 121         }
 122 #else
 123 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag, str...)
 124 #endif
 125
 126 /* These functions are used for rebooting or halting the machine*/
 127 extern void toshiba_rbtx4927_restart(char *command);
 128 extern void toshiba_rbtx4927_halt(void);
 129 extern void toshiba_rbtx4927_power_off(void);
 130
 131 int tx4927_using_backplane = 0;
 132
 133 extern void toshiba_rbtx4927_irq_setup(void);
 134
 135 char *prom_getcmdline(void);
 136
 137 #ifdef CONFIG_PCI
 138 #undef TX4927_SUPPORT_COMMAND_IO
 139 #undef  TX4927_SUPPORT_PCI_66
 140 int tx4927_cpu_clock = 100000000;       /* 100MHz */
 141 unsigned long mips_pci_io_base;
 142 unsigned long mips_pci_io_size;
 143 unsigned long mips_pci_mem_base;
 144 unsigned long mips_pci_mem_size;
 145 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 146 unsigned long mips_pci_io_pciaddr = 0;
 147 unsigned long mips_memory_upper;
 148 static int tx4927_ccfg_toeon = 1;
 149 static int tx4927_pcic_trdyto = 0;      /* default: disabled */
 150 unsigned long tx4927_ce_base[8];
 151 void tx4927_reset_pci_pcic(void);
 152 int tx4927_pci66 = 0;           /* 0:auto */
 153 #endif
 154
 155 char *toshiba_name = "";
 156
 157 #ifdef CONFIG_PCI
 158 extern struct pci_controller tx4927_controller;
 159
 160 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
 161                                     int top_bus, int busnr, int devfn)
 162 {
 163         static struct pci_dev dev;
 164         static struct pci_bus bus;
 165
 166         dev.sysdata = (void *)hose;
 167         dev.devfn = devfn;
 168         bus.number = busnr;
 169         bus.ops = hose->pci_ops;
 170         bus.parent = NULL;
 171         dev.bus = &bus;
 172
 173         return &dev;
 174 }
 175
 176 #define EARLY_PCI_OP(rw, size, type)                                    \
 177 static int early_##rw##_config_##size(struct pci_controller *hose,      \
 178         int top_bus, int bus, int devfn, int offset, type value)        \
 179 {                                                                       \
 180         return pci_##rw##_config_##size(                                \
 181                 fake_pci_dev(hose, top_bus, bus, devfn),                \
 182                 offset, value);                                         \
 183 }
 184
 185 EARLY_PCI_OP(read, byte, u8 *)
 186 EARLY_PCI_OP(read, dword, u32 *)
 187 EARLY_PCI_OP(write, byte, u8)
 188 EARLY_PCI_OP(write, dword, u32)
 189
 190 static int __init tx4927_pcibios_init(void)
 191 {
 192         unsigned int id;
 193         u32 pci_devfn;
 194         int devfn_start = 0;
 195         int devfn_stop = 0xff;
 196         int busno = 0; /* One bus on the Toshiba */
 197         struct pci_controller *hose = &tx4927_controller;
 198
 199         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 200                                        "-\n");
 201
 202         for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
 203                 early_read_config_dword(hose, busno, busno, pci_devfn,
 204                                         PCI_VENDOR_ID, &id);
 205
 206                 if (id == 0xffffffff) {
 207                         continue;
 208                 }
 209
 210                 if (id == 0x94601055) {
 211                         u8 v08_64;
 212                         u32 v32_b0;
 213                         u8 v08_e1;
 214 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 215                         char *s = " sb/isa --";
 216 #endif
 217
 218                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 219                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
 220                              s);
 221
 222                         early_read_config_byte(hose, busno, busno,
 223                                                pci_devfn, 0x64, &v08_64);
 224                         early_read_config_dword(hose, busno, busno,
 225                                                 pci_devfn, 0xb0, &v32_b0);
 226                         early_read_config_byte(hose, busno, busno,
 227                                                pci_devfn, 0xe1, &v08_e1);
 228
 229                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 230                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 231                              ":%s beg 0x64 = 0x%02x\n", s, v08_64);
 232                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 233                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 234                              ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
 235                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 236                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 237                              ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
 238
 239                         /* serial irq control */
 240                         v08_64 = 0xd0;
 241
 242                         /* serial irq pin */
 243                         v32_b0 |= 0x00010000;
 244
 245                         /* ide irq on isa14 */
 246                         v08_e1 &= 0xf0;
 247                         v08_e1 |= 0x0d;
 248
 249                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 250                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 251                              ":%s mid 0x64 = 0x%02x\n", s, v08_64);
 252                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 253                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 254                              ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
 255                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 256                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 257                              ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
 258
 259                         early_write_config_byte(hose, busno, busno,
 260                                                 pci_devfn, 0x64, v08_64);
 261                         early_write_config_dword(hose, busno, busno,
 262                                                  pci_devfn, 0xb0, v32_b0);
 263                         early_write_config_byte(hose, busno, busno,
 264                                                 pci_devfn, 0xe1, v08_e1);
 265
 266 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 267                         {
 268                                 early_read_config_byte(hose, busno, busno,
 269                                                        pci_devfn, 0x64,
 270                                                        &v08_64);
 271                                 early_read_config_dword(hose, busno, busno,
 272                                                         pci_devfn, 0xb0,
 273                                                         &v32_b0);
 274                                 early_read_config_byte(hose, busno, busno,
 275                                                        pci_devfn, 0xe1,
 276                                                        &v08_e1);
 277
 278                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 279                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 280                                      ":%s end 0x64 = 0x%02x\n", s, v08_64);
 281                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 282                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 283                                      ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
 284                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 285                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 286                                      ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
 287                         }
 288 #endif
 289
 290                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 291                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
 292                              s);
 293                 }
 294
 295                 if (id == 0x91301055) {
 296                         u8 v08_04;
 297                         u8 v08_09;
 298                         u8 v08_41;
 299                         u8 v08_43;
 300                         u8 v08_5c;
 301 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 302                         char *s = " sb/ide --";
 303 #endif
 304
 305                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 306                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
 307                              s);
 308
 309                         early_read_config_byte(hose, busno, busno,
 310                                                pci_devfn, 0x04, &v08_04);
 311                         early_read_config_byte(hose, busno, busno,
 312                                                pci_devfn, 0x09, &v08_09);
 313                         early_read_config_byte(hose, busno, busno,
 314                                                pci_devfn, 0x41, &v08_41);
 315                         early_read_config_byte(hose, busno, busno,
 316                                                pci_devfn, 0x43, &v08_43);
 317                         early_read_config_byte(hose, busno, busno,
 318                                                pci_devfn, 0x5c, &v08_5c);
 319
 320                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 321                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 322                              ":%s beg 0x04 = 0x%02x\n", s, v08_04);
 323                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 324                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 325                              ":%s beg 0x09 = 0x%02x\n", s, v08_09);
 326                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 327                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 328                              ":%s beg 0x41 = 0x%02x\n", s, v08_41);
 329                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 330                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 331                              ":%s beg 0x43 = 0x%02x\n", s, v08_43);
 332                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 333                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 334                              ":%s beg 0x5c = 0x%02x\n", s, v08_5c);
 335
 336                         /* enable ide master/io */
 337                         v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
 338
 339                         /* enable ide native mode */
 340                         v08_09 |= 0x05;
 341
 342                         /* enable primary ide */
 343                         v08_41 |= 0x80;
 344
 345                         /* enable secondary ide */
 346                         v08_43 |= 0x80;
 347
 348                         /*
 349                          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 350                          *
 351                          * This line of code is intended to provide the user with a work
 352                          * around solution to the anomalies cited in SMSC's anomaly sheet
 353                          * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
 354                          *
 355                          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 356                          */
 357                         v08_5c |= 0x01;
 358
 359                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 360                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 361                              ":%s mid 0x04 = 0x%02x\n", s, v08_04);
 362                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 363                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 364                              ":%s mid 0x09 = 0x%02x\n", s, v08_09);
 365                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 366                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 367                              ":%s mid 0x41 = 0x%02x\n", s, v08_41);
 368                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 369                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 370                              ":%s mid 0x43 = 0x%02x\n", s, v08_43);
 371                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 372                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 373                              ":%s mid 0x5c = 0x%02x\n", s, v08_5c);
 374
 375                         early_write_config_byte(hose, busno, busno,
 376                                                 pci_devfn, 0x5c, v08_5c);
 377                         early_write_config_byte(hose, busno, busno,
 378                                                 pci_devfn, 0x04, v08_04);
 379                         early_write_config_byte(hose, busno, busno,
 380                                                 pci_devfn, 0x09, v08_09);
 381                         early_write_config_byte(hose, busno, busno,
 382                                                 pci_devfn, 0x41, v08_41);
 383                         early_write_config_byte(hose, busno, busno,
 384                                                 pci_devfn, 0x43, v08_43);
 385
 386 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 387                         {
 388                                 early_read_config_byte(hose, busno, busno,
 389                                                        pci_devfn, 0x04,
 390                                                        &v08_04);
 391                                 early_read_config_byte(hose, busno, busno,
 392                                                        pci_devfn, 0x09,
 393                                                        &v08_09);
 394                                 early_read_config_byte(hose, busno, busno,
 395                                                        pci_devfn, 0x41,
 396                                                        &v08_41);
 397                                 early_read_config_byte(hose, busno, busno,
 398                                                        pci_devfn, 0x43,
 399                                                        &v08_43);
 400                                 early_read_config_byte(hose, busno, busno,
 401                                                        pci_devfn, 0x5c,
 402                                                        &v08_5c);
 403
 404                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 405                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 406                                      ":%s end 0x04 = 0x%02x\n", s, v08_04);
 407                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 408                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 409                                      ":%s end 0x09 = 0x%02x\n", s, v08_09);
 410                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 411                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 412                                      ":%s end 0x41 = 0x%02x\n", s, v08_41);
 413                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 414                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 415                                      ":%s end 0x43 = 0x%02x\n", s, v08_43);
 416                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 417                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 418                                      ":%s end 0x5c = 0x%02x\n", s, v08_5c);
 419                         }
 420 #endif
 421
 422                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 423                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
 424                              s);
 425                 }
 426
 427         }
 428
 429         register_pci_controller(&tx4927_controller);
 430         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 431                                        "+\n");
 432
 433         return 0;
 434 }
 435
 436 arch_initcall(tx4927_pcibios_init);
 437
 438 extern struct resource pci_io_resource;
 439 extern struct resource pci_mem_resource;
 440
 441 void __init tx4927_pci_setup(void)
 442 {
 443         static int called = 0;
 444         extern unsigned int tx4927_get_mem_size(void);
 445
 446         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
 447
 448         mips_memory_upper = tx4927_get_mem_size() << 20;
 449         mips_memory_upper += KSEG0;
 450         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 451                                        "0x%08lx=mips_memory_upper\n",
 452                                        mips_memory_upper);
 453         mips_pci_io_base = TX4927_PCIIO;
 454         mips_pci_io_size = TX4927_PCIIO_SIZE;
 455         mips_pci_mem_base = TX4927_PCIMEM;
 456         mips_pci_mem_size = TX4927_PCIMEM_SIZE;
 457
 458         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 459                                        "0x%08lx=mips_pci_io_base\n",
 460                                        mips_pci_io_base);
 461         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 462                                        "0x%08lx=mips_pci_io_size\n",
 463                                        mips_pci_io_size);
 464         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 465                                        "0x%08lx=mips_pci_mem_base\n",
 466                                        mips_pci_mem_base);
 467         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 468                                        "0x%08lx=mips_pci_mem_size\n",
 469                                        mips_pci_mem_size);
 470         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 471                                        "0x%08lx=pci_io_resource.start\n",
 472                                        pci_io_resource.start);
 473         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 474                                        "0x%08lx=pci_io_resource.end\n",
 475                                        pci_io_resource.end);
 476         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 477                                        "0x%08lx=pci_mem_resource.start\n",
 478                                        pci_mem_resource.start);
 479         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 480                                        "0x%08lx=pci_mem_resource.end\n",
 481                                        pci_mem_resource.end);
 482         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 483                                        "0x%08lx=mips_io_port_base",
 484                                        mips_io_port_base);
 485         if (!called) {
 486                 printk
 487                     ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
 488                      toshiba_name,
 489                      (unsigned short) (tx4927_pcicptr->pciid >> 16),
 490                      (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
 491                      (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
 492                      (!(tx4927_ccfgptr->
 493                         ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
 494                      "Internal");
 495                 called = 1;
 496         }
 497         printk("%s PCIC --%s PCICLK:", toshiba_name,
 498                (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
 499         if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
 500                 int pciclk = 0;
 501                 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
 502                         switch ((unsigned long) tx4927_ccfgptr->
 503                                 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
 504                         case TX4937_CCFG_PCIDIVMODE_4:
 505                                 pciclk = tx4927_cpu_clock / 4;
 506                                 break;
 507                         case TX4937_CCFG_PCIDIVMODE_4_5:
 508                                 pciclk = tx4927_cpu_clock * 2 / 9;
 509                                 break;
 510                         case TX4937_CCFG_PCIDIVMODE_5:
 511                                 pciclk = tx4927_cpu_clock / 5;
 512                                 break;
 513                         case TX4937_CCFG_PCIDIVMODE_5_5:
 514                                 pciclk = tx4927_cpu_clock * 2 / 11;
 515                                 break;
 516                         case TX4937_CCFG_PCIDIVMODE_8:
 517                                 pciclk = tx4927_cpu_clock / 8;
 518                                 break;
 519                         case TX4937_CCFG_PCIDIVMODE_9:
 520                                 pciclk = tx4927_cpu_clock / 9;
 521                                 break;
 522                         case TX4937_CCFG_PCIDIVMODE_10:
 523                                 pciclk = tx4927_cpu_clock / 10;
 524                                 break;
 525                         case TX4937_CCFG_PCIDIVMODE_11:
 526                                 pciclk = tx4927_cpu_clock / 11;
 527                                 break;
 528                         }
 529
 530                 else
 531                         switch ((unsigned long) tx4927_ccfgptr->
 532                                 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
 533                         case TX4927_CCFG_PCIDIVMODE_2_5:
 534                                 pciclk = tx4927_cpu_clock * 2 / 5;
 535                                 break;
 536                         case TX4927_CCFG_PCIDIVMODE_3:
 537                                 pciclk = tx4927_cpu_clock / 3;
 538                                 break;
 539                         case TX4927_CCFG_PCIDIVMODE_5:
 540                                 pciclk = tx4927_cpu_clock / 5;
 541                                 break;
 542                         case TX4927_CCFG_PCIDIVMODE_6:
 543                                 pciclk = tx4927_cpu_clock / 6;
 544                                 break;
 545                         }
 546
 547                 printk("Internal(%dMHz)", pciclk / 1000000);
 548         } else {
 549                 int pciclk = 0;
 550                 int pciclk_setting = *tx4927_pci_clk_ptr;
 551                 switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
 552                 case TX4927_PCI_CLK_33:
 553                         pciclk = 33333333;
 554                         break;
 555                 case TX4927_PCI_CLK_25:
 556                         pciclk = 25000000;
 557                         break;
 558                 case TX4927_PCI_CLK_66:
 559                         pciclk = 66666666;
 560                         break;
 561                 case TX4927_PCI_CLK_50:
 562                         pciclk = 50000000;
 563                         break;
 564                 }
 565                 printk("External(%dMHz)", pciclk / 1000000);
 566         }
 567         printk("\n");
 568
 569
 570
 571         /* GB->PCI mappings */
 572         tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
 573         tx4927_pcicptr->g2piogbase = mips_pci_io_base |
 574 #ifdef __BIG_ENDIAN
 575             TX4927_PCIC_G2PIOGBASE_ECHG
 576 #else
 577             TX4927_PCIC_G2PIOGBASE_BSDIS
 578 #endif
 579             ;
 580
 581         tx4927_pcicptr->g2piopbase = 0;
 582
 583         tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
 584         tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
 585 #ifdef __BIG_ENDIAN
 586             TX4927_PCIC_G2PMnGBASE_ECHG
 587 #else
 588             TX4927_PCIC_G2PMnGBASE_BSDIS
 589 #endif
 590             ;
 591         tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
 592
 593         tx4927_pcicptr->g2pmmask[1] = 0;
 594         tx4927_pcicptr->g2pmgbase[1] = 0;
 595         tx4927_pcicptr->g2pmpbase[1] = 0;
 596         tx4927_pcicptr->g2pmmask[2] = 0;
 597         tx4927_pcicptr->g2pmgbase[2] = 0;
 598         tx4927_pcicptr->g2pmpbase[2] = 0;
 599
 600
 601         /* PCI->GB mappings (I/O 256B) */
 602         tx4927_pcicptr->p2giopbase = 0; /* 256B */
 603
 604         /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
 605         tx4927_pcicptr->p2gm0plbase = 0;
 606         tx4927_pcicptr->p2gm0pubase = 0;
 607         tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
 608 #ifdef __BIG_ENDIAN
 609             TX4927_PCIC_P2GMnGBASE_TECHG
 610 #else
 611             TX4927_PCIC_P2GMnGBASE_TBSDIS
 612 #endif
 613             ;
 614
 615         /* PCI->GB mappings (MEM 16MB) -not used */
 616         tx4927_pcicptr->p2gm1plbase = 0xffffffff;
 617         tx4927_pcicptr->p2gm1pubase = 0xffffffff;
 618         tx4927_pcicptr->p2gmgbase[1] = 0;
 619
 620         /* PCI->GB mappings (MEM 1MB) -not used */
 621         tx4927_pcicptr->p2gm2pbase = 0xffffffff;
 622         tx4927_pcicptr->p2gmgbase[2] = 0;
 623
 624
 625         /* Enable Initiator Memory 0 Space, I/O Space, Config */
 626         tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
 627         tx4927_pcicptr->pciccfg |=
 628             TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
 629             TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
 630
 631
 632         /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
 633         tx4927_pcicptr->pcicfg1 = 0;
 634
 635         if (tx4927_pcic_trdyto >= 0) {
 636                 tx4927_pcicptr->g2ptocnt &= ~0xff;
 637                 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
 638         }
 639
 640         /* Clear All Local Bus Status */
 641         tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
 642         /* Enable All Local Bus Interrupts */
 643         tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
 644         /* Clear All Initiator Status */
 645         tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
 646         /* Enable All Initiator Interrupts */
 647         tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
 648         /* Clear All PCI Status Error */
 649         tx4927_pcicptr->pcistatus =
 650             (tx4927_pcicptr->pcistatus & 0x0000ffff) |
 651             (TX4927_PCIC_PCISTATUS_ALL << 16);
 652         /* Enable All PCI Status Error Interrupts */
 653         tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
 654
 655         /* PCIC Int => IRC IRQ16 */
 656         tx4927_pcicptr->pcicfg2 =
 657             (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
 658
 659         if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
 660                 /* XXX */
 661         } else {
 662                 /* Reset Bus Arbiter */
 663                 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
 664                 /* Enable Bus Arbiter */
 665                 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
 666         }
 667
 668         tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
 669             PCI_COMMAND_MEMORY |
 670             PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 671
 672         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 673                                        ":pci setup complete:\n");
 674         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
 675 }
 676
 677 #endif /* CONFIG_PCI */
 678
 679 static void __noreturn wait_forever(void)
 680 {
 681         while (1)
 682                 if (cpu_wait)
 683                         (*cpu_wait)();
 684 }
 685
 686 void toshiba_rbtx4927_restart(char *command)
 687 {
 688         printk(KERN_NOTICE "System Rebooting...\n");
 689
 690         /* enable the s/w reset register */
 691         writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);
 692
 693         /* wait for enable to be seen */
 694         while ((readb(RBTX4927_SW_RESET_ENABLE) &
 695                 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
 696
 697         /* do a s/w reset */
 698         writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);
 699
 700         /* do something passive while waiting for reset */
 701         local_irq_disable();
 702         wait_forever();
 703         /* no return */
 704 }
 705
 706
 707 void toshiba_rbtx4927_halt(void)
 708 {
 709         printk(KERN_NOTICE "System Halted\n");
 710         local_irq_disable();
 711         wait_forever();
 712         /* no return */
 713 }
 714
 715 void toshiba_rbtx4927_power_off(void)
 716 {
 717         toshiba_rbtx4927_halt();
 718         /* no return */
 719 }
 720
 721 void __init toshiba_rbtx4927_setup(void)
 722 {
 723         int i;
 724         u32 cp0_config;
 725         char *argptr;
 726
 727         printk("CPU is %s\n", toshiba_name);
 728
 729         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 730                                        "-\n");
 731
 732         /* f/w leaves this on at startup */
 733         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 734                                        ":Clearing STO_ERL.\n");
 735         clear_c0_status(ST0_ERL);
 736
 737         /* enable caches -- HCP5 does this, pmon does not */
 738         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 739                                        ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
 740         cp0_config = read_c0_config();
 741         cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
 742         write_c0_config(cp0_config);
 743
 744 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 745         {
 746                 extern void dump_cp0(char *);
 747                 dump_cp0("toshiba_rbtx4927_early_fw_fixup");
 748         }
 749 #endif
 750
 751         set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
 752         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 753                                        ":mips_io_port_base=0x%08lx\n",
 754                                        mips_io_port_base);
 755
 756         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 757                                        ":Resource\n");
 758         ioport_resource.end = 0xffffffff;
 759         iomem_resource.end = 0xffffffff;
 760
 761         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 762                                        ":ResetRoutines\n");
 763         _machine_restart = toshiba_rbtx4927_restart;
 764         _machine_halt = toshiba_rbtx4927_halt;
 765         pm_power_off = toshiba_rbtx4927_power_off;
 766
 767         for (i = 0; i < TX4927_NR_TMR; i++)
 768                 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
 769
 770 #ifdef CONFIG_PCI
 771
 772         /* PCIC */
 773         /*
 774            * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
 775            *
 776            * For TX4927:
 777            * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
 778            * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
 779            * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
 780            * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
 781            * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
 782            * i.e. S9[3]: ON (83MHz), OFF (100MHz)
 783            *
 784            * For TX4937:
 785            * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
 786            * PCIDIVMODE[10] is 0.
 787            * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
 788            * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
 789            * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
 790            * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
 791            * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
 792            * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
 793            *
 794          */
 795         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
 796                                        "ccfg is %lx, PCIDIVMODE is %x\n",
 797                                        (unsigned long) tx4927_ccfgptr->ccfg,
 798                                        (unsigned long) tx4927_ccfgptr->ccfg &
 799                                        (mips_machtype == MACH_TOSHIBA_RBTX4937 ?
 800                                         TX4937_CCFG_PCIDIVMODE_MASK :
 801                                         TX4927_CCFG_PCIDIVMODE_MASK));
 802
 803         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
 804                                        "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
 805                                        (unsigned long) tx4927_ccfgptr->
 806                                        ccfg & TX4927_CCFG_PCI66,
 807                                        (unsigned long) tx4927_ccfgptr->
 808                                        ccfg & TX4927_CCFG_PCIMIDE,
 809                                        (unsigned long) tx4927_ccfgptr->
 810                                        ccfg & TX4927_CCFG_PCIXARB);
 811
 812         if (mips_machtype == MACH_TOSHIBA_RBTX4937)
 813                 switch ((unsigned long)tx4927_ccfgptr->
 814                         ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
 815                 case TX4937_CCFG_PCIDIVMODE_8:
 816                 case TX4937_CCFG_PCIDIVMODE_4:
 817                         tx4927_cpu_clock = 266666666;   /* 266MHz */
 818                         break;
 819                 case TX4937_CCFG_PCIDIVMODE_9:
 820                 case TX4937_CCFG_PCIDIVMODE_4_5:
 821                         tx4927_cpu_clock = 300000000;   /* 300MHz */
 822                         break;
 823                 default:
 824                         tx4927_cpu_clock = 333333333;   /* 333MHz */
 825                 }
 826         else
 827                 switch ((unsigned long)tx4927_ccfgptr->
 828                         ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
 829                 case TX4927_CCFG_PCIDIVMODE_2_5:
 830                 case TX4927_CCFG_PCIDIVMODE_5:
 831                         tx4927_cpu_clock = 166666666;   /* 166MHz */
 832                         break;
 833                 default:
 834                         tx4927_cpu_clock = 200000000;   /* 200MHz */
 835                 }
 836
 837         /* CCFG */
 838         /* enable Timeout BusError */
 839         if (tx4927_ccfg_toeon)
 840                 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
 841
 842         tx4927_pci_setup();
 843         if (tx4927_using_backplane == 1)
 844                 printk("backplane board IS installed\n");
 845         else
 846                 printk("No Backplane \n");
 847
 848         /* this is on ISA bus behind PCI bus, so need PCI up first */
 849 #ifdef CONFIG_TOSHIBA_FPCIB0
 850         {
 851                 if (tx4927_using_backplane) {
 852                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 853                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 854                              ":fpcibo=yes\n");
 855
 856                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 857                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 858                              ":smsc_fdc37m81x_init()\n");
 859                         smsc_fdc37m81x_init(0x3f0);
 860
 861                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 862                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 863                              ":smsc_fdc37m81x_config_beg()\n");
 864                         smsc_fdc37m81x_config_beg();
 865
 866                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 867                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 868                              ":smsc_fdc37m81x_config_set(KBD)\n");
 869                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
 870                                                   SMSC_FDC37M81X_KBD);
 871                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
 872                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
 873                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
 874                                                   1);
 875
 876                         smsc_fdc37m81x_config_end();
 877                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 878                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 879                              ":smsc_fdc37m81x_config_end()\n");
 880                 } else {
 881                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 882                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 883                              ":fpcibo=not_found\n");
 884                 }
 885         }
 886 #else
 887         {
 888                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 889                     (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
 890         }
 891 #endif
 892
 893 #endif /* CONFIG_PCI */
 894
 895 #ifdef CONFIG_SERIAL_TXX9
 896         {
 897                 extern int early_serial_txx9_setup(struct uart_port *port);
 898                 struct uart_port req;
 899                 for(i = 0; i < 2; i++) {
 900                         memset(&req, 0, sizeof(req));
 901                         req.line = i;
 902                         req.iotype = UPIO_MEM;
 903                         req.membase = (char *)(0xff1ff300 + i * 0x100);
 904                         req.mapbase = 0xff1ff300 + i * 0x100;
 905                         req.irq = TX4927_IRQ_PIC_BEG + 8 + i;
 906                         req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 907                         req.uartclk = 50000000;
 908                         early_serial_txx9_setup(&req);
 909                 }
 910         }
 911 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 912         argptr = prom_getcmdline();
 913         if (strstr(argptr, "console=") == NULL) {
 914                 strcat(argptr, " console=ttyS0,38400");
 915         }
 916 #endif
 917 #endif
 918
 919 #ifdef CONFIG_ROOT_NFS
 920         argptr = prom_getcmdline();
 921         if (strstr(argptr, "root=") == NULL) {
 922                 strcat(argptr, " root=/dev/nfs rw");
 923         }
 924 #endif
 925
 926
 927 #ifdef CONFIG_IP_PNP
 928         argptr = prom_getcmdline();
 929         if (strstr(argptr, "ip=") == NULL) {
 930                 strcat(argptr, " ip=any");
 931         }
 932 #endif
 933
 934
 935         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 936                                "+\n");
 937 }
 938
 939 void __init
 940 toshiba_rbtx4927_time_init(void)
 941 {
 942         mips_hpt_frequency = tx4927_cpu_clock / 2;
 943         if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS)
 944                 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
 945                                      TXX9_IRQ_BASE + 17,
 946                                      50000000);
 947 }
 948
 949 static int __init toshiba_rbtx4927_rtc_init(void)
 950 {
 951         static struct resource __initdata res = {
 952                 .start  = 0x1c010000,
 953                 .end    = 0x1c010000 + 0x800 - 1,
 954                 .flags  = IORESOURCE_MEM,
 955         };
 956         struct platform_device *dev =
 957                 platform_device_register_simple("rtc-ds1742", -1, &res, 1);
 958         return IS_ERR(dev) ? PTR_ERR(dev) : 0;
 959 }
 960 device_initcall(toshiba_rbtx4927_rtc_init);
 961
 962 static int __init rbtx4927_ne_init(void)
 963 {
 964         static struct resource __initdata res[] = {
 965                 {
 966                         .start  = RBTX4927_RTL_8019_BASE,
 967                         .end    = RBTX4927_RTL_8019_BASE + 0x20 - 1,
 968                         .flags  = IORESOURCE_IO,
 969                 }, {
 970                         .start  = RBTX4927_RTL_8019_IRQ,
 971                         .flags  = IORESOURCE_IRQ,
 972                 }
 973         };
 974         struct platform_device *dev =
 975                 platform_device_register_simple("ne", -1,
 976                                                 res, ARRAY_SIZE(res));
 977         return IS_ERR(dev) ? PTR_ERR(dev) : 0;
 978 }
 979 device_initcall(rbtx4927_ne_init);