2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/init.h>
48 #define IMM_MASK 0xffff
50 #define JIMM_MASK 0x3ffffff
52 #define FUNC_MASK 0x3f
56 #define SCIMM_MASK 0xfffff
61 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
62 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
63 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
64 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
65 insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
66 insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
67 insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
68 insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw,
69 insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
70 insn_dins, insn_syscall
79 /* This macro sets the non-variable bits of an instruction. */
80 #define M(a, b, c, d, e, f) \
88 static struct insn insn_table[] __cpuinitdata = {
89 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
90 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
91 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
92 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
93 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
94 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
95 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
96 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
97 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
98 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
99 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
100 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
101 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
102 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
103 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
104 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
105 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
106 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
107 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
108 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
109 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
110 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
111 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
112 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
113 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
114 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
115 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
116 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
117 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
118 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
119 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
120 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
121 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
122 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
123 { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
124 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
125 { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
126 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
127 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
128 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
129 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
130 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
131 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
132 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
133 { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
134 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
135 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
136 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
137 { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
138 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
139 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
140 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
141 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
142 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
143 { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
144 { insn_invalid, 0, 0 }
149 static inline __cpuinit u32 build_rs(u32 arg)
152 printk(KERN_WARNING "Micro-assembler field overflow\n");
154 return (arg & RS_MASK) << RS_SH;
157 static inline __cpuinit u32 build_rt(u32 arg)
160 printk(KERN_WARNING "Micro-assembler field overflow\n");
162 return (arg & RT_MASK) << RT_SH;
165 static inline __cpuinit u32 build_rd(u32 arg)
168 printk(KERN_WARNING "Micro-assembler field overflow\n");
170 return (arg & RD_MASK) << RD_SH;
173 static inline __cpuinit u32 build_re(u32 arg)
176 printk(KERN_WARNING "Micro-assembler field overflow\n");
178 return (arg & RE_MASK) << RE_SH;
181 static inline __cpuinit u32 build_simm(s32 arg)
183 if (arg > 0x7fff || arg < -0x8000)
184 printk(KERN_WARNING "Micro-assembler field overflow\n");
189 static inline __cpuinit u32 build_uimm(u32 arg)
192 printk(KERN_WARNING "Micro-assembler field overflow\n");
194 return arg & IMM_MASK;
197 static inline __cpuinit u32 build_bimm(s32 arg)
199 if (arg > 0x1ffff || arg < -0x20000)
200 printk(KERN_WARNING "Micro-assembler field overflow\n");
203 printk(KERN_WARNING "Invalid micro-assembler branch target\n");
205 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
208 static inline __cpuinit u32 build_jimm(u32 arg)
210 if (arg & ~((JIMM_MASK) << 2))
211 printk(KERN_WARNING "Micro-assembler field overflow\n");
213 return (arg >> 2) & JIMM_MASK;
216 static inline __cpuinit u32 build_scimm(u32 arg)
218 if (arg & ~SCIMM_MASK)
219 printk(KERN_WARNING "Micro-assembler field overflow\n");
221 return (arg & SCIMM_MASK) << SCIMM_SH;
224 static inline __cpuinit u32 build_func(u32 arg)
226 if (arg & ~FUNC_MASK)
227 printk(KERN_WARNING "Micro-assembler field overflow\n");
229 return arg & FUNC_MASK;
232 static inline __cpuinit u32 build_set(u32 arg)
235 printk(KERN_WARNING "Micro-assembler field overflow\n");
237 return arg & SET_MASK;
241 * The order of opcode arguments is implicitly left to right,
242 * starting with RS and ending with FUNC or IMM.
244 static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
246 struct insn *ip = NULL;
251 for (i = 0; insn_table[i].opcode != insn_invalid; i++)
252 if (insn_table[i].opcode == opc) {
257 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
258 panic("Unsupported Micro-assembler instruction %d", opc);
263 op |= build_rs(va_arg(ap, u32));
265 op |= build_rt(va_arg(ap, u32));
267 op |= build_rd(va_arg(ap, u32));
269 op |= build_re(va_arg(ap, u32));
270 if (ip->fields & SIMM)
271 op |= build_simm(va_arg(ap, s32));
272 if (ip->fields & UIMM)
273 op |= build_uimm(va_arg(ap, u32));
274 if (ip->fields & BIMM)
275 op |= build_bimm(va_arg(ap, s32));
276 if (ip->fields & JIMM)
277 op |= build_jimm(va_arg(ap, u32));
278 if (ip->fields & FUNC)
279 op |= build_func(va_arg(ap, u32));
280 if (ip->fields & SET)
281 op |= build_set(va_arg(ap, u32));
282 if (ip->fields & SCIMM)
283 op |= build_scimm(va_arg(ap, u32));
290 #define I_u1u2u3(op) \
293 build_insn(buf, insn##op, a, b, c); \
296 #define I_u2u1u3(op) \
299 build_insn(buf, insn##op, b, a, c); \
302 #define I_u3u1u2(op) \
305 build_insn(buf, insn##op, b, c, a); \
308 #define I_u1u2s3(op) \
311 build_insn(buf, insn##op, a, b, c); \
314 #define I_u2s3u1(op) \
317 build_insn(buf, insn##op, c, a, b); \
320 #define I_u2u1s3(op) \
323 build_insn(buf, insn##op, b, a, c); \
326 #define I_u2u1msbu3(op) \
329 build_insn(buf, insn##op, b, a, c+d-1, c); \
335 build_insn(buf, insn##op, a, b); \
341 build_insn(buf, insn##op, a, b); \
347 build_insn(buf, insn##op, a); \
353 build_insn(buf, insn##op); \
413 void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
420 int __cpuinit uasm_in_compat_space_p(long addr)
422 /* Is this address in 32bit compat space? */
424 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
430 static int __cpuinit uasm_rel_highest(long val)
433 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
439 static int __cpuinit uasm_rel_higher(long val)
442 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
448 int __cpuinit uasm_rel_hi(long val)
450 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
453 int __cpuinit uasm_rel_lo(long val)
455 return ((val & 0xffff) ^ 0x8000) - 0x8000;
458 void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
460 if (!uasm_in_compat_space_p(addr)) {
461 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
462 if (uasm_rel_higher(addr))
463 uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
464 if (uasm_rel_hi(addr)) {
465 uasm_i_dsll(buf, rs, rs, 16);
466 uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr));
467 uasm_i_dsll(buf, rs, rs, 16);
469 uasm_i_dsll32(buf, rs, rs, 0);
471 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
474 void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
476 UASM_i_LA_mostly(buf, rs, addr);
477 if (uasm_rel_lo(addr)) {
478 if (!uasm_in_compat_space_p(addr))
479 uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr));
481 uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
485 /* Handle relocations. */
487 uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
490 (*rel)->type = R_MIPS_PC16;
495 static inline void __cpuinit
496 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
498 long laddr = (long)lab->addr;
499 long raddr = (long)rel->addr;
503 *rel->addr |= build_bimm(laddr - (raddr + 4));
507 panic("Unsupported Micro-assembler relocation %d",
513 uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
515 struct uasm_label *l;
517 for (; rel->lab != UASM_LABEL_INVALID; rel++)
518 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
519 if (rel->lab == l->lab)
520 __resolve_relocs(rel, l);
524 uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
526 for (; rel->lab != UASM_LABEL_INVALID; rel++)
527 if (rel->addr >= first && rel->addr < end)
532 uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
534 for (; lab->lab != UASM_LABEL_INVALID; lab++)
535 if (lab->addr >= first && lab->addr < end)
540 uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
541 u32 *end, u32 *target)
543 long off = (long)(target - first);
545 memcpy(target, first, (end - first) * sizeof(u32));
547 uasm_move_relocs(rel, first, end, off);
548 uasm_move_labels(lab, first, end, off);
551 int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
553 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
554 if (rel->addr == addr
555 && (rel->type == R_MIPS_PC16
556 || rel->type == R_MIPS_26))
563 /* Convenience functions for labeled branches. */
565 uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
567 uasm_r_mips_pc16(r, *p, lid);
568 uasm_i_bltz(p, reg, 0);
572 uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
574 uasm_r_mips_pc16(r, *p, lid);
579 uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
581 uasm_r_mips_pc16(r, *p, lid);
582 uasm_i_beqz(p, reg, 0);
586 uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
588 uasm_r_mips_pc16(r, *p, lid);
589 uasm_i_beqzl(p, reg, 0);
593 uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
594 unsigned int reg2, int lid)
596 uasm_r_mips_pc16(r, *p, lid);
597 uasm_i_bne(p, reg1, reg2, 0);
601 uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
603 uasm_r_mips_pc16(r, *p, lid);
604 uasm_i_bnez(p, reg, 0);
608 uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
610 uasm_r_mips_pc16(r, *p, lid);
611 uasm_i_bgezl(p, reg, 0);
615 uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
617 uasm_r_mips_pc16(r, *p, lid);
618 uasm_i_bgez(p, reg, 0);