arch/mips/kvm/mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/errno.h>
  14 #include <linux/err.h>
  15 #include <linux/kdebug.h>
  16 #include <linux/module.h>
  17 #include <linux/uaccess.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/sched/signal.h>
  20 #include <linux/fs.h>
  21 #include <linux/bootmem.h>
  22
  23 #include <asm/fpu.h>
  24 #include <asm/page.h>
  25 #include <asm/cacheflush.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/pgalloc.h>
  28 #include <asm/pgtable.h>
  29
  30 #include <linux/kvm_host.h>
  31
  32 #include "interrupt.h"
  33 #include "commpage.h"
  34
  35 #define CREATE_TRACE_POINTS
  36 #include "trace.h"
  37
  38 #ifndef VECTORSPACING
  39 #define VECTORSPACING 0x100     /* for EI/VI mode */
  40 #endif
  41
  42 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
  43 struct kvm_stats_debugfs_item debugfs_entries[] = {
  44         { "wait",         VCPU_STAT(wait_exits),         KVM_STAT_VCPU },
  45         { "cache",        VCPU_STAT(cache_exits),        KVM_STAT_VCPU },
  46         { "signal",       VCPU_STAT(signal_exits),       KVM_STAT_VCPU },
  47         { "interrupt",    VCPU_STAT(int_exits),          KVM_STAT_VCPU },
  48         { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
  49         { "tlbmod",       VCPU_STAT(tlbmod_exits),       KVM_STAT_VCPU },
  50         { "tlbmiss_ld",   VCPU_STAT(tlbmiss_ld_exits),   KVM_STAT_VCPU },
  51         { "tlbmiss_st",   VCPU_STAT(tlbmiss_st_exits),   KVM_STAT_VCPU },
  52         { "addrerr_st",   VCPU_STAT(addrerr_st_exits),   KVM_STAT_VCPU },
  53         { "addrerr_ld",   VCPU_STAT(addrerr_ld_exits),   KVM_STAT_VCPU },
  54         { "syscall",      VCPU_STAT(syscall_exits),      KVM_STAT_VCPU },
  55         { "resvd_inst",   VCPU_STAT(resvd_inst_exits),   KVM_STAT_VCPU },
  56         { "break_inst",   VCPU_STAT(break_inst_exits),   KVM_STAT_VCPU },
  57         { "trap_inst",    VCPU_STAT(trap_inst_exits),    KVM_STAT_VCPU },
  58         { "msa_fpe",      VCPU_STAT(msa_fpe_exits),      KVM_STAT_VCPU },
  59         { "fpe",          VCPU_STAT(fpe_exits),          KVM_STAT_VCPU },
  60         { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
  61         { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
  62 #ifdef CONFIG_KVM_MIPS_VZ
  63         { "vz_gpsi",      VCPU_STAT(vz_gpsi_exits),      KVM_STAT_VCPU },
  64         { "vz_gsfc",      VCPU_STAT(vz_gsfc_exits),      KVM_STAT_VCPU },
  65         { "vz_hc",        VCPU_STAT(vz_hc_exits),        KVM_STAT_VCPU },
  66         { "vz_grr",       VCPU_STAT(vz_grr_exits),       KVM_STAT_VCPU },
  67         { "vz_gva",       VCPU_STAT(vz_gva_exits),       KVM_STAT_VCPU },
  68         { "vz_ghfc",      VCPU_STAT(vz_ghfc_exits),      KVM_STAT_VCPU },
  69         { "vz_gpa",       VCPU_STAT(vz_gpa_exits),       KVM_STAT_VCPU },
  70         { "vz_resvd",     VCPU_STAT(vz_resvd_exits),     KVM_STAT_VCPU },
  71 #endif
  72         { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
  73         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
  74         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
  75         { "halt_wakeup",  VCPU_STAT(halt_wakeup),        KVM_STAT_VCPU },
  76         {NULL}
  77 };
  78
  79 bool kvm_trace_guest_mode_change;
  80
  81 int kvm_guest_mode_change_trace_reg(void)
  82 {
  83         kvm_trace_guest_mode_change = 1;
  84         return 0;
  85 }
  86
  87 void kvm_guest_mode_change_trace_unreg(void)
  88 {
  89         kvm_trace_guest_mode_change = 0;
  90 }
  91
  92 /*
  93  * XXXKYMA: We are simulatoring a processor that has the WII bit set in
  94  * Config7, so we are "runnable" if interrupts are pending
  95  */
  96 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
  97 {
  98         return !!(vcpu->arch.pending_exceptions);
  99 }
 100
 101 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
 102 {
 103         return false;
 104 }
 105
 106 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
 107 {
 108         return 1;
 109 }
 110
 111 int kvm_arch_hardware_enable(void)
 112 {
 113         return kvm_mips_callbacks->hardware_enable();
 114 }
 115
 116 void kvm_arch_hardware_disable(void)
 117 {
 118         kvm_mips_callbacks->hardware_disable();
 119 }
 120
 121 int kvm_arch_hardware_setup(void)
 122 {
 123         return 0;
 124 }
 125
 126 void kvm_arch_check_processor_compat(void *rtn)
 127 {
 128         *(int *)rtn = 0;
 129 }
 130
 131 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 132 {
 133         switch (type) {
 134 #ifdef CONFIG_KVM_MIPS_VZ
 135         case KVM_VM_MIPS_VZ:
 136 #else
 137         case KVM_VM_MIPS_TE:
 138 #endif
 139                 break;
 140         default:
 141                 /* Unsupported KVM type */
 142                 return -EINVAL;
 143         };
 144
 145         /* Allocate page table to map GPA -> RPA */
 146         kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
 147         if (!kvm->arch.gpa_mm.pgd)
 148                 return -ENOMEM;
 149
 150         return 0;
 151 }
 152
 153 bool kvm_arch_has_vcpu_debugfs(void)
 154 {
 155         return false;
 156 }
 157
 158 int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu)
 159 {
 160         return 0;
 161 }
 162
 163 void kvm_mips_free_vcpus(struct kvm *kvm)
 164 {
 165         unsigned int i;
 166         struct kvm_vcpu *vcpu;
 167
 168         kvm_for_each_vcpu(i, vcpu, kvm) {
 169                 kvm_arch_vcpu_free(vcpu);
 170         }
 171
 172         mutex_lock(&kvm->lock);
 173
 174         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
 175                 kvm->vcpus[i] = NULL;
 176
 177         atomic_set(&kvm->online_vcpus, 0);
 178
 179         mutex_unlock(&kvm->lock);
 180 }
 181
 182 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
 183 {
 184         /* It should always be safe to remove after flushing the whole range */
 185         WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
 186         pgd_free(NULL, kvm->arch.gpa_mm.pgd);
 187 }
 188
 189 void kvm_arch_destroy_vm(struct kvm *kvm)
 190 {
 191         kvm_mips_free_vcpus(kvm);
 192         kvm_mips_free_gpa_pt(kvm);
 193 }
 194
 195 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
 196                         unsigned long arg)
 197 {
 198         return -ENOIOCTLCMD;
 199 }
 200
 201 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
 202                             unsigned long npages)
 203 {
 204         return 0;
 205 }
 206
 207 void kvm_arch_flush_shadow_all(struct kvm *kvm)
 208 {
 209         /* Flush whole GPA */
 210         kvm_mips_flush_gpa_pt(kvm, 0, ~0);
 211
 212         /* Let implementation do the rest */
 213         kvm_mips_callbacks->flush_shadow_all(kvm);
 214 }
 215
 216 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
 217                                    struct kvm_memory_slot *slot)
 218 {
 219         /*
 220          * The slot has been made invalid (ready for moving or deletion), so we
 221          * need to ensure that it can no longer be accessed by any guest VCPUs.
 222          */
 223
 224         spin_lock(&kvm->mmu_lock);
 225         /* Flush slot from GPA */
 226         kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
 227                               slot->base_gfn + slot->npages - 1);
 228         /* Let implementation do the rest */
 229         kvm_mips_callbacks->flush_shadow_memslot(kvm, slot);
 230         spin_unlock(&kvm->mmu_lock);
 231 }
 232
 233 int kvm_arch_prepare_memory_region(struct kvm *kvm,
 234                                    struct kvm_memory_slot *memslot,
 235                                    const struct kvm_userspace_memory_region *mem,
 236                                    enum kvm_mr_change change)
 237 {
 238         return 0;
 239 }
 240
 241 void kvm_arch_commit_memory_region(struct kvm *kvm,
 242                                    const struct kvm_userspace_memory_region *mem,
 243                                    const struct kvm_memory_slot *old,
 244                                    const struct kvm_memory_slot *new,
 245                                    enum kvm_mr_change change)
 246 {
 247         int needs_flush;
 248
 249         kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
 250                   __func__, kvm, mem->slot, mem->guest_phys_addr,
 251                   mem->memory_size, mem->userspace_addr);
 252
 253         /*
 254          * If dirty page logging is enabled, write protect all pages in the slot
 255          * ready for dirty logging.
 256          *
 257          * There is no need to do this in any of the following cases:
 258          * CREATE:      No dirty mappings will already exist.
 259          * MOVE/DELETE: The old mappings will already have been cleaned up by
 260          *              kvm_arch_flush_shadow_memslot()
 261          */
 262         if (change == KVM_MR_FLAGS_ONLY &&
 263             (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
 264              new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
 265                 spin_lock(&kvm->mmu_lock);
 266                 /* Write protect GPA page table entries */
 267                 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
 268                                         new->base_gfn + new->npages - 1);
 269                 /* Let implementation do the rest */
 270                 if (needs_flush)
 271                         kvm_mips_callbacks->flush_shadow_memslot(kvm, new);
 272                 spin_unlock(&kvm->mmu_lock);
 273         }
 274 }
 275
 276 static inline void dump_handler(const char *symbol, void *start, void *end)
 277 {
 278         u32 *p;
 279
 280         pr_debug("LEAF(%s)\n", symbol);
 281
 282         pr_debug("\t.set push\n");
 283         pr_debug("\t.set noreorder\n");
 284
 285         for (p = start; p < (u32 *)end; ++p)
 286                 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
 287
 288         pr_debug("\t.set\tpop\n");
 289
 290         pr_debug("\tEND(%s)\n", symbol);
 291 }
 292
 293 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
 294 {
 295         int err, size;
 296         void *gebase, *p, *handler, *refill_start, *refill_end;
 297         int i;
 298
 299         struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
 300
 301         if (!vcpu) {
 302                 err = -ENOMEM;
 303                 goto out;
 304         }
 305
 306         err = kvm_vcpu_init(vcpu, kvm, id);
 307
 308         if (err)
 309                 goto out_free_cpu;
 310
 311         kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
 312
 313         /*
 314          * Allocate space for host mode exception handlers that handle
 315          * guest mode exits
 316          */
 317         if (cpu_has_veic || cpu_has_vint)
 318                 size = 0x200 + VECTORSPACING * 64;
 319         else
 320                 size = 0x4000;
 321
 322         gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
 323
 324         if (!gebase) {
 325                 err = -ENOMEM;
 326                 goto out_uninit_cpu;
 327         }
 328         kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
 329                   ALIGN(size, PAGE_SIZE), gebase);
 330
 331         /*
 332          * Check new ebase actually fits in CP0_EBase. The lack of a write gate
 333          * limits us to the low 512MB of physical address space. If the memory
 334          * we allocate is out of range, just give up now.
 335          */
 336         if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
 337                 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
 338                         gebase);
 339                 err = -ENOMEM;
 340                 goto out_free_gebase;
 341         }
 342
 343         /* Save new ebase */
 344         vcpu->arch.guest_ebase = gebase;
 345
 346         /* Build guest exception vectors dynamically in unmapped memory */
 347         handler = gebase + 0x2000;
 348
 349         /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
 350         refill_start = gebase;
 351         if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT))
 352                 refill_start += 0x080;
 353         refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
 354
 355         /* General Exception Entry point */
 356         kvm_mips_build_exception(gebase + 0x180, handler);
 357
 358         /* For vectored interrupts poke the exception code @ all offsets 0-7 */
 359         for (i = 0; i < 8; i++) {
 360                 kvm_debug("L1 Vectored handler @ %p\n",
 361                           gebase + 0x200 + (i * VECTORSPACING));
 362                 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
 363                                          handler);
 364         }
 365
 366         /* General exit handler */
 367         p = handler;
 368         p = kvm_mips_build_exit(p);
 369
 370         /* Guest entry routine */
 371         vcpu->arch.vcpu_run = p;
 372         p = kvm_mips_build_vcpu_run(p);
 373
 374         /* Dump the generated code */
 375         pr_debug("#include <asm/asm.h>\n");
 376         pr_debug("#include <asm/regdef.h>\n");
 377         pr_debug("\n");
 378         dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
 379         dump_handler("kvm_tlb_refill", refill_start, refill_end);
 380         dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
 381         dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
 382
 383         /* Invalidate the icache for these ranges */
 384         flush_icache_range((unsigned long)gebase,
 385                            (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
 386
 387         /*
 388          * Allocate comm page for guest kernel, a TLB will be reserved for
 389          * mapping GVA @ 0xFFFF8000 to this page
 390          */
 391         vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
 392
 393         if (!vcpu->arch.kseg0_commpage) {
 394                 err = -ENOMEM;
 395                 goto out_free_gebase;
 396         }
 397
 398         kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
 399         kvm_mips_commpage_init(vcpu);
 400
 401         /* Init */
 402         vcpu->arch.last_sched_cpu = -1;
 403         vcpu->arch.last_exec_cpu = -1;
 404
 405         return vcpu;
 406
 407 out_free_gebase:
 408         kfree(gebase);
 409
 410 out_uninit_cpu:
 411         kvm_vcpu_uninit(vcpu);
 412
 413 out_free_cpu:
 414         kfree(vcpu);
 415
 416 out:
 417         return ERR_PTR(err);
 418 }
 419
 420 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
 421 {
 422         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 423
 424         kvm_vcpu_uninit(vcpu);
 425
 426         kvm_mips_dump_stats(vcpu);
 427
 428         kvm_mmu_free_memory_caches(vcpu);
 429         kfree(vcpu->arch.guest_ebase);
 430         kfree(vcpu->arch.kseg0_commpage);
 431         kfree(vcpu);
 432 }
 433
 434 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 435 {
 436         kvm_arch_vcpu_free(vcpu);
 437 }
 438
 439 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 440                                         struct kvm_guest_debug *dbg)
 441 {
 442         return -ENOIOCTLCMD;
 443 }
 444
 445 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 446 {
 447         int r = -EINTR;
 448
 449         kvm_sigset_activate(vcpu);
 450
 451         if (vcpu->mmio_needed) {
 452                 if (!vcpu->mmio_is_write)
 453                         kvm_mips_complete_mmio_load(vcpu, run);
 454                 vcpu->mmio_needed = 0;
 455         }
 456
 457         if (run->immediate_exit)
 458                 goto out;
 459
 460         lose_fpu(1);
 461
 462         local_irq_disable();
 463         guest_enter_irqoff();
 464         trace_kvm_enter(vcpu);
 465
 466         /*
 467          * Make sure the read of VCPU requests in vcpu_run() callback is not
 468          * reordered ahead of the write to vcpu->mode, or we could miss a TLB
 469          * flush request while the requester sees the VCPU as outside of guest
 470          * mode and not needing an IPI.
 471          */
 472         smp_store_mb(vcpu->mode, IN_GUEST_MODE);
 473
 474         r = kvm_mips_callbacks->vcpu_run(run, vcpu);
 475
 476         trace_kvm_out(vcpu);
 477         guest_exit_irqoff();
 478         local_irq_enable();
 479
 480 out:
 481         kvm_sigset_deactivate(vcpu);
 482
 483         return r;
 484 }
 485
 486 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 487                              struct kvm_mips_interrupt *irq)
 488 {
 489         int intr = (int)irq->irq;
 490         struct kvm_vcpu *dvcpu = NULL;
 491
 492         if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
 493                 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
 494                           (int)intr);
 495
 496         if (irq->cpu == -1)
 497                 dvcpu = vcpu;
 498         else
 499                 dvcpu = vcpu->kvm->vcpus[irq->cpu];
 500
 501         if (intr == 2 || intr == 3 || intr == 4) {
 502                 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
 503
 504         } else if (intr == -2 || intr == -3 || intr == -4) {
 505                 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
 506         } else {
 507                 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
 508                         irq->cpu, irq->irq);
 509                 return -EINVAL;
 510         }
 511
 512         dvcpu->arch.wait = 0;
 513
 514         if (swq_has_sleeper(&dvcpu->wq))
 515                 swake_up(&dvcpu->wq);
 516
 517         return 0;
 518 }
 519
 520 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 521                                     struct kvm_mp_state *mp_state)
 522 {
 523         return -ENOIOCTLCMD;
 524 }
 525
 526 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 527                                     struct kvm_mp_state *mp_state)
 528 {
 529         return -ENOIOCTLCMD;
 530 }
 531
 532 static u64 kvm_mips_get_one_regs[] = {
 533         KVM_REG_MIPS_R0,
 534         KVM_REG_MIPS_R1,
 535         KVM_REG_MIPS_R2,
 536         KVM_REG_MIPS_R3,
 537         KVM_REG_MIPS_R4,
 538         KVM_REG_MIPS_R5,
 539         KVM_REG_MIPS_R6,
 540         KVM_REG_MIPS_R7,
 541         KVM_REG_MIPS_R8,
 542         KVM_REG_MIPS_R9,
 543         KVM_REG_MIPS_R10,
 544         KVM_REG_MIPS_R11,
 545         KVM_REG_MIPS_R12,
 546         KVM_REG_MIPS_R13,
 547         KVM_REG_MIPS_R14,
 548         KVM_REG_MIPS_R15,
 549         KVM_REG_MIPS_R16,
 550         KVM_REG_MIPS_R17,
 551         KVM_REG_MIPS_R18,
 552         KVM_REG_MIPS_R19,
 553         KVM_REG_MIPS_R20,
 554         KVM_REG_MIPS_R21,
 555         KVM_REG_MIPS_R22,
 556         KVM_REG_MIPS_R23,
 557         KVM_REG_MIPS_R24,
 558         KVM_REG_MIPS_R25,
 559         KVM_REG_MIPS_R26,
 560         KVM_REG_MIPS_R27,
 561         KVM_REG_MIPS_R28,
 562         KVM_REG_MIPS_R29,
 563         KVM_REG_MIPS_R30,
 564         KVM_REG_MIPS_R31,
 565
 566 #ifndef CONFIG_CPU_MIPSR6
 567         KVM_REG_MIPS_HI,
 568         KVM_REG_MIPS_LO,
 569 #endif
 570         KVM_REG_MIPS_PC,
 571 };
 572
 573 static u64 kvm_mips_get_one_regs_fpu[] = {
 574         KVM_REG_MIPS_FCR_IR,
 575         KVM_REG_MIPS_FCR_CSR,
 576 };
 577
 578 static u64 kvm_mips_get_one_regs_msa[] = {
 579         KVM_REG_MIPS_MSA_IR,
 580         KVM_REG_MIPS_MSA_CSR,
 581 };
 582
 583 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
 584 {
 585         unsigned long ret;
 586
 587         ret = ARRAY_SIZE(kvm_mips_get_one_regs);
 588         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 589                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
 590                 /* odd doubles */
 591                 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
 592                         ret += 16;
 593         }
 594         if (kvm_mips_guest_can_have_msa(&vcpu->arch))
 595                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
 596         ret += kvm_mips_callbacks->num_regs(vcpu);
 597
 598         return ret;
 599 }
 600
 601 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
 602 {
 603         u64 index;
 604         unsigned int i;
 605
 606         if (copy_to_user(indices, kvm_mips_get_one_regs,
 607                          sizeof(kvm_mips_get_one_regs)))
 608                 return -EFAULT;
 609         indices += ARRAY_SIZE(kvm_mips_get_one_regs);
 610
 611         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 612                 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
 613                                  sizeof(kvm_mips_get_one_regs_fpu)))
 614                         return -EFAULT;
 615                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
 616
 617                 for (i = 0; i < 32; ++i) {
 618                         index = KVM_REG_MIPS_FPR_32(i);
 619                         if (copy_to_user(indices, &index, sizeof(index)))
 620                                 return -EFAULT;
 621                         ++indices;
 622
 623                         /* skip odd doubles if no F64 */
 624                         if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
 625                                 continue;
 626
 627                         index = KVM_REG_MIPS_FPR_64(i);
 628                         if (copy_to_user(indices, &index, sizeof(index)))
 629                                 return -EFAULT;
 630                         ++indices;
 631                 }
 632         }
 633
 634         if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
 635                 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
 636                                  sizeof(kvm_mips_get_one_regs_msa)))
 637                         return -EFAULT;
 638                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
 639
 640                 for (i = 0; i < 32; ++i) {
 641                         index = KVM_REG_MIPS_VEC_128(i);
 642                         if (copy_to_user(indices, &index, sizeof(index)))
 643                                 return -EFAULT;
 644                         ++indices;
 645                 }
 646         }
 647
 648         return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
 649 }
 650
 651 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
 652                             const struct kvm_one_reg *reg)
 653 {
 654         struct mips_coproc *cop0 = vcpu->arch.cop0;
 655         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 656         int ret;
 657         s64 v;
 658         s64 vs[2];
 659         unsigned int idx;
 660
 661         switch (reg->id) {
 662         /* General purpose registers */
 663         case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
 664                 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
 665                 break;
 666 #ifndef CONFIG_CPU_MIPSR6
 667         case KVM_REG_MIPS_HI:
 668                 v = (long)vcpu->arch.hi;
 669                 break;
 670         case KVM_REG_MIPS_LO:
 671                 v = (long)vcpu->arch.lo;
 672                 break;
 673 #endif
 674         case KVM_REG_MIPS_PC:
 675                 v = (long)vcpu->arch.pc;
 676                 break;
 677
 678         /* Floating point registers */
 679         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 680                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 681                         return -EINVAL;
 682                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 683                 /* Odd singles in top of even double when FR=0 */
 684                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 685                         v = get_fpr32(&fpu->fpr[idx], 0);
 686                 else
 687                         v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
 688                 break;
 689         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 690                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 691                         return -EINVAL;
 692                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 693                 /* Can't access odd doubles in FR=0 mode */
 694                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 695                         return -EINVAL;
 696                 v = get_fpr64(&fpu->fpr[idx], 0);
 697                 break;
 698         case KVM_REG_MIPS_FCR_IR:
 699                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 700                         return -EINVAL;
 701                 v = boot_cpu_data.fpu_id;
 702                 break;
 703         case KVM_REG_MIPS_FCR_CSR:
 704                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 705                         return -EINVAL;
 706                 v = fpu->fcr31;
 707                 break;
 708
 709         /* MIPS SIMD Architecture (MSA) registers */
 710         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 711                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 712                         return -EINVAL;
 713                 /* Can't access MSA registers in FR=0 mode */
 714                 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
 715                         return -EINVAL;
 716                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 717 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 718                 /* least significant byte first */
 719                 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
 720                 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
 721 #else
 722                 /* most significant byte first */
 723                 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
 724                 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
 725 #endif
 726                 break;
 727         case KVM_REG_MIPS_MSA_IR:
 728                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 729                         return -EINVAL;
 730                 v = boot_cpu_data.msa_id;
 731                 break;
 732         case KVM_REG_MIPS_MSA_CSR:
 733                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 734                         return -EINVAL;
 735                 v = fpu->msacsr;
 736                 break;
 737
 738         /* registers to be handled specially */
 739         default:
 740                 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
 741                 if (ret)
 742                         return ret;
 743                 break;
 744         }
 745         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 746                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 747
 748                 return put_user(v, uaddr64);
 749         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 750                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 751                 u32 v32 = (u32)v;
 752
 753                 return put_user(v32, uaddr32);
 754         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 755                 void __user *uaddr = (void __user *)(long)reg->addr;
 756
 757                 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
 758         } else {
 759                 return -EINVAL;
 760         }
 761 }
 762
 763 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
 764                             const struct kvm_one_reg *reg)
 765 {
 766         struct mips_coproc *cop0 = vcpu->arch.cop0;
 767         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 768         s64 v;
 769         s64 vs[2];
 770         unsigned int idx;
 771
 772         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 773                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 774
 775                 if (get_user(v, uaddr64) != 0)
 776                         return -EFAULT;
 777         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 778                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 779                 s32 v32;
 780
 781                 if (get_user(v32, uaddr32) != 0)
 782                         return -EFAULT;
 783                 v = (s64)v32;
 784         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 785                 void __user *uaddr = (void __user *)(long)reg->addr;
 786
 787                 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
 788         } else {
 789                 return -EINVAL;
 790         }
 791
 792         switch (reg->id) {
 793         /* General purpose registers */
 794         case KVM_REG_MIPS_R0:
 795                 /* Silently ignore requests to set $0 */
 796                 break;
 797         case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
 798                 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
 799                 break;
 800 #ifndef CONFIG_CPU_MIPSR6
 801         case KVM_REG_MIPS_HI:
 802                 vcpu->arch.hi = v;
 803                 break;
 804         case KVM_REG_MIPS_LO:
 805                 vcpu->arch.lo = v;
 806                 break;
 807 #endif
 808         case KVM_REG_MIPS_PC:
 809                 vcpu->arch.pc = v;
 810                 break;
 811
 812         /* Floating point registers */
 813         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 814                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 815                         return -EINVAL;
 816                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 817                 /* Odd singles in top of even double when FR=0 */
 818                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 819                         set_fpr32(&fpu->fpr[idx], 0, v);
 820                 else
 821                         set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
 822                 break;
 823         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 824                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 825                         return -EINVAL;
 826                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 827                 /* Can't access odd doubles in FR=0 mode */
 828                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 829                         return -EINVAL;
 830                 set_fpr64(&fpu->fpr[idx], 0, v);
 831                 break;
 832         case KVM_REG_MIPS_FCR_IR:
 833                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 834                         return -EINVAL;
 835                 /* Read-only */
 836                 break;
 837         case KVM_REG_MIPS_FCR_CSR:
 838                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 839                         return -EINVAL;
 840                 fpu->fcr31 = v;
 841                 break;
 842
 843         /* MIPS SIMD Architecture (MSA) registers */
 844         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 845                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 846                         return -EINVAL;
 847                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 848 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 849                 /* least significant byte first */
 850                 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
 851                 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
 852 #else
 853                 /* most significant byte first */
 854                 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
 855                 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
 856 #endif
 857                 break;
 858         case KVM_REG_MIPS_MSA_IR:
 859                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 860                         return -EINVAL;
 861                 /* Read-only */
 862                 break;
 863         case KVM_REG_MIPS_MSA_CSR:
 864                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 865                         return -EINVAL;
 866                 fpu->msacsr = v;
 867                 break;
 868
 869         /* registers to be handled specially */
 870         default:
 871                 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
 872         }
 873         return 0;
 874 }
 875
 876 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
 877                                      struct kvm_enable_cap *cap)
 878 {
 879         int r = 0;
 880
 881         if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
 882                 return -EINVAL;
 883         if (cap->flags)
 884                 return -EINVAL;
 885         if (cap->args[0])
 886                 return -EINVAL;
 887
 888         switch (cap->cap) {
 889         case KVM_CAP_MIPS_FPU:
 890                 vcpu->arch.fpu_enabled = true;
 891                 break;
 892         case KVM_CAP_MIPS_MSA:
 893                 vcpu->arch.msa_enabled = true;
 894                 break;
 895         default:
 896                 r = -EINVAL;
 897                 break;
 898         }
 899
 900         return r;
 901 }
 902
 903 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
 904                          unsigned long arg)
 905 {
 906         struct kvm_vcpu *vcpu = filp->private_data;
 907         void __user *argp = (void __user *)arg;
 908         long r;
 909
 910         switch (ioctl) {
 911         case KVM_SET_ONE_REG:
 912         case KVM_GET_ONE_REG: {
 913                 struct kvm_one_reg reg;
 914
 915                 if (copy_from_user(&reg, argp, sizeof(reg)))
 916                         return -EFAULT;
 917                 if (ioctl == KVM_SET_ONE_REG)
 918                         return kvm_mips_set_reg(vcpu, &reg);
 919                 else
 920                         return kvm_mips_get_reg(vcpu, &reg);
 921         }
 922         case KVM_GET_REG_LIST: {
 923                 struct kvm_reg_list __user *user_list = argp;
 924                 struct kvm_reg_list reg_list;
 925                 unsigned n;
 926
 927                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
 928                         return -EFAULT;
 929                 n = reg_list.n;
 930                 reg_list.n = kvm_mips_num_regs(vcpu);
 931                 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
 932                         return -EFAULT;
 933                 if (n < reg_list.n)
 934                         return -E2BIG;
 935                 return kvm_mips_copy_reg_indices(vcpu, user_list->reg);
 936         }
 937         case KVM_INTERRUPT:
 938                 {
 939                         struct kvm_mips_interrupt irq;
 940
 941                         if (copy_from_user(&irq, argp, sizeof(irq)))
 942                                 return -EFAULT;
 943                         kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
 944                                   irq.irq);
 945
 946                         r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
 947                         break;
 948                 }
 949         case KVM_ENABLE_CAP: {
 950                 struct kvm_enable_cap cap;
 951
 952                 if (copy_from_user(&cap, argp, sizeof(cap)))
 953                         return -EFAULT;
 954                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
 955                 break;
 956         }
 957         default:
 958                 r = -ENOIOCTLCMD;
 959         }
 960         return r;
 961 }
 962
 963 /**
 964  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
 965  * @kvm: kvm instance
 966  * @log: slot id and address to which we copy the log
 967  *
 968  * Steps 1-4 below provide general overview of dirty page logging. See
 969  * kvm_get_dirty_log_protect() function description for additional details.
 970  *
 971  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
 972  * always flush the TLB (step 4) even if previous step failed  and the dirty
 973  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
 974  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
 975  * writes will be marked dirty for next log read.
 976  *
 977  *   1. Take a snapshot of the bit and clear it if needed.
 978  *   2. Write protect the corresponding page.
 979  *   3. Copy the snapshot to the userspace.
 980  *   4. Flush TLB's if needed.
 981  */
 982 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
 983 {
 984         struct kvm_memslots *slots;
 985         struct kvm_memory_slot *memslot;
 986         bool is_dirty = false;
 987         int r;
 988
 989         mutex_lock(&kvm->slots_lock);
 990
 991         r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
 992
 993         if (is_dirty) {
 994                 slots = kvm_memslots(kvm);
 995                 memslot = id_to_memslot(slots, log->slot);
 996
 997                 /* Let implementation handle TLB/GVA invalidation */
 998                 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
 999         }
1000
1001         mutex_unlock(&kvm->slots_lock);
1002         return r;
1003 }
1004
1005 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1006 {
1007         long r;
1008
1009         switch (ioctl) {
1010         default:
1011                 r = -ENOIOCTLCMD;
1012         }
1013
1014         return r;
1015 }
1016
1017 int kvm_arch_init(void *opaque)
1018 {
1019         if (kvm_mips_callbacks) {
1020                 kvm_err("kvm: module already exists\n");
1021                 return -EEXIST;
1022         }
1023
1024         return kvm_mips_emulation_init(&kvm_mips_callbacks);
1025 }
1026
1027 void kvm_arch_exit(void)
1028 {
1029         kvm_mips_callbacks = NULL;
1030 }
1031
1032 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1033                                   struct kvm_sregs *sregs)
1034 {
1035         return -ENOIOCTLCMD;
1036 }
1037
1038 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1039                                   struct kvm_sregs *sregs)
1040 {
1041         return -ENOIOCTLCMD;
1042 }
1043
1044 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1045 {
1046 }
1047
1048 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1049 {
1050         return -ENOIOCTLCMD;
1051 }
1052
1053 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1054 {
1055         return -ENOIOCTLCMD;
1056 }
1057
1058 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1059 {
1060         return VM_FAULT_SIGBUS;
1061 }
1062
1063 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1064 {
1065         int r;
1066
1067         switch (ext) {
1068         case KVM_CAP_ONE_REG:
1069         case KVM_CAP_ENABLE_CAP:
1070         case KVM_CAP_READONLY_MEM:
1071         case KVM_CAP_SYNC_MMU:
1072         case KVM_CAP_IMMEDIATE_EXIT:
1073                 r = 1;
1074                 break;
1075         case KVM_CAP_NR_VCPUS:
1076                 r = num_online_cpus();
1077                 break;
1078         case KVM_CAP_MAX_VCPUS:
1079                 r = KVM_MAX_VCPUS;
1080                 break;
1081         case KVM_CAP_MIPS_FPU:
1082                 /* We don't handle systems with inconsistent cpu_has_fpu */
1083                 r = !!raw_cpu_has_fpu;
1084                 break;
1085         case KVM_CAP_MIPS_MSA:
1086                 /*
1087                  * We don't support MSA vector partitioning yet:
1088                  * 1) It would require explicit support which can't be tested
1089                  *    yet due to lack of support in current hardware.
1090                  * 2) It extends the state that would need to be saved/restored
1091                  *    by e.g. QEMU for migration.
1092                  *
1093                  * When vector partitioning hardware becomes available, support
1094                  * could be added by requiring a flag when enabling
1095                  * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1096                  * to save/restore the appropriate extra state.
1097                  */
1098                 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1099                 break;
1100         default:
1101                 r = kvm_mips_callbacks->check_extension(kvm, ext);
1102                 break;
1103         }
1104         return r;
1105 }
1106
1107 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1108 {
1109         return kvm_mips_pending_timer(vcpu) ||
1110                 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1111 }
1112
1113 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1114 {
1115         int i;
1116         struct mips_coproc *cop0;
1117
1118         if (!vcpu)
1119                 return -1;
1120
1121         kvm_debug("VCPU Register Dump:\n");
1122         kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1123         kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1124
1125         for (i = 0; i < 32; i += 4) {
1126                 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1127                        vcpu->arch.gprs[i],
1128                        vcpu->arch.gprs[i + 1],
1129                        vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1130         }
1131         kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1132         kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1133
1134         cop0 = vcpu->arch.cop0;
1135         kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1136                   kvm_read_c0_guest_status(cop0),
1137                   kvm_read_c0_guest_cause(cop0));
1138
1139         kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1140
1141         return 0;
1142 }
1143
1144 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1145 {
1146         int i;
1147
1148         for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1149                 vcpu->arch.gprs[i] = regs->gpr[i];
1150         vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1151         vcpu->arch.hi = regs->hi;
1152         vcpu->arch.lo = regs->lo;
1153         vcpu->arch.pc = regs->pc;
1154
1155         return 0;
1156 }
1157
1158 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1159 {
1160         int i;
1161
1162         for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1163                 regs->gpr[i] = vcpu->arch.gprs[i];
1164
1165         regs->hi = vcpu->arch.hi;
1166         regs->lo = vcpu->arch.lo;
1167         regs->pc = vcpu->arch.pc;
1168
1169         return 0;
1170 }
1171
1172 static void kvm_mips_comparecount_func(unsigned long data)
1173 {
1174         struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1175
1176         kvm_mips_callbacks->queue_timer_int(vcpu);
1177
1178         vcpu->arch.wait = 0;
1179         if (swq_has_sleeper(&vcpu->wq))
1180                 swake_up(&vcpu->wq);
1181 }
1182
1183 /* low level hrtimer wake routine */
1184 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1185 {
1186         struct kvm_vcpu *vcpu;
1187
1188         vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1189         kvm_mips_comparecount_func((unsigned long) vcpu);
1190         return kvm_mips_count_timeout(vcpu);
1191 }
1192
1193 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1194 {
1195         int err;
1196
1197         err = kvm_mips_callbacks->vcpu_init(vcpu);
1198         if (err)
1199                 return err;
1200
1201         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1202                      HRTIMER_MODE_REL);
1203         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1204         return 0;
1205 }
1206
1207 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
1208 {
1209         kvm_mips_callbacks->vcpu_uninit(vcpu);
1210 }
1211
1212 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1213                                   struct kvm_translation *tr)
1214 {
1215         return 0;
1216 }
1217
1218 /* Initial guest state */
1219 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1220 {
1221         return kvm_mips_callbacks->vcpu_setup(vcpu);
1222 }
1223
1224 static void kvm_mips_set_c0_status(void)
1225 {
1226         u32 status = read_c0_status();
1227
1228         if (cpu_has_dsp)
1229                 status |= (ST0_MX);
1230
1231         write_c0_status(status);
1232         ehb();
1233 }
1234
1235 /*
1236  * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1237  */
1238 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1239 {
1240         u32 cause = vcpu->arch.host_cp0_cause;
1241         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1242         u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1243         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1244         enum emulation_result er = EMULATE_DONE;
1245         u32 inst;
1246         int ret = RESUME_GUEST;
1247
1248         vcpu->mode = OUTSIDE_GUEST_MODE;
1249
1250         /* re-enable HTW before enabling interrupts */
1251         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1252                 htw_start();
1253
1254         /* Set a default exit reason */
1255         run->exit_reason = KVM_EXIT_UNKNOWN;
1256         run->ready_for_interrupt_injection = 1;
1257
1258         /*
1259          * Set the appropriate status bits based on host CPU features,
1260          * before we hit the scheduler
1261          */
1262         kvm_mips_set_c0_status();
1263
1264         local_irq_enable();
1265
1266         kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1267                         cause, opc, run, vcpu);
1268         trace_kvm_exit(vcpu, exccode);
1269
1270         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1271                 /*
1272                  * Do a privilege check, if in UM most of these exit conditions
1273                  * end up causing an exception to be delivered to the Guest
1274                  * Kernel
1275                  */
1276                 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1277                 if (er == EMULATE_PRIV_FAIL) {
1278                         goto skip_emul;
1279                 } else if (er == EMULATE_FAIL) {
1280                         run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1281                         ret = RESUME_HOST;
1282                         goto skip_emul;
1283                 }
1284         }
1285
1286         switch (exccode) {
1287         case EXCCODE_INT:
1288                 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1289
1290                 ++vcpu->stat.int_exits;
1291
1292                 if (need_resched())
1293                         cond_resched();
1294
1295                 ret = RESUME_GUEST;
1296                 break;
1297
1298         case EXCCODE_CPU:
1299                 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1300
1301                 ++vcpu->stat.cop_unusable_exits;
1302                 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1303                 /* XXXKYMA: Might need to return to user space */
1304                 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1305                         ret = RESUME_HOST;
1306                 break;
1307
1308         case EXCCODE_MOD:
1309                 ++vcpu->stat.tlbmod_exits;
1310                 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1311                 break;
1312
1313         case EXCCODE_TLBS:
1314                 kvm_debug("TLB ST fault:  cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1315                           cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1316                           badvaddr);
1317
1318                 ++vcpu->stat.tlbmiss_st_exits;
1319                 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1320                 break;
1321
1322         case EXCCODE_TLBL:
1323                 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1324                           cause, opc, badvaddr);
1325
1326                 ++vcpu->stat.tlbmiss_ld_exits;
1327                 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1328                 break;
1329
1330         case EXCCODE_ADES:
1331                 ++vcpu->stat.addrerr_st_exits;
1332                 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1333                 break;
1334
1335         case EXCCODE_ADEL:
1336                 ++vcpu->stat.addrerr_ld_exits;
1337                 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1338                 break;
1339
1340         case EXCCODE_SYS:
1341                 ++vcpu->stat.syscall_exits;
1342                 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1343                 break;
1344
1345         case EXCCODE_RI:
1346                 ++vcpu->stat.resvd_inst_exits;
1347                 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1348                 break;
1349
1350         case EXCCODE_BP:
1351                 ++vcpu->stat.break_inst_exits;
1352                 ret = kvm_mips_callbacks->handle_break(vcpu);
1353                 break;
1354
1355         case EXCCODE_TR:
1356                 ++vcpu->stat.trap_inst_exits;
1357                 ret = kvm_mips_callbacks->handle_trap(vcpu);
1358                 break;
1359
1360         case EXCCODE_MSAFPE:
1361                 ++vcpu->stat.msa_fpe_exits;
1362                 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1363                 break;
1364
1365         case EXCCODE_FPE:
1366                 ++vcpu->stat.fpe_exits;
1367                 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1368                 break;
1369
1370         case EXCCODE_MSADIS:
1371                 ++vcpu->stat.msa_disabled_exits;
1372                 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1373                 break;
1374
1375         case EXCCODE_GE:
1376                 /* defer exit accounting to handler */
1377                 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1378                 break;
1379
1380         default:
1381                 if (cause & CAUSEF_BD)
1382                         opc += 1;
1383                 inst = 0;
1384                 kvm_get_badinstr(opc, vcpu, &inst);
1385                 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x  BadVaddr: %#lx Status: %#x\n",
1386                         exccode, opc, inst, badvaddr,
1387                         kvm_read_c0_guest_status(vcpu->arch.cop0));
1388                 kvm_arch_vcpu_dump_regs(vcpu);
1389                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1390                 ret = RESUME_HOST;
1391                 break;
1392
1393         }
1394
1395 skip_emul:
1396         local_irq_disable();
1397
1398         if (ret == RESUME_GUEST)
1399                 kvm_vz_acquire_htimer(vcpu);
1400
1401         if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1402                 kvm_mips_deliver_interrupts(vcpu, cause);
1403
1404         if (!(ret & RESUME_HOST)) {
1405                 /* Only check for signals if not already exiting to userspace */
1406                 if (signal_pending(current)) {
1407                         run->exit_reason = KVM_EXIT_INTR;
1408                         ret = (-EINTR << 2) | RESUME_HOST;
1409                         ++vcpu->stat.signal_exits;
1410                         trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1411                 }
1412         }
1413
1414         if (ret == RESUME_GUEST) {
1415                 trace_kvm_reenter(vcpu);
1416
1417                 /*
1418                  * Make sure the read of VCPU requests in vcpu_reenter()
1419                  * callback is not reordered ahead of the write to vcpu->mode,
1420                  * or we could miss a TLB flush request while the requester sees
1421                  * the VCPU as outside of guest mode and not needing an IPI.
1422                  */
1423                 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1424
1425                 kvm_mips_callbacks->vcpu_reenter(run, vcpu);
1426
1427                 /*
1428                  * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1429                  * is live), restore FCR31 / MSACSR.
1430                  *
1431                  * This should be before returning to the guest exception
1432                  * vector, as it may well cause an [MSA] FP exception if there
1433                  * are pending exception bits unmasked. (see
1434                  * kvm_mips_csr_die_notifier() for how that is handled).
1435                  */
1436                 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1437                     read_c0_status() & ST0_CU1)
1438                         __kvm_restore_fcsr(&vcpu->arch);
1439
1440                 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1441                     read_c0_config5() & MIPS_CONF5_MSAEN)
1442                         __kvm_restore_msacsr(&vcpu->arch);
1443         }
1444
1445         /* Disable HTW before returning to guest or host */
1446         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1447                 htw_stop();
1448
1449         return ret;
1450 }
1451
1452 /* Enable FPU for guest and restore context */
1453 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1454 {
1455         struct mips_coproc *cop0 = vcpu->arch.cop0;
1456         unsigned int sr, cfg5;
1457
1458         preempt_disable();
1459
1460         sr = kvm_read_c0_guest_status(cop0);
1461
1462         /*
1463          * If MSA state is already live, it is undefined how it interacts with
1464          * FR=0 FPU state, and we don't want to hit reserved instruction
1465          * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1466          * play it safe and save it first.
1467          *
1468          * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1469          * get called when guest CU1 is set, however we can't trust the guest
1470          * not to clobber the status register directly via the commpage.
1471          */
1472         if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1473             vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1474                 kvm_lose_fpu(vcpu);
1475
1476         /*
1477          * Enable FPU for guest
1478          * We set FR and FRE according to guest context
1479          */
1480         change_c0_status(ST0_CU1 | ST0_FR, sr);
1481         if (cpu_has_fre) {
1482                 cfg5 = kvm_read_c0_guest_config5(cop0);
1483                 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1484         }
1485         enable_fpu_hazard();
1486
1487         /* If guest FPU state not active, restore it now */
1488         if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1489                 __kvm_restore_fpu(&vcpu->arch);
1490                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1491                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1492         } else {
1493                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1494         }
1495
1496         preempt_enable();
1497 }
1498
1499 #ifdef CONFIG_CPU_HAS_MSA
1500 /* Enable MSA for guest and restore context */
1501 void kvm_own_msa(struct kvm_vcpu *vcpu)
1502 {
1503         struct mips_coproc *cop0 = vcpu->arch.cop0;
1504         unsigned int sr, cfg5;
1505
1506         preempt_disable();
1507
1508         /*
1509          * Enable FPU if enabled in guest, since we're restoring FPU context
1510          * anyway. We set FR and FRE according to guest context.
1511          */
1512         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1513                 sr = kvm_read_c0_guest_status(cop0);
1514
1515                 /*
1516                  * If FR=0 FPU state is already live, it is undefined how it
1517                  * interacts with MSA state, so play it safe and save it first.
1518                  */
1519                 if (!(sr & ST0_FR) &&
1520                     (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1521                                 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1522                         kvm_lose_fpu(vcpu);
1523
1524                 change_c0_status(ST0_CU1 | ST0_FR, sr);
1525                 if (sr & ST0_CU1 && cpu_has_fre) {
1526                         cfg5 = kvm_read_c0_guest_config5(cop0);
1527                         change_c0_config5(MIPS_CONF5_FRE, cfg5);
1528                 }
1529         }
1530
1531         /* Enable MSA for guest */
1532         set_c0_config5(MIPS_CONF5_MSAEN);
1533         enable_fpu_hazard();
1534
1535         switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1536         case KVM_MIPS_AUX_FPU:
1537                 /*
1538                  * Guest FPU state already loaded, only restore upper MSA state
1539                  */
1540                 __kvm_restore_msa_upper(&vcpu->arch);
1541                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1542                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1543                 break;
1544         case 0:
1545                 /* Neither FPU or MSA already active, restore full MSA state */
1546                 __kvm_restore_msa(&vcpu->arch);
1547                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1548                 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1549                         vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1550                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1551                               KVM_TRACE_AUX_FPU_MSA);
1552                 break;
1553         default:
1554                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1555                 break;
1556         }
1557
1558         preempt_enable();
1559 }
1560 #endif
1561
1562 /* Drop FPU & MSA without saving it */
1563 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1564 {
1565         preempt_disable();
1566         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1567                 disable_msa();
1568                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1569                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1570         }
1571         if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1572                 clear_c0_status(ST0_CU1 | ST0_FR);
1573                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1574                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1575         }
1576         preempt_enable();
1577 }
1578
1579 /* Save and disable FPU & MSA */
1580 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1581 {
1582         /*
1583          * With T&E, FPU & MSA get disabled in root context (hardware) when it
1584          * is disabled in guest context (software), but the register state in
1585          * the hardware may still be in use.
1586          * This is why we explicitly re-enable the hardware before saving.
1587          */
1588
1589         preempt_disable();
1590         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1591                 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1592                         set_c0_config5(MIPS_CONF5_MSAEN);
1593                         enable_fpu_hazard();
1594                 }
1595
1596                 __kvm_save_msa(&vcpu->arch);
1597                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1598
1599                 /* Disable MSA & FPU */
1600                 disable_msa();
1601                 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1602                         clear_c0_status(ST0_CU1 | ST0_FR);
1603                         disable_fpu_hazard();
1604                 }
1605                 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1606         } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1607                 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1608                         set_c0_status(ST0_CU1);
1609                         enable_fpu_hazard();
1610                 }
1611
1612                 __kvm_save_fpu(&vcpu->arch);
1613                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1614                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1615
1616                 /* Disable FPU */
1617                 clear_c0_status(ST0_CU1 | ST0_FR);
1618                 disable_fpu_hazard();
1619         }
1620         preempt_enable();
1621 }
1622
1623 /*
1624  * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1625  * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1626  * exception if cause bits are set in the value being written.
1627  */
1628 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1629                                    unsigned long cmd, void *ptr)
1630 {
1631         struct die_args *args = (struct die_args *)ptr;
1632         struct pt_regs *regs = args->regs;
1633         unsigned long pc;
1634
1635         /* Only interested in FPE and MSAFPE */
1636         if (cmd != DIE_FP && cmd != DIE_MSAFP)
1637                 return NOTIFY_DONE;
1638
1639         /* Return immediately if guest context isn't active */
1640         if (!(current->flags & PF_VCPU))
1641                 return NOTIFY_DONE;
1642
1643         /* Should never get here from user mode */
1644         BUG_ON(user_mode(regs));
1645
1646         pc = instruction_pointer(regs);
1647         switch (cmd) {
1648         case DIE_FP:
1649                 /* match 2nd instruction in __kvm_restore_fcsr */
1650                 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1651                         return NOTIFY_DONE;
1652                 break;
1653         case DIE_MSAFP:
1654                 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1655                 if (!cpu_has_msa ||
1656                     pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1657                     pc > (unsigned long)&__kvm_restore_msacsr + 8)
1658                         return NOTIFY_DONE;
1659                 break;
1660         }
1661
1662         /* Move PC forward a little and continue executing */
1663         instruction_pointer(regs) += 4;
1664
1665         return NOTIFY_STOP;
1666 }
1667
1668 static struct notifier_block kvm_mips_csr_die_notifier = {
1669         .notifier_call = kvm_mips_csr_die_notify,
1670 };
1671
1672 static int __init kvm_mips_init(void)
1673 {
1674         int ret;
1675
1676         ret = kvm_mips_entry_setup();
1677         if (ret)
1678                 return ret;
1679
1680         ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1681
1682         if (ret)
1683                 return ret;
1684
1685         register_die_notifier(&kvm_mips_csr_die_notifier);
1686
1687         return 0;
1688 }
1689
1690 static void __exit kvm_mips_exit(void)
1691 {
1692         kvm_exit();
1693
1694         unregister_die_notifier(&kvm_mips_csr_die_notifier);
1695 }
1696
1697 module_init(kvm_mips_init);
1698 module_exit(kvm_mips_exit);
1699
1700 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);