arch/mips/kvm/mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/err.h>
  14 #include <linux/kdebug.h>
  15 #include <linux/module.h>
  16 #include <linux/vmalloc.h>
  17 #include <linux/fs.h>
  18 #include <linux/bootmem.h>
  19 #include <asm/fpu.h>
  20 #include <asm/page.h>
  21 #include <asm/cacheflush.h>
  22 #include <asm/mmu_context.h>
  23 #include <asm/pgtable.h>
  24
  25 #include <linux/kvm_host.h>
  26
  27 #include "interrupt.h"
  28 #include "commpage.h"
  29
  30 #define CREATE_TRACE_POINTS
  31 #include "trace.h"
  32
  33 #ifndef VECTORSPACING
  34 #define VECTORSPACING 0x100     /* for EI/VI mode */
  35 #endif
  36
  37 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
  38 struct kvm_stats_debugfs_item debugfs_entries[] = {
  39         { "wait",         VCPU_STAT(wait_exits),         KVM_STAT_VCPU },
  40         { "cache",        VCPU_STAT(cache_exits),        KVM_STAT_VCPU },
  41         { "signal",       VCPU_STAT(signal_exits),       KVM_STAT_VCPU },
  42         { "interrupt",    VCPU_STAT(int_exits),          KVM_STAT_VCPU },
  43         { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
  44         { "tlbmod",       VCPU_STAT(tlbmod_exits),       KVM_STAT_VCPU },
  45         { "tlbmiss_ld",   VCPU_STAT(tlbmiss_ld_exits),   KVM_STAT_VCPU },
  46         { "tlbmiss_st",   VCPU_STAT(tlbmiss_st_exits),   KVM_STAT_VCPU },
  47         { "addrerr_st",   VCPU_STAT(addrerr_st_exits),   KVM_STAT_VCPU },
  48         { "addrerr_ld",   VCPU_STAT(addrerr_ld_exits),   KVM_STAT_VCPU },
  49         { "syscall",      VCPU_STAT(syscall_exits),      KVM_STAT_VCPU },
  50         { "resvd_inst",   VCPU_STAT(resvd_inst_exits),   KVM_STAT_VCPU },
  51         { "break_inst",   VCPU_STAT(break_inst_exits),   KVM_STAT_VCPU },
  52         { "trap_inst",    VCPU_STAT(trap_inst_exits),    KVM_STAT_VCPU },
  53         { "msa_fpe",      VCPU_STAT(msa_fpe_exits),      KVM_STAT_VCPU },
  54         { "fpe",          VCPU_STAT(fpe_exits),          KVM_STAT_VCPU },
  55         { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
  56         { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
  57         { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
  58         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
  59         { "halt_wakeup",  VCPU_STAT(halt_wakeup),        KVM_STAT_VCPU },
  60         {NULL}
  61 };
  62
  63 static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
  64 {
  65         int i;
  66
  67         for_each_possible_cpu(i) {
  68                 vcpu->arch.guest_kernel_asid[i] = 0;
  69                 vcpu->arch.guest_user_asid[i] = 0;
  70         }
  71
  72         return 0;
  73 }
  74
  75 /*
  76  * XXXKYMA: We are simulatoring a processor that has the WII bit set in
  77  * Config7, so we are "runnable" if interrupts are pending
  78  */
  79 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
  80 {
  81         return !!(vcpu->arch.pending_exceptions);
  82 }
  83
  84 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
  85 {
  86         return 1;
  87 }
  88
  89 int kvm_arch_hardware_enable(void)
  90 {
  91         return 0;
  92 }
  93
  94 int kvm_arch_hardware_setup(void)
  95 {
  96         return 0;
  97 }
  98
  99 void kvm_arch_check_processor_compat(void *rtn)
 100 {
 101         *(int *)rtn = 0;
 102 }
 103
 104 static void kvm_mips_init_tlbs(struct kvm *kvm)
 105 {
 106         unsigned long wired;
 107
 108         /*
 109          * Add a wired entry to the TLB, it is used to map the commpage to
 110          * the Guest kernel
 111          */
 112         wired = read_c0_wired();
 113         write_c0_wired(wired + 1);
 114         mtc0_tlbw_hazard();
 115         kvm->arch.commpage_tlb = wired;
 116
 117         kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
 118                   kvm->arch.commpage_tlb);
 119 }
 120
 121 static void kvm_mips_init_vm_percpu(void *arg)
 122 {
 123         struct kvm *kvm = (struct kvm *)arg;
 124
 125         kvm_mips_init_tlbs(kvm);
 126         kvm_mips_callbacks->vm_init(kvm);
 127
 128 }
 129
 130 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 131 {
 132         if (atomic_inc_return(&kvm_mips_instance) == 1) {
 133                 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
 134                           __func__);
 135                 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
 136         }
 137
 138         return 0;
 139 }
 140
 141 void kvm_mips_free_vcpus(struct kvm *kvm)
 142 {
 143         unsigned int i;
 144         struct kvm_vcpu *vcpu;
 145
 146         /* Put the pages we reserved for the guest pmap */
 147         for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
 148                 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
 149                         kvm_mips_release_pfn_clean(kvm->arch.guest_pmap[i]);
 150         }
 151         kfree(kvm->arch.guest_pmap);
 152
 153         kvm_for_each_vcpu(i, vcpu, kvm) {
 154                 kvm_arch_vcpu_free(vcpu);
 155         }
 156
 157         mutex_lock(&kvm->lock);
 158
 159         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
 160                 kvm->vcpus[i] = NULL;
 161
 162         atomic_set(&kvm->online_vcpus, 0);
 163
 164         mutex_unlock(&kvm->lock);
 165 }
 166
 167 static void kvm_mips_uninit_tlbs(void *arg)
 168 {
 169         /* Restore wired count */
 170         write_c0_wired(0);
 171         mtc0_tlbw_hazard();
 172         /* Clear out all the TLBs */
 173         kvm_local_flush_tlb_all();
 174 }
 175
 176 void kvm_arch_destroy_vm(struct kvm *kvm)
 177 {
 178         kvm_mips_free_vcpus(kvm);
 179
 180         /* If this is the last instance, restore wired count */
 181         if (atomic_dec_return(&kvm_mips_instance) == 0) {
 182                 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
 183                           __func__);
 184                 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
 185         }
 186 }
 187
 188 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
 189                         unsigned long arg)
 190 {
 191         return -ENOIOCTLCMD;
 192 }
 193
 194 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
 195                             unsigned long npages)
 196 {
 197         return 0;
 198 }
 199
 200 int kvm_arch_prepare_memory_region(struct kvm *kvm,
 201                                    struct kvm_memory_slot *memslot,
 202                                    const struct kvm_userspace_memory_region *mem,
 203                                    enum kvm_mr_change change)
 204 {
 205         return 0;
 206 }
 207
 208 void kvm_arch_commit_memory_region(struct kvm *kvm,
 209                                    const struct kvm_userspace_memory_region *mem,
 210                                    const struct kvm_memory_slot *old,
 211                                    const struct kvm_memory_slot *new,
 212                                    enum kvm_mr_change change)
 213 {
 214         unsigned long npages = 0;
 215         int i;
 216
 217         kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
 218                   __func__, kvm, mem->slot, mem->guest_phys_addr,
 219                   mem->memory_size, mem->userspace_addr);
 220
 221         /* Setup Guest PMAP table */
 222         if (!kvm->arch.guest_pmap) {
 223                 if (mem->slot == 0)
 224                         npages = mem->memory_size >> PAGE_SHIFT;
 225
 226                 if (npages) {
 227                         kvm->arch.guest_pmap_npages = npages;
 228                         kvm->arch.guest_pmap =
 229                             kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
 230
 231                         if (!kvm->arch.guest_pmap) {
 232                                 kvm_err("Failed to allocate guest PMAP\n");
 233                                 return;
 234                         }
 235
 236                         kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
 237                                   npages, kvm->arch.guest_pmap);
 238
 239                         /* Now setup the page table */
 240                         for (i = 0; i < npages; i++)
 241                                 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
 242                 }
 243         }
 244 }
 245
 246 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
 247 {
 248         int err, size, offset;
 249         void *gebase;
 250         int i;
 251
 252         struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
 253
 254         if (!vcpu) {
 255                 err = -ENOMEM;
 256                 goto out;
 257         }
 258
 259         err = kvm_vcpu_init(vcpu, kvm, id);
 260
 261         if (err)
 262                 goto out_free_cpu;
 263
 264         kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
 265
 266         /*
 267          * Allocate space for host mode exception handlers that handle
 268          * guest mode exits
 269          */
 270         if (cpu_has_veic || cpu_has_vint)
 271                 size = 0x200 + VECTORSPACING * 64;
 272         else
 273                 size = 0x4000;
 274
 275         /* Save Linux EBASE */
 276         vcpu->arch.host_ebase = (void *)read_c0_ebase();
 277
 278         gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
 279
 280         if (!gebase) {
 281                 err = -ENOMEM;
 282                 goto out_uninit_cpu;
 283         }
 284         kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
 285                   ALIGN(size, PAGE_SIZE), gebase);
 286
 287         /* Save new ebase */
 288         vcpu->arch.guest_ebase = gebase;
 289
 290         /* Copy L1 Guest Exception handler to correct offset */
 291
 292         /* TLB Refill, EXL = 0 */
 293         memcpy(gebase, mips32_exception,
 294                mips32_exceptionEnd - mips32_exception);
 295
 296         /* General Exception Entry point */
 297         memcpy(gebase + 0x180, mips32_exception,
 298                mips32_exceptionEnd - mips32_exception);
 299
 300         /* For vectored interrupts poke the exception code @ all offsets 0-7 */
 301         for (i = 0; i < 8; i++) {
 302                 kvm_debug("L1 Vectored handler @ %p\n",
 303                           gebase + 0x200 + (i * VECTORSPACING));
 304                 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception,
 305                        mips32_exceptionEnd - mips32_exception);
 306         }
 307
 308         /* General handler, relocate to unmapped space for sanity's sake */
 309         offset = 0x2000;
 310         kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
 311                   gebase + offset,
 312                   mips32_GuestExceptionEnd - mips32_GuestException);
 313
 314         memcpy(gebase + offset, mips32_GuestException,
 315                mips32_GuestExceptionEnd - mips32_GuestException);
 316
 317         /* Invalidate the icache for these ranges */
 318         local_flush_icache_range((unsigned long)gebase,
 319                                 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
 320
 321         /*
 322          * Allocate comm page for guest kernel, a TLB will be reserved for
 323          * mapping GVA @ 0xFFFF8000 to this page
 324          */
 325         vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
 326
 327         if (!vcpu->arch.kseg0_commpage) {
 328                 err = -ENOMEM;
 329                 goto out_free_gebase;
 330         }
 331
 332         kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
 333         kvm_mips_commpage_init(vcpu);
 334
 335         /* Init */
 336         vcpu->arch.last_sched_cpu = -1;
 337
 338         /* Start off the timer */
 339         kvm_mips_init_count(vcpu);
 340
 341         return vcpu;
 342
 343 out_free_gebase:
 344         kfree(gebase);
 345
 346 out_uninit_cpu:
 347         kvm_vcpu_uninit(vcpu);
 348
 349 out_free_cpu:
 350         kfree(vcpu);
 351
 352 out:
 353         return ERR_PTR(err);
 354 }
 355
 356 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
 357 {
 358         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 359
 360         kvm_vcpu_uninit(vcpu);
 361
 362         kvm_mips_dump_stats(vcpu);
 363
 364         kfree(vcpu->arch.guest_ebase);
 365         kfree(vcpu->arch.kseg0_commpage);
 366         kfree(vcpu);
 367 }
 368
 369 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 370 {
 371         kvm_arch_vcpu_free(vcpu);
 372 }
 373
 374 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 375                                         struct kvm_guest_debug *dbg)
 376 {
 377         return -ENOIOCTLCMD;
 378 }
 379
 380 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 381 {
 382         int r = 0;
 383         sigset_t sigsaved;
 384
 385         if (vcpu->sigset_active)
 386                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
 387
 388         if (vcpu->mmio_needed) {
 389                 if (!vcpu->mmio_is_write)
 390                         kvm_mips_complete_mmio_load(vcpu, run);
 391                 vcpu->mmio_needed = 0;
 392         }
 393
 394         lose_fpu(1);
 395
 396         local_irq_disable();
 397         /* Check if we have any exceptions/interrupts pending */
 398         kvm_mips_deliver_interrupts(vcpu,
 399                                     kvm_read_c0_guest_cause(vcpu->arch.cop0));
 400
 401         __kvm_guest_enter();
 402
 403         /* Disable hardware page table walking while in guest */
 404         htw_stop();
 405
 406         r = __kvm_mips_vcpu_run(run, vcpu);
 407
 408         /* Re-enable HTW before enabling interrupts */
 409         htw_start();
 410
 411         __kvm_guest_exit();
 412         local_irq_enable();
 413
 414         if (vcpu->sigset_active)
 415                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
 416
 417         return r;
 418 }
 419
 420 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 421                              struct kvm_mips_interrupt *irq)
 422 {
 423         int intr = (int)irq->irq;
 424         struct kvm_vcpu *dvcpu = NULL;
 425
 426         if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
 427                 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
 428                           (int)intr);
 429
 430         if (irq->cpu == -1)
 431                 dvcpu = vcpu;
 432         else
 433                 dvcpu = vcpu->kvm->vcpus[irq->cpu];
 434
 435         if (intr == 2 || intr == 3 || intr == 4) {
 436                 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
 437
 438         } else if (intr == -2 || intr == -3 || intr == -4) {
 439                 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
 440         } else {
 441                 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
 442                         irq->cpu, irq->irq);
 443                 return -EINVAL;
 444         }
 445
 446         dvcpu->arch.wait = 0;
 447
 448         if (swait_active(&dvcpu->wq))
 449                 swake_up(&dvcpu->wq);
 450
 451         return 0;
 452 }
 453
 454 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 455                                     struct kvm_mp_state *mp_state)
 456 {
 457         return -ENOIOCTLCMD;
 458 }
 459
 460 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 461                                     struct kvm_mp_state *mp_state)
 462 {
 463         return -ENOIOCTLCMD;
 464 }
 465
 466 static u64 kvm_mips_get_one_regs[] = {
 467         KVM_REG_MIPS_R0,
 468         KVM_REG_MIPS_R1,
 469         KVM_REG_MIPS_R2,
 470         KVM_REG_MIPS_R3,
 471         KVM_REG_MIPS_R4,
 472         KVM_REG_MIPS_R5,
 473         KVM_REG_MIPS_R6,
 474         KVM_REG_MIPS_R7,
 475         KVM_REG_MIPS_R8,
 476         KVM_REG_MIPS_R9,
 477         KVM_REG_MIPS_R10,
 478         KVM_REG_MIPS_R11,
 479         KVM_REG_MIPS_R12,
 480         KVM_REG_MIPS_R13,
 481         KVM_REG_MIPS_R14,
 482         KVM_REG_MIPS_R15,
 483         KVM_REG_MIPS_R16,
 484         KVM_REG_MIPS_R17,
 485         KVM_REG_MIPS_R18,
 486         KVM_REG_MIPS_R19,
 487         KVM_REG_MIPS_R20,
 488         KVM_REG_MIPS_R21,
 489         KVM_REG_MIPS_R22,
 490         KVM_REG_MIPS_R23,
 491         KVM_REG_MIPS_R24,
 492         KVM_REG_MIPS_R25,
 493         KVM_REG_MIPS_R26,
 494         KVM_REG_MIPS_R27,
 495         KVM_REG_MIPS_R28,
 496         KVM_REG_MIPS_R29,
 497         KVM_REG_MIPS_R30,
 498         KVM_REG_MIPS_R31,
 499
 500         KVM_REG_MIPS_HI,
 501         KVM_REG_MIPS_LO,
 502         KVM_REG_MIPS_PC,
 503
 504         KVM_REG_MIPS_CP0_INDEX,
 505         KVM_REG_MIPS_CP0_CONTEXT,
 506         KVM_REG_MIPS_CP0_USERLOCAL,
 507         KVM_REG_MIPS_CP0_PAGEMASK,
 508         KVM_REG_MIPS_CP0_WIRED,
 509         KVM_REG_MIPS_CP0_HWRENA,
 510         KVM_REG_MIPS_CP0_BADVADDR,
 511         KVM_REG_MIPS_CP0_COUNT,
 512         KVM_REG_MIPS_CP0_ENTRYHI,
 513         KVM_REG_MIPS_CP0_COMPARE,
 514         KVM_REG_MIPS_CP0_STATUS,
 515         KVM_REG_MIPS_CP0_CAUSE,
 516         KVM_REG_MIPS_CP0_EPC,
 517         KVM_REG_MIPS_CP0_PRID,
 518         KVM_REG_MIPS_CP0_CONFIG,
 519         KVM_REG_MIPS_CP0_CONFIG1,
 520         KVM_REG_MIPS_CP0_CONFIG2,
 521         KVM_REG_MIPS_CP0_CONFIG3,
 522         KVM_REG_MIPS_CP0_CONFIG4,
 523         KVM_REG_MIPS_CP0_CONFIG5,
 524         KVM_REG_MIPS_CP0_CONFIG7,
 525         KVM_REG_MIPS_CP0_ERROREPC,
 526
 527         KVM_REG_MIPS_COUNT_CTL,
 528         KVM_REG_MIPS_COUNT_RESUME,
 529         KVM_REG_MIPS_COUNT_HZ,
 530 };
 531
 532 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
 533                             const struct kvm_one_reg *reg)
 534 {
 535         struct mips_coproc *cop0 = vcpu->arch.cop0;
 536         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 537         int ret;
 538         s64 v;
 539         s64 vs[2];
 540         unsigned int idx;
 541
 542         switch (reg->id) {
 543         /* General purpose registers */
 544         case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
 545                 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
 546                 break;
 547         case KVM_REG_MIPS_HI:
 548                 v = (long)vcpu->arch.hi;
 549                 break;
 550         case KVM_REG_MIPS_LO:
 551                 v = (long)vcpu->arch.lo;
 552                 break;
 553         case KVM_REG_MIPS_PC:
 554                 v = (long)vcpu->arch.pc;
 555                 break;
 556
 557         /* Floating point registers */
 558         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 559                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 560                         return -EINVAL;
 561                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 562                 /* Odd singles in top of even double when FR=0 */
 563                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 564                         v = get_fpr32(&fpu->fpr[idx], 0);
 565                 else
 566                         v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
 567                 break;
 568         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 569                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 570                         return -EINVAL;
 571                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 572                 /* Can't access odd doubles in FR=0 mode */
 573                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 574                         return -EINVAL;
 575                 v = get_fpr64(&fpu->fpr[idx], 0);
 576                 break;
 577         case KVM_REG_MIPS_FCR_IR:
 578                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 579                         return -EINVAL;
 580                 v = boot_cpu_data.fpu_id;
 581                 break;
 582         case KVM_REG_MIPS_FCR_CSR:
 583                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 584                         return -EINVAL;
 585                 v = fpu->fcr31;
 586                 break;
 587
 588         /* MIPS SIMD Architecture (MSA) registers */
 589         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 590                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 591                         return -EINVAL;
 592                 /* Can't access MSA registers in FR=0 mode */
 593                 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
 594                         return -EINVAL;
 595                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 596 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 597                 /* least significant byte first */
 598                 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
 599                 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
 600 #else
 601                 /* most significant byte first */
 602                 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
 603                 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
 604 #endif
 605                 break;
 606         case KVM_REG_MIPS_MSA_IR:
 607                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 608                         return -EINVAL;
 609                 v = boot_cpu_data.msa_id;
 610                 break;
 611         case KVM_REG_MIPS_MSA_CSR:
 612                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 613                         return -EINVAL;
 614                 v = fpu->msacsr;
 615                 break;
 616
 617         /* Co-processor 0 registers */
 618         case KVM_REG_MIPS_CP0_INDEX:
 619                 v = (long)kvm_read_c0_guest_index(cop0);
 620                 break;
 621         case KVM_REG_MIPS_CP0_CONTEXT:
 622                 v = (long)kvm_read_c0_guest_context(cop0);
 623                 break;
 624         case KVM_REG_MIPS_CP0_USERLOCAL:
 625                 v = (long)kvm_read_c0_guest_userlocal(cop0);
 626                 break;
 627         case KVM_REG_MIPS_CP0_PAGEMASK:
 628                 v = (long)kvm_read_c0_guest_pagemask(cop0);
 629                 break;
 630         case KVM_REG_MIPS_CP0_WIRED:
 631                 v = (long)kvm_read_c0_guest_wired(cop0);
 632                 break;
 633         case KVM_REG_MIPS_CP0_HWRENA:
 634                 v = (long)kvm_read_c0_guest_hwrena(cop0);
 635                 break;
 636         case KVM_REG_MIPS_CP0_BADVADDR:
 637                 v = (long)kvm_read_c0_guest_badvaddr(cop0);
 638                 break;
 639         case KVM_REG_MIPS_CP0_ENTRYHI:
 640                 v = (long)kvm_read_c0_guest_entryhi(cop0);
 641                 break;
 642         case KVM_REG_MIPS_CP0_COMPARE:
 643                 v = (long)kvm_read_c0_guest_compare(cop0);
 644                 break;
 645         case KVM_REG_MIPS_CP0_STATUS:
 646                 v = (long)kvm_read_c0_guest_status(cop0);
 647                 break;
 648         case KVM_REG_MIPS_CP0_CAUSE:
 649                 v = (long)kvm_read_c0_guest_cause(cop0);
 650                 break;
 651         case KVM_REG_MIPS_CP0_EPC:
 652                 v = (long)kvm_read_c0_guest_epc(cop0);
 653                 break;
 654         case KVM_REG_MIPS_CP0_PRID:
 655                 v = (long)kvm_read_c0_guest_prid(cop0);
 656                 break;
 657         case KVM_REG_MIPS_CP0_CONFIG:
 658                 v = (long)kvm_read_c0_guest_config(cop0);
 659                 break;
 660         case KVM_REG_MIPS_CP0_CONFIG1:
 661                 v = (long)kvm_read_c0_guest_config1(cop0);
 662                 break;
 663         case KVM_REG_MIPS_CP0_CONFIG2:
 664                 v = (long)kvm_read_c0_guest_config2(cop0);
 665                 break;
 666         case KVM_REG_MIPS_CP0_CONFIG3:
 667                 v = (long)kvm_read_c0_guest_config3(cop0);
 668                 break;
 669         case KVM_REG_MIPS_CP0_CONFIG4:
 670                 v = (long)kvm_read_c0_guest_config4(cop0);
 671                 break;
 672         case KVM_REG_MIPS_CP0_CONFIG5:
 673                 v = (long)kvm_read_c0_guest_config5(cop0);
 674                 break;
 675         case KVM_REG_MIPS_CP0_CONFIG7:
 676                 v = (long)kvm_read_c0_guest_config7(cop0);
 677                 break;
 678         case KVM_REG_MIPS_CP0_ERROREPC:
 679                 v = (long)kvm_read_c0_guest_errorepc(cop0);
 680                 break;
 681         /* registers to be handled specially */
 682         case KVM_REG_MIPS_CP0_COUNT:
 683         case KVM_REG_MIPS_COUNT_CTL:
 684         case KVM_REG_MIPS_COUNT_RESUME:
 685         case KVM_REG_MIPS_COUNT_HZ:
 686                 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
 687                 if (ret)
 688                         return ret;
 689                 break;
 690         default:
 691                 return -EINVAL;
 692         }
 693         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 694                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 695
 696                 return put_user(v, uaddr64);
 697         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 698                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 699                 u32 v32 = (u32)v;
 700
 701                 return put_user(v32, uaddr32);
 702         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 703                 void __user *uaddr = (void __user *)(long)reg->addr;
 704
 705                 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
 706         } else {
 707                 return -EINVAL;
 708         }
 709 }
 710
 711 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
 712                             const struct kvm_one_reg *reg)
 713 {
 714         struct mips_coproc *cop0 = vcpu->arch.cop0;
 715         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 716         s64 v;
 717         s64 vs[2];
 718         unsigned int idx;
 719
 720         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 721                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 722
 723                 if (get_user(v, uaddr64) != 0)
 724                         return -EFAULT;
 725         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 726                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 727                 s32 v32;
 728
 729                 if (get_user(v32, uaddr32) != 0)
 730                         return -EFAULT;
 731                 v = (s64)v32;
 732         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 733                 void __user *uaddr = (void __user *)(long)reg->addr;
 734
 735                 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
 736         } else {
 737                 return -EINVAL;
 738         }
 739
 740         switch (reg->id) {
 741         /* General purpose registers */
 742         case KVM_REG_MIPS_R0:
 743                 /* Silently ignore requests to set $0 */
 744                 break;
 745         case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
 746                 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
 747                 break;
 748         case KVM_REG_MIPS_HI:
 749                 vcpu->arch.hi = v;
 750                 break;
 751         case KVM_REG_MIPS_LO:
 752                 vcpu->arch.lo = v;
 753                 break;
 754         case KVM_REG_MIPS_PC:
 755                 vcpu->arch.pc = v;
 756                 break;
 757
 758         /* Floating point registers */
 759         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 760                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 761                         return -EINVAL;
 762                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 763                 /* Odd singles in top of even double when FR=0 */
 764                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 765                         set_fpr32(&fpu->fpr[idx], 0, v);
 766                 else
 767                         set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
 768                 break;
 769         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 770                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 771                         return -EINVAL;
 772                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 773                 /* Can't access odd doubles in FR=0 mode */
 774                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 775                         return -EINVAL;
 776                 set_fpr64(&fpu->fpr[idx], 0, v);
 777                 break;
 778         case KVM_REG_MIPS_FCR_IR:
 779                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 780                         return -EINVAL;
 781                 /* Read-only */
 782                 break;
 783         case KVM_REG_MIPS_FCR_CSR:
 784                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 785                         return -EINVAL;
 786                 fpu->fcr31 = v;
 787                 break;
 788
 789         /* MIPS SIMD Architecture (MSA) registers */
 790         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 791                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 792                         return -EINVAL;
 793                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 794 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 795                 /* least significant byte first */
 796                 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
 797                 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
 798 #else
 799                 /* most significant byte first */
 800                 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
 801                 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
 802 #endif
 803                 break;
 804         case KVM_REG_MIPS_MSA_IR:
 805                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 806                         return -EINVAL;
 807                 /* Read-only */
 808                 break;
 809         case KVM_REG_MIPS_MSA_CSR:
 810                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 811                         return -EINVAL;
 812                 fpu->msacsr = v;
 813                 break;
 814
 815         /* Co-processor 0 registers */
 816         case KVM_REG_MIPS_CP0_INDEX:
 817                 kvm_write_c0_guest_index(cop0, v);
 818                 break;
 819         case KVM_REG_MIPS_CP0_CONTEXT:
 820                 kvm_write_c0_guest_context(cop0, v);
 821                 break;
 822         case KVM_REG_MIPS_CP0_USERLOCAL:
 823                 kvm_write_c0_guest_userlocal(cop0, v);
 824                 break;
 825         case KVM_REG_MIPS_CP0_PAGEMASK:
 826                 kvm_write_c0_guest_pagemask(cop0, v);
 827                 break;
 828         case KVM_REG_MIPS_CP0_WIRED:
 829                 kvm_write_c0_guest_wired(cop0, v);
 830                 break;
 831         case KVM_REG_MIPS_CP0_HWRENA:
 832                 kvm_write_c0_guest_hwrena(cop0, v);
 833                 break;
 834         case KVM_REG_MIPS_CP0_BADVADDR:
 835                 kvm_write_c0_guest_badvaddr(cop0, v);
 836                 break;
 837         case KVM_REG_MIPS_CP0_ENTRYHI:
 838                 kvm_write_c0_guest_entryhi(cop0, v);
 839                 break;
 840         case KVM_REG_MIPS_CP0_STATUS:
 841                 kvm_write_c0_guest_status(cop0, v);
 842                 break;
 843         case KVM_REG_MIPS_CP0_EPC:
 844                 kvm_write_c0_guest_epc(cop0, v);
 845                 break;
 846         case KVM_REG_MIPS_CP0_PRID:
 847                 kvm_write_c0_guest_prid(cop0, v);
 848                 break;
 849         case KVM_REG_MIPS_CP0_ERROREPC:
 850                 kvm_write_c0_guest_errorepc(cop0, v);
 851                 break;
 852         /* registers to be handled specially */
 853         case KVM_REG_MIPS_CP0_COUNT:
 854         case KVM_REG_MIPS_CP0_COMPARE:
 855         case KVM_REG_MIPS_CP0_CAUSE:
 856         case KVM_REG_MIPS_CP0_CONFIG:
 857         case KVM_REG_MIPS_CP0_CONFIG1:
 858         case KVM_REG_MIPS_CP0_CONFIG2:
 859         case KVM_REG_MIPS_CP0_CONFIG3:
 860         case KVM_REG_MIPS_CP0_CONFIG4:
 861         case KVM_REG_MIPS_CP0_CONFIG5:
 862         case KVM_REG_MIPS_COUNT_CTL:
 863         case KVM_REG_MIPS_COUNT_RESUME:
 864         case KVM_REG_MIPS_COUNT_HZ:
 865                 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
 866         default:
 867                 return -EINVAL;
 868         }
 869         return 0;
 870 }
 871
 872 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
 873                                      struct kvm_enable_cap *cap)
 874 {
 875         int r = 0;
 876
 877         if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
 878                 return -EINVAL;
 879         if (cap->flags)
 880                 return -EINVAL;
 881         if (cap->args[0])
 882                 return -EINVAL;
 883
 884         switch (cap->cap) {
 885         case KVM_CAP_MIPS_FPU:
 886                 vcpu->arch.fpu_enabled = true;
 887                 break;
 888         case KVM_CAP_MIPS_MSA:
 889                 vcpu->arch.msa_enabled = true;
 890                 break;
 891         default:
 892                 r = -EINVAL;
 893                 break;
 894         }
 895
 896         return r;
 897 }
 898
 899 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
 900                          unsigned long arg)
 901 {
 902         struct kvm_vcpu *vcpu = filp->private_data;
 903         void __user *argp = (void __user *)arg;
 904         long r;
 905
 906         switch (ioctl) {
 907         case KVM_SET_ONE_REG:
 908         case KVM_GET_ONE_REG: {
 909                 struct kvm_one_reg reg;
 910
 911                 if (copy_from_user(&reg, argp, sizeof(reg)))
 912                         return -EFAULT;
 913                 if (ioctl == KVM_SET_ONE_REG)
 914                         return kvm_mips_set_reg(vcpu, &reg);
 915                 else
 916                         return kvm_mips_get_reg(vcpu, &reg);
 917         }
 918         case KVM_GET_REG_LIST: {
 919                 struct kvm_reg_list __user *user_list = argp;
 920                 u64 __user *reg_dest;
 921                 struct kvm_reg_list reg_list;
 922                 unsigned n;
 923
 924                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
 925                         return -EFAULT;
 926                 n = reg_list.n;
 927                 reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
 928                 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
 929                         return -EFAULT;
 930                 if (n < reg_list.n)
 931                         return -E2BIG;
 932                 reg_dest = user_list->reg;
 933                 if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
 934                                  sizeof(kvm_mips_get_one_regs)))
 935                         return -EFAULT;
 936                 return 0;
 937         }
 938         case KVM_NMI:
 939                 /* Treat the NMI as a CPU reset */
 940                 r = kvm_mips_reset_vcpu(vcpu);
 941                 break;
 942         case KVM_INTERRUPT:
 943                 {
 944                         struct kvm_mips_interrupt irq;
 945
 946                         r = -EFAULT;
 947                         if (copy_from_user(&irq, argp, sizeof(irq)))
 948                                 goto out;
 949
 950                         kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
 951                                   irq.irq);
 952
 953                         r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
 954                         break;
 955                 }
 956         case KVM_ENABLE_CAP: {
 957                 struct kvm_enable_cap cap;
 958
 959                 r = -EFAULT;
 960                 if (copy_from_user(&cap, argp, sizeof(cap)))
 961                         goto out;
 962                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
 963                 break;
 964         }
 965         default:
 966                 r = -ENOIOCTLCMD;
 967         }
 968
 969 out:
 970         return r;
 971 }
 972
 973 /* Get (and clear) the dirty memory log for a memory slot. */
 974 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
 975 {
 976         struct kvm_memslots *slots;
 977         struct kvm_memory_slot *memslot;
 978         unsigned long ga, ga_end;
 979         int is_dirty = 0;
 980         int r;
 981         unsigned long n;
 982
 983         mutex_lock(&kvm->slots_lock);
 984
 985         r = kvm_get_dirty_log(kvm, log, &is_dirty);
 986         if (r)
 987                 goto out;
 988
 989         /* If nothing is dirty, don't bother messing with page tables. */
 990         if (is_dirty) {
 991                 slots = kvm_memslots(kvm);
 992                 memslot = id_to_memslot(slots, log->slot);
 993
 994                 ga = memslot->base_gfn << PAGE_SHIFT;
 995                 ga_end = ga + (memslot->npages << PAGE_SHIFT);
 996
 997                 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
 998                          ga_end);
 999
1000                 n = kvm_dirty_bitmap_bytes(memslot);
1001                 memset(memslot->dirty_bitmap, 0, n);
1002         }
1003
1004         r = 0;
1005 out:
1006         mutex_unlock(&kvm->slots_lock);
1007         return r;
1008
1009 }
1010
1011 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1012 {
1013         long r;
1014
1015         switch (ioctl) {
1016         default:
1017                 r = -ENOIOCTLCMD;
1018         }
1019
1020         return r;
1021 }
1022
1023 int kvm_arch_init(void *opaque)
1024 {
1025         if (kvm_mips_callbacks) {
1026                 kvm_err("kvm: module already exists\n");
1027                 return -EEXIST;
1028         }
1029
1030         return kvm_mips_emulation_init(&kvm_mips_callbacks);
1031 }
1032
1033 void kvm_arch_exit(void)
1034 {
1035         kvm_mips_callbacks = NULL;
1036 }
1037
1038 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1039                                   struct kvm_sregs *sregs)
1040 {
1041         return -ENOIOCTLCMD;
1042 }
1043
1044 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1045                                   struct kvm_sregs *sregs)
1046 {
1047         return -ENOIOCTLCMD;
1048 }
1049
1050 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1051 {
1052 }
1053
1054 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1055 {
1056         return -ENOIOCTLCMD;
1057 }
1058
1059 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1060 {
1061         return -ENOIOCTLCMD;
1062 }
1063
1064 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1065 {
1066         return VM_FAULT_SIGBUS;
1067 }
1068
1069 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1070 {
1071         int r;
1072
1073         switch (ext) {
1074         case KVM_CAP_ONE_REG:
1075         case KVM_CAP_ENABLE_CAP:
1076                 r = 1;
1077                 break;
1078         case KVM_CAP_COALESCED_MMIO:
1079                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1080                 break;
1081         case KVM_CAP_MIPS_FPU:
1082                 /* We don't handle systems with inconsistent cpu_has_fpu */
1083                 r = !!raw_cpu_has_fpu;
1084                 break;
1085         case KVM_CAP_MIPS_MSA:
1086                 /*
1087                  * We don't support MSA vector partitioning yet:
1088                  * 1) It would require explicit support which can't be tested
1089                  *    yet due to lack of support in current hardware.
1090                  * 2) It extends the state that would need to be saved/restored
1091                  *    by e.g. QEMU for migration.
1092                  *
1093                  * When vector partitioning hardware becomes available, support
1094                  * could be added by requiring a flag when enabling
1095                  * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1096                  * to save/restore the appropriate extra state.
1097                  */
1098                 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1099                 break;
1100         default:
1101                 r = 0;
1102                 break;
1103         }
1104         return r;
1105 }
1106
1107 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1108 {
1109         return kvm_mips_pending_timer(vcpu);
1110 }
1111
1112 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1113 {
1114         int i;
1115         struct mips_coproc *cop0;
1116
1117         if (!vcpu)
1118                 return -1;
1119
1120         kvm_debug("VCPU Register Dump:\n");
1121         kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1122         kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1123
1124         for (i = 0; i < 32; i += 4) {
1125                 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1126                        vcpu->arch.gprs[i],
1127                        vcpu->arch.gprs[i + 1],
1128                        vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1129         }
1130         kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1131         kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1132
1133         cop0 = vcpu->arch.cop0;
1134         kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1135                   kvm_read_c0_guest_status(cop0),
1136                   kvm_read_c0_guest_cause(cop0));
1137
1138         kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1139
1140         return 0;
1141 }
1142
1143 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1144 {
1145         int i;
1146
1147         for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1148                 vcpu->arch.gprs[i] = regs->gpr[i];
1149         vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1150         vcpu->arch.hi = regs->hi;
1151         vcpu->arch.lo = regs->lo;
1152         vcpu->arch.pc = regs->pc;
1153
1154         return 0;
1155 }
1156
1157 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1158 {
1159         int i;
1160
1161         for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1162                 regs->gpr[i] = vcpu->arch.gprs[i];
1163
1164         regs->hi = vcpu->arch.hi;
1165         regs->lo = vcpu->arch.lo;
1166         regs->pc = vcpu->arch.pc;
1167
1168         return 0;
1169 }
1170
1171 static void kvm_mips_comparecount_func(unsigned long data)
1172 {
1173         struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1174
1175         kvm_mips_callbacks->queue_timer_int(vcpu);
1176
1177         vcpu->arch.wait = 0;
1178         if (swait_active(&vcpu->wq))
1179                 swake_up(&vcpu->wq);
1180 }
1181
1182 /* low level hrtimer wake routine */
1183 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1184 {
1185         struct kvm_vcpu *vcpu;
1186
1187         vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1188         kvm_mips_comparecount_func((unsigned long) vcpu);
1189         return kvm_mips_count_timeout(vcpu);
1190 }
1191
1192 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1193 {
1194         kvm_mips_callbacks->vcpu_init(vcpu);
1195         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1196                      HRTIMER_MODE_REL);
1197         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1198         return 0;
1199 }
1200
1201 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1202                                   struct kvm_translation *tr)
1203 {
1204         return 0;
1205 }
1206
1207 /* Initial guest state */
1208 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1209 {
1210         return kvm_mips_callbacks->vcpu_setup(vcpu);
1211 }
1212
1213 static void kvm_mips_set_c0_status(void)
1214 {
1215         uint32_t status = read_c0_status();
1216
1217         if (cpu_has_dsp)
1218                 status |= (ST0_MX);
1219
1220         write_c0_status(status);
1221         ehb();
1222 }
1223
1224 /*
1225  * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1226  */
1227 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1228 {
1229         uint32_t cause = vcpu->arch.host_cp0_cause;
1230         uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1231         uint32_t __user *opc = (uint32_t __user *) vcpu->arch.pc;
1232         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1233         enum emulation_result er = EMULATE_DONE;
1234         int ret = RESUME_GUEST;
1235
1236         /* re-enable HTW before enabling interrupts */
1237         htw_start();
1238
1239         /* Set a default exit reason */
1240         run->exit_reason = KVM_EXIT_UNKNOWN;
1241         run->ready_for_interrupt_injection = 1;
1242
1243         /*
1244          * Set the appropriate status bits based on host CPU features,
1245          * before we hit the scheduler
1246          */
1247         kvm_mips_set_c0_status();
1248
1249         local_irq_enable();
1250
1251         kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1252                         cause, opc, run, vcpu);
1253
1254         /*
1255          * Do a privilege check, if in UM most of these exit conditions end up
1256          * causing an exception to be delivered to the Guest Kernel
1257          */
1258         er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1259         if (er == EMULATE_PRIV_FAIL) {
1260                 goto skip_emul;
1261         } else if (er == EMULATE_FAIL) {
1262                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1263                 ret = RESUME_HOST;
1264                 goto skip_emul;
1265         }
1266
1267         switch (exccode) {
1268         case EXCCODE_INT:
1269                 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1270
1271                 ++vcpu->stat.int_exits;
1272                 trace_kvm_exit(vcpu, INT_EXITS);
1273
1274                 if (need_resched())
1275                         cond_resched();
1276
1277                 ret = RESUME_GUEST;
1278                 break;
1279
1280         case EXCCODE_CPU:
1281                 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1282
1283                 ++vcpu->stat.cop_unusable_exits;
1284                 trace_kvm_exit(vcpu, COP_UNUSABLE_EXITS);
1285                 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1286                 /* XXXKYMA: Might need to return to user space */
1287                 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1288                         ret = RESUME_HOST;
1289                 break;
1290
1291         case EXCCODE_MOD:
1292                 ++vcpu->stat.tlbmod_exits;
1293                 trace_kvm_exit(vcpu, TLBMOD_EXITS);
1294                 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1295                 break;
1296
1297         case EXCCODE_TLBS:
1298                 kvm_debug("TLB ST fault:  cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1299                           cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1300                           badvaddr);
1301
1302                 ++vcpu->stat.tlbmiss_st_exits;
1303                 trace_kvm_exit(vcpu, TLBMISS_ST_EXITS);
1304                 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1305                 break;
1306
1307         case EXCCODE_TLBL:
1308                 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1309                           cause, opc, badvaddr);
1310
1311                 ++vcpu->stat.tlbmiss_ld_exits;
1312                 trace_kvm_exit(vcpu, TLBMISS_LD_EXITS);
1313                 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1314                 break;
1315
1316         case EXCCODE_ADES:
1317                 ++vcpu->stat.addrerr_st_exits;
1318                 trace_kvm_exit(vcpu, ADDRERR_ST_EXITS);
1319                 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1320                 break;
1321
1322         case EXCCODE_ADEL:
1323                 ++vcpu->stat.addrerr_ld_exits;
1324                 trace_kvm_exit(vcpu, ADDRERR_LD_EXITS);
1325                 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1326                 break;
1327
1328         case EXCCODE_SYS:
1329                 ++vcpu->stat.syscall_exits;
1330                 trace_kvm_exit(vcpu, SYSCALL_EXITS);
1331                 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1332                 break;
1333
1334         case EXCCODE_RI:
1335                 ++vcpu->stat.resvd_inst_exits;
1336                 trace_kvm_exit(vcpu, RESVD_INST_EXITS);
1337                 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1338                 break;
1339
1340         case EXCCODE_BP:
1341                 ++vcpu->stat.break_inst_exits;
1342                 trace_kvm_exit(vcpu, BREAK_INST_EXITS);
1343                 ret = kvm_mips_callbacks->handle_break(vcpu);
1344                 break;
1345
1346         case EXCCODE_TR:
1347                 ++vcpu->stat.trap_inst_exits;
1348                 trace_kvm_exit(vcpu, TRAP_INST_EXITS);
1349                 ret = kvm_mips_callbacks->handle_trap(vcpu);
1350                 break;
1351
1352         case EXCCODE_MSAFPE:
1353                 ++vcpu->stat.msa_fpe_exits;
1354                 trace_kvm_exit(vcpu, MSA_FPE_EXITS);
1355                 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1356                 break;
1357
1358         case EXCCODE_FPE:
1359                 ++vcpu->stat.fpe_exits;
1360                 trace_kvm_exit(vcpu, FPE_EXITS);
1361                 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1362                 break;
1363
1364         case EXCCODE_MSADIS:
1365                 ++vcpu->stat.msa_disabled_exits;
1366                 trace_kvm_exit(vcpu, MSA_DISABLED_EXITS);
1367                 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1368                 break;
1369
1370         default:
1371                 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x  BadVaddr: %#lx Status: %#lx\n",
1372                         exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1373                         kvm_read_c0_guest_status(vcpu->arch.cop0));
1374                 kvm_arch_vcpu_dump_regs(vcpu);
1375                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1376                 ret = RESUME_HOST;
1377                 break;
1378
1379         }
1380
1381 skip_emul:
1382         local_irq_disable();
1383
1384         if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1385                 kvm_mips_deliver_interrupts(vcpu, cause);
1386
1387         if (!(ret & RESUME_HOST)) {
1388                 /* Only check for signals if not already exiting to userspace */
1389                 if (signal_pending(current)) {
1390                         run->exit_reason = KVM_EXIT_INTR;
1391                         ret = (-EINTR << 2) | RESUME_HOST;
1392                         ++vcpu->stat.signal_exits;
1393                         trace_kvm_exit(vcpu, SIGNAL_EXITS);
1394                 }
1395         }
1396
1397         if (ret == RESUME_GUEST) {
1398                 /*
1399                  * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1400                  * is live), restore FCR31 / MSACSR.
1401                  *
1402                  * This should be before returning to the guest exception
1403                  * vector, as it may well cause an [MSA] FP exception if there
1404                  * are pending exception bits unmasked. (see
1405                  * kvm_mips_csr_die_notifier() for how that is handled).
1406                  */
1407                 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1408                     read_c0_status() & ST0_CU1)
1409                         __kvm_restore_fcsr(&vcpu->arch);
1410
1411                 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1412                     read_c0_config5() & MIPS_CONF5_MSAEN)
1413                         __kvm_restore_msacsr(&vcpu->arch);
1414         }
1415
1416         /* Disable HTW before returning to guest or host */
1417         htw_stop();
1418
1419         return ret;
1420 }
1421
1422 /* Enable FPU for guest and restore context */
1423 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1424 {
1425         struct mips_coproc *cop0 = vcpu->arch.cop0;
1426         unsigned int sr, cfg5;
1427
1428         preempt_disable();
1429
1430         sr = kvm_read_c0_guest_status(cop0);
1431
1432         /*
1433          * If MSA state is already live, it is undefined how it interacts with
1434          * FR=0 FPU state, and we don't want to hit reserved instruction
1435          * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1436          * play it safe and save it first.
1437          *
1438          * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1439          * get called when guest CU1 is set, however we can't trust the guest
1440          * not to clobber the status register directly via the commpage.
1441          */
1442         if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1443             vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
1444                 kvm_lose_fpu(vcpu);
1445
1446         /*
1447          * Enable FPU for guest
1448          * We set FR and FRE according to guest context
1449          */
1450         change_c0_status(ST0_CU1 | ST0_FR, sr);
1451         if (cpu_has_fre) {
1452                 cfg5 = kvm_read_c0_guest_config5(cop0);
1453                 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1454         }
1455         enable_fpu_hazard();
1456
1457         /* If guest FPU state not active, restore it now */
1458         if (!(vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)) {
1459                 __kvm_restore_fpu(&vcpu->arch);
1460                 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1461         }
1462
1463         preempt_enable();
1464 }
1465
1466 #ifdef CONFIG_CPU_HAS_MSA
1467 /* Enable MSA for guest and restore context */
1468 void kvm_own_msa(struct kvm_vcpu *vcpu)
1469 {
1470         struct mips_coproc *cop0 = vcpu->arch.cop0;
1471         unsigned int sr, cfg5;
1472
1473         preempt_disable();
1474
1475         /*
1476          * Enable FPU if enabled in guest, since we're restoring FPU context
1477          * anyway. We set FR and FRE according to guest context.
1478          */
1479         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1480                 sr = kvm_read_c0_guest_status(cop0);
1481
1482                 /*
1483                  * If FR=0 FPU state is already live, it is undefined how it
1484                  * interacts with MSA state, so play it safe and save it first.
1485                  */
1486                 if (!(sr & ST0_FR) &&
1487                     (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU |
1488                                 KVM_MIPS_FPU_MSA)) == KVM_MIPS_FPU_FPU)
1489                         kvm_lose_fpu(vcpu);
1490
1491                 change_c0_status(ST0_CU1 | ST0_FR, sr);
1492                 if (sr & ST0_CU1 && cpu_has_fre) {
1493                         cfg5 = kvm_read_c0_guest_config5(cop0);
1494                         change_c0_config5(MIPS_CONF5_FRE, cfg5);
1495                 }
1496         }
1497
1498         /* Enable MSA for guest */
1499         set_c0_config5(MIPS_CONF5_MSAEN);
1500         enable_fpu_hazard();
1501
1502         switch (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA)) {
1503         case KVM_MIPS_FPU_FPU:
1504                 /*
1505                  * Guest FPU state already loaded, only restore upper MSA state
1506                  */
1507                 __kvm_restore_msa_upper(&vcpu->arch);
1508                 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
1509                 break;
1510         case 0:
1511                 /* Neither FPU or MSA already active, restore full MSA state */
1512                 __kvm_restore_msa(&vcpu->arch);
1513                 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
1514                 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1515                         vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1516                 break;
1517         default:
1518                 break;
1519         }
1520
1521         preempt_enable();
1522 }
1523 #endif
1524
1525 /* Drop FPU & MSA without saving it */
1526 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1527 {
1528         preempt_disable();
1529         if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
1530                 disable_msa();
1531                 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_MSA;
1532         }
1533         if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1534                 clear_c0_status(ST0_CU1 | ST0_FR);
1535                 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1536         }
1537         preempt_enable();
1538 }
1539
1540 /* Save and disable FPU & MSA */
1541 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1542 {
1543         /*
1544          * FPU & MSA get disabled in root context (hardware) when it is disabled
1545          * in guest context (software), but the register state in the hardware
1546          * may still be in use. This is why we explicitly re-enable the hardware
1547          * before saving.
1548          */
1549
1550         preempt_disable();
1551         if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
1552                 set_c0_config5(MIPS_CONF5_MSAEN);
1553                 enable_fpu_hazard();
1554
1555                 __kvm_save_msa(&vcpu->arch);
1556
1557                 /* Disable MSA & FPU */
1558                 disable_msa();
1559                 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
1560                         clear_c0_status(ST0_CU1 | ST0_FR);
1561                 vcpu->arch.fpu_inuse &= ~(KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA);
1562         } else if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1563                 set_c0_status(ST0_CU1);
1564                 enable_fpu_hazard();
1565
1566                 __kvm_save_fpu(&vcpu->arch);
1567                 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1568
1569                 /* Disable FPU */
1570                 clear_c0_status(ST0_CU1 | ST0_FR);
1571         }
1572         preempt_enable();
1573 }
1574
1575 /*
1576  * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1577  * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1578  * exception if cause bits are set in the value being written.
1579  */
1580 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1581                                    unsigned long cmd, void *ptr)
1582 {
1583         struct die_args *args = (struct die_args *)ptr;
1584         struct pt_regs *regs = args->regs;
1585         unsigned long pc;
1586
1587         /* Only interested in FPE and MSAFPE */
1588         if (cmd != DIE_FP && cmd != DIE_MSAFP)
1589                 return NOTIFY_DONE;
1590
1591         /* Return immediately if guest context isn't active */
1592         if (!(current->flags & PF_VCPU))
1593                 return NOTIFY_DONE;
1594
1595         /* Should never get here from user mode */
1596         BUG_ON(user_mode(regs));
1597
1598         pc = instruction_pointer(regs);
1599         switch (cmd) {
1600         case DIE_FP:
1601                 /* match 2nd instruction in __kvm_restore_fcsr */
1602                 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1603                         return NOTIFY_DONE;
1604                 break;
1605         case DIE_MSAFP:
1606                 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1607                 if (!cpu_has_msa ||
1608                     pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1609                     pc > (unsigned long)&__kvm_restore_msacsr + 8)
1610                         return NOTIFY_DONE;
1611                 break;
1612         }
1613
1614         /* Move PC forward a little and continue executing */
1615         instruction_pointer(regs) += 4;
1616
1617         return NOTIFY_STOP;
1618 }
1619
1620 static struct notifier_block kvm_mips_csr_die_notifier = {
1621         .notifier_call = kvm_mips_csr_die_notify,
1622 };
1623
1624 static int __init kvm_mips_init(void)
1625 {
1626         int ret;
1627
1628         ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1629
1630         if (ret)
1631                 return ret;
1632
1633         register_die_notifier(&kvm_mips_csr_die_notifier);
1634
1635         /*
1636          * On MIPS, kernel modules are executed from "mapped space", which
1637          * requires TLBs. The TLB handling code is statically linked with
1638          * the rest of the kernel (tlb.c) to avoid the possibility of
1639          * double faulting. The issue is that the TLB code references
1640          * routines that are part of the the KVM module, which are only
1641          * available once the module is loaded.
1642          */
1643         kvm_mips_gfn_to_pfn = gfn_to_pfn;
1644         kvm_mips_release_pfn_clean = kvm_release_pfn_clean;
1645         kvm_mips_is_error_pfn = is_error_pfn;
1646
1647         return 0;
1648 }
1649
1650 static void __exit kvm_mips_exit(void)
1651 {
1652         kvm_exit();
1653
1654         kvm_mips_gfn_to_pfn = NULL;
1655         kvm_mips_release_pfn_clean = NULL;
1656         kvm_mips_is_error_pfn = NULL;
1657
1658         unregister_die_notifier(&kvm_mips_csr_die_notifier);
1659 }
1660
1661 module_init(kvm_mips_init);
1662 module_exit(kvm_mips_exit);
1663
1664 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);