arch/mips/kernel/process.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others.
   7  * Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  * Copyright (C) 2004 Thiemo Seufer
  10  * Copyright (C) 2013  Imagination Technologies Ltd.
  11  */
  12 #include <linux/errno.h>
  13 #include <linux/sched.h>
  14 #include <linux/sched/debug.h>
  15 #include <linux/sched/task.h>
  16 #include <linux/sched/task_stack.h>
  17 #include <linux/tick.h>
  18 #include <linux/kernel.h>
  19 #include <linux/mm.h>
  20 #include <linux/stddef.h>
  21 #include <linux/unistd.h>
  22 #include <linux/export.h>
  23 #include <linux/ptrace.h>
  24 #include <linux/mman.h>
  25 #include <linux/personality.h>
  26 #include <linux/sys.h>
  27 #include <linux/init.h>
  28 #include <linux/completion.h>
  29 #include <linux/kallsyms.h>
  30 #include <linux/random.h>
  31 #include <linux/prctl.h>
  32 #include <linux/nmi.h>
  33 #include <linux/cpu.h>
  34
  35 #include <asm/asm.h>
  36 #include <asm/bootinfo.h>
  37 #include <asm/cpu.h>
  38 #include <asm/dsemul.h>
  39 #include <asm/dsp.h>
  40 #include <asm/fpu.h>
  41 #include <asm/irq.h>
  42 #include <asm/msa.h>
  43 #include <asm/pgtable.h>
  44 #include <asm/mipsregs.h>
  45 #include <asm/processor.h>
  46 #include <asm/reg.h>
  47 #include <linux/uaccess.h>
  48 #include <asm/io.h>
  49 #include <asm/elf.h>
  50 #include <asm/isadep.h>
  51 #include <asm/inst.h>
  52 #include <asm/stacktrace.h>
  53 #include <asm/irq_regs.h>
  54
  55 #ifdef CONFIG_HOTPLUG_CPU
  56 void arch_cpu_idle_dead(void)
  57 {
  58         play_dead();
  59 }
  60 #endif
  61
  62 asmlinkage void ret_from_fork(void);
  63 asmlinkage void ret_from_kernel_thread(void);
  64
  65 void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
  66 {
  67         unsigned long status;
  68
  69         /* New thread loses kernel privileges. */
  70         status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK);
  71         status |= KU_USER;
  72         regs->cp0_status = status;
  73         lose_fpu(0);
  74         clear_thread_flag(TIF_MSA_CTX_LIVE);
  75         clear_used_math();
  76         atomic_set(&current->thread.bd_emu_frame, BD_EMUFRAME_NONE);
  77         init_dsp();
  78         regs->cp0_epc = pc;
  79         regs->regs[29] = sp;
  80 }
  81
  82 void exit_thread(struct task_struct *tsk)
  83 {
  84         /*
  85          * User threads may have allocated a delay slot emulation frame.
  86          * If so, clean up that allocation.
  87          */
  88         if (!(current->flags & PF_KTHREAD))
  89                 dsemul_thread_cleanup(tsk);
  90 }
  91
  92 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  93 {
  94         /*
  95          * Save any process state which is live in hardware registers to the
  96          * parent context prior to duplication. This prevents the new child
  97          * state becoming stale if the parent is preempted before copy_thread()
  98          * gets a chance to save the parent's live hardware registers to the
  99          * child context.
 100          */
 101         preempt_disable();
 102
 103         if (is_msa_enabled())
 104                 save_msa(current);
 105         else if (is_fpu_owner())
 106                 _save_fp(current);
 107
 108         save_dsp(current);
 109
 110         preempt_enable();
 111
 112         *dst = *src;
 113         return 0;
 114 }
 115
 116 /*
 117  * Copy architecture-specific thread state
 118  */
 119 int copy_thread_tls(unsigned long clone_flags, unsigned long usp,
 120         unsigned long kthread_arg, struct task_struct *p, unsigned long tls)
 121 {
 122         struct thread_info *ti = task_thread_info(p);
 123         struct pt_regs *childregs, *regs = current_pt_regs();
 124         unsigned long childksp;
 125
 126         childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32;
 127
 128         /* set up new TSS. */
 129         childregs = (struct pt_regs *) childksp - 1;
 130         /*  Put the stack after the struct pt_regs.  */
 131         childksp = (unsigned long) childregs;
 132         p->thread.cp0_status = read_c0_status() & ~(ST0_CU2|ST0_CU1);
 133         if (unlikely(p->flags & PF_KTHREAD)) {
 134                 /* kernel thread */
 135                 unsigned long status = p->thread.cp0_status;
 136                 memset(childregs, 0, sizeof(struct pt_regs));
 137                 ti->addr_limit = KERNEL_DS;
 138                 p->thread.reg16 = usp; /* fn */
 139                 p->thread.reg17 = kthread_arg;
 140                 p->thread.reg29 = childksp;
 141                 p->thread.reg31 = (unsigned long) ret_from_kernel_thread;
 142 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 143                 status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) |
 144                          ((status & (ST0_KUC | ST0_IEC)) << 2);
 145 #else
 146                 status |= ST0_EXL;
 147 #endif
 148                 childregs->cp0_status = status;
 149                 return 0;
 150         }
 151
 152         /* user thread */
 153         *childregs = *regs;
 154         childregs->regs[7] = 0; /* Clear error flag */
 155         childregs->regs[2] = 0; /* Child gets zero as return value */
 156         if (usp)
 157                 childregs->regs[29] = usp;
 158         ti->addr_limit = USER_DS;
 159
 160         p->thread.reg29 = (unsigned long) childregs;
 161         p->thread.reg31 = (unsigned long) ret_from_fork;
 162
 163         /*
 164          * New tasks lose permission to use the fpu. This accelerates context
 165          * switching for most programs since they don't use the fpu.
 166          */
 167         childregs->cp0_status &= ~(ST0_CU2|ST0_CU1);
 168
 169         clear_tsk_thread_flag(p, TIF_USEDFPU);
 170         clear_tsk_thread_flag(p, TIF_USEDMSA);
 171         clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE);
 172
 173 #ifdef CONFIG_MIPS_MT_FPAFF
 174         clear_tsk_thread_flag(p, TIF_FPUBOUND);
 175 #endif /* CONFIG_MIPS_MT_FPAFF */
 176
 177         atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE);
 178
 179         if (clone_flags & CLONE_SETTLS)
 180                 ti->tp_value = tls;
 181
 182         return 0;
 183 }
 184
 185 #ifdef CONFIG_STACKPROTECTOR
 186 #include <linux/stackprotector.h>
 187 unsigned long __stack_chk_guard __read_mostly;
 188 EXPORT_SYMBOL(__stack_chk_guard);
 189 #endif
 190
 191 struct mips_frame_info {
 192         void            *func;
 193         unsigned long   func_size;
 194         int             frame_size;
 195         int             pc_offset;
 196 };
 197
 198 #define J_TARGET(pc,target)     \
 199                 (((unsigned long)(pc) & 0xf0000000) | ((target) << 2))
 200
 201 static inline int is_ra_save_ins(union mips_instruction *ip, int *poff)
 202 {
 203 #ifdef CONFIG_CPU_MICROMIPS
 204         /*
 205          * swsp ra,offset
 206          * swm16 reglist,offset(sp)
 207          * swm32 reglist,offset(sp)
 208          * sw32 ra,offset(sp)
 209          * jradiussp - NOT SUPPORTED
 210          *
 211          * microMIPS is way more fun...
 212          */
 213         if (mm_insn_16bit(ip->word >> 16)) {
 214                 switch (ip->mm16_r5_format.opcode) {
 215                 case mm_swsp16_op:
 216                         if (ip->mm16_r5_format.rt != 31)
 217                                 return 0;
 218
 219                         *poff = ip->mm16_r5_format.imm;
 220                         *poff = (*poff << 2) / sizeof(ulong);
 221                         return 1;
 222
 223                 case mm_pool16c_op:
 224                         switch (ip->mm16_m_format.func) {
 225                         case mm_swm16_op:
 226                                 *poff = ip->mm16_m_format.imm;
 227                                 *poff += 1 + ip->mm16_m_format.rlist;
 228                                 *poff = (*poff << 2) / sizeof(ulong);
 229                                 return 1;
 230
 231                         default:
 232                                 return 0;
 233                         }
 234
 235                 default:
 236                         return 0;
 237                 }
 238         }
 239
 240         switch (ip->i_format.opcode) {
 241         case mm_sw32_op:
 242                 if (ip->i_format.rs != 29)
 243                         return 0;
 244                 if (ip->i_format.rt != 31)
 245                         return 0;
 246
 247                 *poff = ip->i_format.simmediate / sizeof(ulong);
 248                 return 1;
 249
 250         case mm_pool32b_op:
 251                 switch (ip->mm_m_format.func) {
 252                 case mm_swm32_func:
 253                         if (ip->mm_m_format.rd < 0x10)
 254                                 return 0;
 255                         if (ip->mm_m_format.base != 29)
 256                                 return 0;
 257
 258                         *poff = ip->mm_m_format.simmediate;
 259                         *poff += (ip->mm_m_format.rd & 0xf) * sizeof(u32);
 260                         *poff /= sizeof(ulong);
 261                         return 1;
 262                 default:
 263                         return 0;
 264                 }
 265
 266         default:
 267                 return 0;
 268         }
 269 #else
 270         /* sw / sd $ra, offset($sp) */
 271         if ((ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) &&
 272                 ip->i_format.rs == 29 && ip->i_format.rt == 31) {
 273                 *poff = ip->i_format.simmediate / sizeof(ulong);
 274                 return 1;
 275         }
 276
 277         return 0;
 278 #endif
 279 }
 280
 281 static inline int is_jump_ins(union mips_instruction *ip)
 282 {
 283 #ifdef CONFIG_CPU_MICROMIPS
 284         /*
 285          * jr16,jrc,jalr16,jalr16
 286          * jal
 287          * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb
 288          * jraddiusp - NOT SUPPORTED
 289          *
 290          * microMIPS is kind of more fun...
 291          */
 292         if (mm_insn_16bit(ip->word >> 16)) {
 293                 if ((ip->mm16_r5_format.opcode == mm_pool16c_op &&
 294                     (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op))
 295                         return 1;
 296                 return 0;
 297         }
 298
 299         if (ip->j_format.opcode == mm_j32_op)
 300                 return 1;
 301         if (ip->j_format.opcode == mm_jal32_op)
 302                 return 1;
 303         if (ip->r_format.opcode != mm_pool32a_op ||
 304                         ip->r_format.func != mm_pool32axf_op)
 305                 return 0;
 306         return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op;
 307 #else
 308         if (ip->j_format.opcode == j_op)
 309                 return 1;
 310         if (ip->j_format.opcode == jal_op)
 311                 return 1;
 312         if (ip->r_format.opcode != spec_op)
 313                 return 0;
 314         return ip->r_format.func == jalr_op || ip->r_format.func == jr_op;
 315 #endif
 316 }
 317
 318 static inline int is_sp_move_ins(union mips_instruction *ip, int *frame_size)
 319 {
 320 #ifdef CONFIG_CPU_MICROMIPS
 321         unsigned short tmp;
 322
 323         /*
 324          * addiusp -imm
 325          * addius5 sp,-imm
 326          * addiu32 sp,sp,-imm
 327          * jradiussp - NOT SUPPORTED
 328          *
 329          * microMIPS is not more fun...
 330          */
 331         if (mm_insn_16bit(ip->word >> 16)) {
 332                 if (ip->mm16_r3_format.opcode == mm_pool16d_op &&
 333                     ip->mm16_r3_format.simmediate & mm_addiusp_func) {
 334                         tmp = ip->mm_b0_format.simmediate >> 1;
 335                         tmp = ((tmp & 0x1ff) ^ 0x100) - 0x100;
 336                         if ((tmp + 2) < 4) /* 0x0,0x1,0x1fe,0x1ff are special */
 337                                 tmp ^= 0x100;
 338                         *frame_size = -(signed short)(tmp << 2);
 339                         return 1;
 340                 }
 341                 if (ip->mm16_r5_format.opcode == mm_pool16d_op &&
 342                     ip->mm16_r5_format.rt == 29) {
 343                         tmp = ip->mm16_r5_format.imm >> 1;
 344                         *frame_size = -(signed short)(tmp & 0xf);
 345                         return 1;
 346                 }
 347                 return 0;
 348         }
 349
 350         if (ip->mm_i_format.opcode == mm_addiu32_op &&
 351             ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29) {
 352                 *frame_size = -ip->i_format.simmediate;
 353                 return 1;
 354         }
 355 #else
 356         /* addiu/daddiu sp,sp,-imm */
 357         if (ip->i_format.rs != 29 || ip->i_format.rt != 29)
 358                 return 0;
 359
 360         if (ip->i_format.opcode == addiu_op ||
 361             ip->i_format.opcode == daddiu_op) {
 362                 *frame_size = -ip->i_format.simmediate;
 363                 return 1;
 364         }
 365 #endif
 366         return 0;
 367 }
 368
 369 static int get_frame_info(struct mips_frame_info *info)
 370 {
 371         bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS);
 372         union mips_instruction insn, *ip, *ip_end;
 373         const unsigned int max_insns = 128;
 374         unsigned int last_insn_size = 0;
 375         unsigned int i;
 376         bool saw_jump = false;
 377
 378         info->pc_offset = -1;
 379         info->frame_size = 0;
 380
 381         ip = (void *)msk_isa16_mode((ulong)info->func);
 382         if (!ip)
 383                 goto err;
 384
 385         ip_end = (void *)ip + info->func_size;
 386
 387         for (i = 0; i < max_insns && ip < ip_end; i++) {
 388                 ip = (void *)ip + last_insn_size;
 389                 if (is_mmips && mm_insn_16bit(ip->halfword[0])) {
 390                         insn.word = ip->halfword[0] << 16;
 391                         last_insn_size = 2;
 392                 } else if (is_mmips) {
 393                         insn.word = ip->halfword[0] << 16 | ip->halfword[1];
 394                         last_insn_size = 4;
 395                 } else {
 396                         insn.word = ip->word;
 397                         last_insn_size = 4;
 398                 }
 399
 400                 if (!info->frame_size) {
 401                         is_sp_move_ins(&insn, &info->frame_size);
 402                         continue;
 403                 } else if (!saw_jump && is_jump_ins(ip)) {
 404                         /*
 405                          * If we see a jump instruction, we are finished
 406                          * with the frame save.
 407                          *
 408                          * Some functions can have a shortcut return at
 409                          * the beginning of the function, so don't start
 410                          * looking for jump instruction until we see the
 411                          * frame setup.
 412                          *
 413                          * The RA save instruction can get put into the
 414                          * delay slot of the jump instruction, so look
 415                          * at the next instruction, too.
 416                          */
 417                         saw_jump = true;
 418                         continue;
 419                 }
 420                 if (info->pc_offset == -1 &&
 421                     is_ra_save_ins(&insn, &info->pc_offset))
 422                         break;
 423                 if (saw_jump)
 424                         break;
 425         }
 426         if (info->frame_size && info->pc_offset >= 0) /* nested */
 427                 return 0;
 428         if (info->pc_offset < 0) /* leaf */
 429                 return 1;
 430         /* prologue seems bogus... */
 431 err:
 432         return -1;
 433 }
 434
 435 static struct mips_frame_info schedule_mfi __read_mostly;
 436
 437 #ifdef CONFIG_KALLSYMS
 438 static unsigned long get___schedule_addr(void)
 439 {
 440         return kallsyms_lookup_name("__schedule");
 441 }
 442 #else
 443 static unsigned long get___schedule_addr(void)
 444 {
 445         union mips_instruction *ip = (void *)schedule;
 446         int max_insns = 8;
 447         int i;
 448
 449         for (i = 0; i < max_insns; i++, ip++) {
 450                 if (ip->j_format.opcode == j_op)
 451                         return J_TARGET(ip, ip->j_format.target);
 452         }
 453         return 0;
 454 }
 455 #endif
 456
 457 static int __init frame_info_init(void)
 458 {
 459         unsigned long size = 0;
 460 #ifdef CONFIG_KALLSYMS
 461         unsigned long ofs;
 462 #endif
 463         unsigned long addr;
 464
 465         addr = get___schedule_addr();
 466         if (!addr)
 467                 addr = (unsigned long)schedule;
 468
 469 #ifdef CONFIG_KALLSYMS
 470         kallsyms_lookup_size_offset(addr, &size, &ofs);
 471 #endif
 472         schedule_mfi.func = (void *)addr;
 473         schedule_mfi.func_size = size;
 474
 475         get_frame_info(&schedule_mfi);
 476
 477         /*
 478          * Without schedule() frame info, result given by
 479          * thread_saved_pc() and get_wchan() are not reliable.
 480          */
 481         if (schedule_mfi.pc_offset < 0)
 482                 printk("Can't analyze schedule() prologue at %p\n", schedule);
 483
 484         return 0;
 485 }
 486
 487 arch_initcall(frame_info_init);
 488
 489 /*
 490  * Return saved PC of a blocked thread.
 491  */
 492 static unsigned long thread_saved_pc(struct task_struct *tsk)
 493 {
 494         struct thread_struct *t = &tsk->thread;
 495
 496         /* New born processes are a special case */
 497         if (t->reg31 == (unsigned long) ret_from_fork)
 498                 return t->reg31;
 499         if (schedule_mfi.pc_offset < 0)
 500                 return 0;
 501         return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset];
 502 }
 503
 504
 505 #ifdef CONFIG_KALLSYMS
 506 /* generic stack unwinding function */
 507 unsigned long notrace unwind_stack_by_address(unsigned long stack_page,
 508                                               unsigned long *sp,
 509                                               unsigned long pc,
 510                                               unsigned long *ra)
 511 {
 512         unsigned long low, high, irq_stack_high;
 513         struct mips_frame_info info;
 514         unsigned long size, ofs;
 515         struct pt_regs *regs;
 516         int leaf;
 517
 518         if (!stack_page)
 519                 return 0;
 520
 521         /*
 522          * IRQ stacks start at IRQ_STACK_START
 523          * task stacks at THREAD_SIZE - 32
 524          */
 525         low = stack_page;
 526         if (!preemptible() && on_irq_stack(raw_smp_processor_id(), *sp)) {
 527                 high = stack_page + IRQ_STACK_START;
 528                 irq_stack_high = high;
 529         } else {
 530                 high = stack_page + THREAD_SIZE - 32;
 531                 irq_stack_high = 0;
 532         }
 533
 534         /*
 535          * If we reached the top of the interrupt stack, start unwinding
 536          * the interrupted task stack.
 537          */
 538         if (unlikely(*sp == irq_stack_high)) {
 539                 unsigned long task_sp = *(unsigned long *)*sp;
 540
 541                 /*
 542                  * Check that the pointer saved in the IRQ stack head points to
 543                  * something within the stack of the current task
 544                  */
 545                 if (!object_is_on_stack((void *)task_sp))
 546                         return 0;
 547
 548                 /*
 549                  * Follow pointer to tasks kernel stack frame where interrupted
 550                  * state was saved.
 551                  */
 552                 regs = (struct pt_regs *)task_sp;
 553                 pc = regs->cp0_epc;
 554                 if (!user_mode(regs) && __kernel_text_address(pc)) {
 555                         *sp = regs->regs[29];
 556                         *ra = regs->regs[31];
 557                         return pc;
 558                 }
 559                 return 0;
 560         }
 561         if (!kallsyms_lookup_size_offset(pc, &size, &ofs))
 562                 return 0;
 563         /*
 564          * Return ra if an exception occurred at the first instruction
 565          */
 566         if (unlikely(ofs == 0)) {
 567                 pc = *ra;
 568                 *ra = 0;
 569                 return pc;
 570         }
 571
 572         info.func = (void *)(pc - ofs);
 573         info.func_size = ofs;   /* analyze from start to ofs */
 574         leaf = get_frame_info(&info);
 575         if (leaf < 0)
 576                 return 0;
 577
 578         if (*sp < low || *sp + info.frame_size > high)
 579                 return 0;
 580
 581         if (leaf)
 582                 /*
 583                  * For some extreme cases, get_frame_info() can
 584                  * consider wrongly a nested function as a leaf
 585                  * one. In that cases avoid to return always the
 586                  * same value.
 587                  */
 588                 pc = pc != *ra ? *ra : 0;
 589         else
 590                 pc = ((unsigned long *)(*sp))[info.pc_offset];
 591
 592         *sp += info.frame_size;
 593         *ra = 0;
 594         return __kernel_text_address(pc) ? pc : 0;
 595 }
 596 EXPORT_SYMBOL(unwind_stack_by_address);
 597
 598 /* used by show_backtrace() */
 599 unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
 600                            unsigned long pc, unsigned long *ra)
 601 {
 602         unsigned long stack_page = 0;
 603         int cpu;
 604
 605         for_each_possible_cpu(cpu) {
 606                 if (on_irq_stack(cpu, *sp)) {
 607                         stack_page = (unsigned long)irq_stack[cpu];
 608                         break;
 609                 }
 610         }
 611
 612         if (!stack_page)
 613                 stack_page = (unsigned long)task_stack_page(task);
 614
 615         return unwind_stack_by_address(stack_page, sp, pc, ra);
 616 }
 617 #endif
 618
 619 /*
 620  * get_wchan - a maintenance nightmare^W^Wpain in the ass ...
 621  */
 622 unsigned long get_wchan(struct task_struct *task)
 623 {
 624         unsigned long pc = 0;
 625 #ifdef CONFIG_KALLSYMS
 626         unsigned long sp;
 627         unsigned long ra = 0;
 628 #endif
 629
 630         if (!task || task == current || task->state == TASK_RUNNING)
 631                 goto out;
 632         if (!task_stack_page(task))
 633                 goto out;
 634
 635         pc = thread_saved_pc(task);
 636
 637 #ifdef CONFIG_KALLSYMS
 638         sp = task->thread.reg29 + schedule_mfi.frame_size;
 639
 640         while (in_sched_functions(pc))
 641                 pc = unwind_stack(task, &sp, pc, &ra);
 642 #endif
 643
 644 out:
 645         return pc;
 646 }
 647
 648 /*
 649  * Don't forget that the stack pointer must be aligned on a 8 bytes
 650  * boundary for 32-bits ABI and 16 bytes for 64-bits ABI.
 651  */
 652 unsigned long arch_align_stack(unsigned long sp)
 653 {
 654         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 655                 sp -= get_random_int() & ~PAGE_MASK;
 656
 657         return sp & ALMASK;
 658 }
 659
 660 static DEFINE_PER_CPU(call_single_data_t, backtrace_csd);
 661 static struct cpumask backtrace_csd_busy;
 662
 663 static void handle_backtrace(void *info)
 664 {
 665         nmi_cpu_backtrace(get_irq_regs());
 666         cpumask_clear_cpu(smp_processor_id(), &backtrace_csd_busy);
 667 }
 668
 669 static void raise_backtrace(cpumask_t *mask)
 670 {
 671         call_single_data_t *csd;
 672         int cpu;
 673
 674         for_each_cpu(cpu, mask) {
 675                 /*
 676                  * If we previously sent an IPI to the target CPU & it hasn't
 677                  * cleared its bit in the busy cpumask then it didn't handle
 678                  * our previous IPI & it's not safe for us to reuse the
 679                  * call_single_data_t.
 680                  */
 681                 if (cpumask_test_and_set_cpu(cpu, &backtrace_csd_busy)) {
 682                         pr_warn("Unable to send backtrace IPI to CPU%u - perhaps it hung?\n",
 683                                 cpu);
 684                         continue;
 685                 }
 686
 687                 csd = &per_cpu(backtrace_csd, cpu);
 688                 csd->func = handle_backtrace;
 689                 smp_call_function_single_async(cpu, csd);
 690         }
 691 }
 692
 693 void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
 694 {
 695         nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace);
 696 }
 697
 698 int mips_get_process_fp_mode(struct task_struct *task)
 699 {
 700         int value = 0;
 701
 702         if (!test_tsk_thread_flag(task, TIF_32BIT_FPREGS))
 703                 value |= PR_FP_MODE_FR;
 704         if (test_tsk_thread_flag(task, TIF_HYBRID_FPREGS))
 705                 value |= PR_FP_MODE_FRE;
 706
 707         return value;
 708 }
 709
 710 static long prepare_for_fp_mode_switch(void *unused)
 711 {
 712         /*
 713          * This is icky, but we use this to simply ensure that all CPUs have
 714          * context switched, regardless of whether they were previously running
 715          * kernel or user code. This ensures that no CPU currently has its FPU
 716          * enabled, or is about to attempt to enable it through any path other
 717          * than enable_restore_fp_context() which will wait appropriately for
 718          * fp_mode_switching to be zero.
 719          */
 720         return 0;
 721 }
 722
 723 int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
 724 {
 725         const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE;
 726         struct task_struct *t;
 727         struct cpumask process_cpus;
 728         int cpu;
 729
 730         /* If nothing to change, return right away, successfully.  */
 731         if (value == mips_get_process_fp_mode(task))
 732                 return 0;
 733
 734         /* Only accept a mode change if 64-bit FP enabled for o32.  */
 735         if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
 736                 return -EOPNOTSUPP;
 737
 738         /* And only for o32 tasks.  */
 739         if (IS_ENABLED(CONFIG_64BIT) && !test_thread_flag(TIF_32BIT_REGS))
 740                 return -EOPNOTSUPP;
 741
 742         /* Check the value is valid */
 743         if (value & ~known_bits)
 744                 return -EOPNOTSUPP;
 745
 746         /* Setting FRE without FR is not supported.  */
 747         if ((value & (PR_FP_MODE_FR | PR_FP_MODE_FRE)) == PR_FP_MODE_FRE)
 748                 return -EOPNOTSUPP;
 749
 750         /* Avoid inadvertently triggering emulation */
 751         if ((value & PR_FP_MODE_FR) && raw_cpu_has_fpu &&
 752             !(raw_current_cpu_data.fpu_id & MIPS_FPIR_F64))
 753                 return -EOPNOTSUPP;
 754         if ((value & PR_FP_MODE_FRE) && raw_cpu_has_fpu && !cpu_has_fre)
 755                 return -EOPNOTSUPP;
 756
 757         /* FR = 0 not supported in MIPS R6 */
 758         if (!(value & PR_FP_MODE_FR) && raw_cpu_has_fpu && cpu_has_mips_r6)
 759                 return -EOPNOTSUPP;
 760
 761         /* Indicate the new FP mode in each thread */
 762         for_each_thread(task, t) {
 763                 /* Update desired FP register width */
 764                 if (value & PR_FP_MODE_FR) {
 765                         clear_tsk_thread_flag(t, TIF_32BIT_FPREGS);
 766                 } else {
 767                         set_tsk_thread_flag(t, TIF_32BIT_FPREGS);
 768                         clear_tsk_thread_flag(t, TIF_MSA_CTX_LIVE);
 769                 }
 770
 771                 /* Update desired FP single layout */
 772                 if (value & PR_FP_MODE_FRE)
 773                         set_tsk_thread_flag(t, TIF_HYBRID_FPREGS);
 774                 else
 775                         clear_tsk_thread_flag(t, TIF_HYBRID_FPREGS);
 776         }
 777
 778         /*
 779          * We need to ensure that all threads in the process have switched mode
 780          * before returning, in order to allow userland to not worry about
 781          * races. We can do this by forcing all CPUs that any thread in the
 782          * process may be running on to schedule something else - in this case
 783          * prepare_for_fp_mode_switch().
 784          *
 785          * We begin by generating a mask of all CPUs that any thread in the
 786          * process may be running on.
 787          */
 788         cpumask_clear(&process_cpus);
 789         for_each_thread(task, t)
 790                 cpumask_set_cpu(task_cpu(t), &process_cpus);
 791
 792         /*
 793          * Now we schedule prepare_for_fp_mode_switch() on each of those CPUs.
 794          *
 795          * The CPUs may have rescheduled already since we switched mode or
 796          * generated the cpumask, but that doesn't matter. If the task in this
 797          * process is scheduled out then our scheduling
 798          * prepare_for_fp_mode_switch() will simply be redundant. If it's
 799          * scheduled in then it will already have picked up the new FP mode
 800          * whilst doing so.
 801          */
 802         get_online_cpus();
 803         for_each_cpu_and(cpu, &process_cpus, cpu_online_mask)
 804                 work_on_cpu(cpu, prepare_for_fp_mode_switch, NULL);
 805         put_online_cpus();
 806
 807         wake_up_var(&task->mm->context.fp_mode_switching);
 808
 809         return 0;
 810 }
 811
 812 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
 813 void mips_dump_regs32(u32 *uregs, const struct pt_regs *regs)
 814 {
 815         unsigned int i;
 816
 817         for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) {
 818                 /* k0/k1 are copied as zero. */
 819                 if (i == MIPS32_EF_R26 || i == MIPS32_EF_R27)
 820                         uregs[i] = 0;
 821                 else
 822                         uregs[i] = regs->regs[i - MIPS32_EF_R0];
 823         }
 824
 825         uregs[MIPS32_EF_LO] = regs->lo;
 826         uregs[MIPS32_EF_HI] = regs->hi;
 827         uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc;
 828         uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
 829         uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status;
 830         uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause;
 831 }
 832 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
 833
 834 #ifdef CONFIG_64BIT
 835 void mips_dump_regs64(u64 *uregs, const struct pt_regs *regs)
 836 {
 837         unsigned int i;
 838
 839         for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) {
 840                 /* k0/k1 are copied as zero. */
 841                 if (i == MIPS64_EF_R26 || i == MIPS64_EF_R27)
 842                         uregs[i] = 0;
 843                 else
 844                         uregs[i] = regs->regs[i - MIPS64_EF_R0];
 845         }
 846
 847         uregs[MIPS64_EF_LO] = regs->lo;
 848         uregs[MIPS64_EF_HI] = regs->hi;
 849         uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc;
 850         uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
 851         uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status;
 852         uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause;
 853 }
 854 #endif /* CONFIG_64BIT */