arch/mips/include/asm/octeon/cvmx-smix-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2012 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_SMIX_DEFS_H__
  29 #define __CVMX_SMIX_DEFS_H__
  30
  31 static inline uint64_t CVMX_SMIX_CLK(unsigned long offset)
  32 {
  33         switch (cvmx_get_octeon_family()) {
  34         case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
  35         case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
  36         case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
  37         case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
  38         case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
  39                 return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
  40         case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  41         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  42         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  43         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  44         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  45         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  46                 return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
  47         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  48                 return CVMX_ADD_IO_SEG(0x0001180000003818ull) + (offset) * 128;
  49         }
  50         return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
  51 }
  52
  53 static inline uint64_t CVMX_SMIX_CMD(unsigned long offset)
  54 {
  55         switch (cvmx_get_octeon_family()) {
  56         case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
  57         case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
  58         case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
  59         case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
  60         case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
  61                 return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
  62         case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  63         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  64         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  65         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  66         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  67         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  68                 return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
  69         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  70                 return CVMX_ADD_IO_SEG(0x0001180000003800ull) + (offset) * 128;
  71         }
  72         return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
  73 }
  74
  75 static inline uint64_t CVMX_SMIX_EN(unsigned long offset)
  76 {
  77         switch (cvmx_get_octeon_family()) {
  78         case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
  79         case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
  80         case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
  81         case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
  82         case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
  83                 return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
  84         case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  85         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  86         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  87         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  88         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  89         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  90                 return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
  91         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  92                 return CVMX_ADD_IO_SEG(0x0001180000003820ull) + (offset) * 128;
  93         }
  94         return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
  95 }
  96
  97 static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset)
  98 {
  99         switch (cvmx_get_octeon_family()) {
 100         case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
 101         case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
 102         case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
 103         case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
 104         case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
 105                 return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
 106         case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 107         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 108         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 109         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 110         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 111         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 112                 return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
 113         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 114                 return CVMX_ADD_IO_SEG(0x0001180000003810ull) + (offset) * 128;
 115         }
 116         return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
 117 }
 118
 119 static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset)
 120 {
 121         switch (cvmx_get_octeon_family()) {
 122         case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
 123         case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
 124         case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
 125         case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
 126         case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
 127                 return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
 128         case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 129         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 130         case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 131         case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 132         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 133         case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 134                 return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
 135         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 136                 return CVMX_ADD_IO_SEG(0x0001180000003808ull) + (offset) * 128;
 137         }
 138         return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
 139 }
 140
 141 union cvmx_smix_clk {
 142         uint64_t u64;
 143         struct cvmx_smix_clk_s {
 144 #ifdef __BIG_ENDIAN_BITFIELD
 145                 uint64_t reserved_25_63:39;
 146                 uint64_t mode:1;
 147                 uint64_t reserved_21_23:3;
 148                 uint64_t sample_hi:5;
 149                 uint64_t sample_mode:1;
 150                 uint64_t reserved_14_14:1;
 151                 uint64_t clk_idle:1;
 152                 uint64_t preamble:1;
 153                 uint64_t sample:4;
 154                 uint64_t phase:8;
 155 #else
 156                 uint64_t phase:8;
 157                 uint64_t sample:4;
 158                 uint64_t preamble:1;
 159                 uint64_t clk_idle:1;
 160                 uint64_t reserved_14_14:1;
 161                 uint64_t sample_mode:1;
 162                 uint64_t sample_hi:5;
 163                 uint64_t reserved_21_23:3;
 164                 uint64_t mode:1;
 165                 uint64_t reserved_25_63:39;
 166 #endif
 167         } s;
 168         struct cvmx_smix_clk_cn30xx {
 169 #ifdef __BIG_ENDIAN_BITFIELD
 170                 uint64_t reserved_21_63:43;
 171                 uint64_t sample_hi:5;
 172                 uint64_t sample_mode:1;
 173                 uint64_t reserved_14_14:1;
 174                 uint64_t clk_idle:1;
 175                 uint64_t preamble:1;
 176                 uint64_t sample:4;
 177                 uint64_t phase:8;
 178 #else
 179                 uint64_t phase:8;
 180                 uint64_t sample:4;
 181                 uint64_t preamble:1;
 182                 uint64_t clk_idle:1;
 183                 uint64_t reserved_14_14:1;
 184                 uint64_t sample_mode:1;
 185                 uint64_t sample_hi:5;
 186                 uint64_t reserved_21_63:43;
 187 #endif
 188         } cn30xx;
 189 };
 190
 191 union cvmx_smix_cmd {
 192         uint64_t u64;
 193         struct cvmx_smix_cmd_s {
 194 #ifdef __BIG_ENDIAN_BITFIELD
 195                 uint64_t reserved_18_63:46;
 196                 uint64_t phy_op:2;
 197                 uint64_t reserved_13_15:3;
 198                 uint64_t phy_adr:5;
 199                 uint64_t reserved_5_7:3;
 200                 uint64_t reg_adr:5;
 201 #else
 202                 uint64_t reg_adr:5;
 203                 uint64_t reserved_5_7:3;
 204                 uint64_t phy_adr:5;
 205                 uint64_t reserved_13_15:3;
 206                 uint64_t phy_op:2;
 207                 uint64_t reserved_18_63:46;
 208 #endif
 209         } s;
 210         struct cvmx_smix_cmd_cn30xx {
 211 #ifdef __BIG_ENDIAN_BITFIELD
 212                 uint64_t reserved_17_63:47;
 213                 uint64_t phy_op:1;
 214                 uint64_t reserved_13_15:3;
 215                 uint64_t phy_adr:5;
 216                 uint64_t reserved_5_7:3;
 217                 uint64_t reg_adr:5;
 218 #else
 219                 uint64_t reg_adr:5;
 220                 uint64_t reserved_5_7:3;
 221                 uint64_t phy_adr:5;
 222                 uint64_t reserved_13_15:3;
 223                 uint64_t phy_op:1;
 224                 uint64_t reserved_17_63:47;
 225 #endif
 226         } cn30xx;
 227 };
 228
 229 union cvmx_smix_en {
 230         uint64_t u64;
 231         struct cvmx_smix_en_s {
 232 #ifdef __BIG_ENDIAN_BITFIELD
 233                 uint64_t reserved_1_63:63;
 234                 uint64_t en:1;
 235 #else
 236                 uint64_t en:1;
 237                 uint64_t reserved_1_63:63;
 238 #endif
 239         } s;
 240 };
 241
 242 union cvmx_smix_rd_dat {
 243         uint64_t u64;
 244         struct cvmx_smix_rd_dat_s {
 245 #ifdef __BIG_ENDIAN_BITFIELD
 246                 uint64_t reserved_18_63:46;
 247                 uint64_t pending:1;
 248                 uint64_t val:1;
 249                 uint64_t dat:16;
 250 #else
 251                 uint64_t dat:16;
 252                 uint64_t val:1;
 253                 uint64_t pending:1;
 254                 uint64_t reserved_18_63:46;
 255 #endif
 256         } s;
 257 };
 258
 259 union cvmx_smix_wr_dat {
 260         uint64_t u64;
 261         struct cvmx_smix_wr_dat_s {
 262 #ifdef __BIG_ENDIAN_BITFIELD
 263                 uint64_t reserved_18_63:46;
 264                 uint64_t pending:1;
 265                 uint64_t val:1;
 266                 uint64_t dat:16;
 267 #else
 268                 uint64_t dat:16;
 269                 uint64_t val:1;
 270                 uint64_t pending:1;
 271                 uint64_t reserved_18_63:46;
 272 #endif
 273         } s;
 274 };
 275
 276 #endif