2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (c) 2006 Ralf Baechle (ralf@linux-mips.org)
13 #include <linux/futex.h>
14 #include <linux/uaccess.h>
15 #include <asm/asm-eva.h>
16 #include <asm/barrier.h>
17 #include <asm/compiler.h>
18 #include <asm/errno.h>
21 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
23 if (cpu_has_llsc && R10000_LLSC_WAR) { \
24 __asm__ __volatile__( \
28 " .set arch=r4000 \n" \
29 "1: ll %1, %4 # __futex_atomic_op \n" \
32 " .set arch=r4000 \n" \
39 " .section .fixup,\"ax\" \n" \
43 " .section __ex_table,\"a\" \n" \
44 " "__UA_ADDR "\t1b, 4b \n" \
45 " "__UA_ADDR "\t2b, 4b \n" \
47 : "=r" (ret), "=&r" (oldval), \
48 "=" GCC_OFF_SMALL_ASM() (*uaddr) \
49 : "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
52 } else if (cpu_has_llsc) { \
53 __asm__ __volatile__( \
57 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
58 "1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \
61 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
62 "2: "user_sc("$1", "%2")" \n" \
68 " .section .fixup,\"ax\" \n" \
72 " .section __ex_table,\"a\" \n" \
73 " "__UA_ADDR "\t1b, 4b \n" \
74 " "__UA_ADDR "\t2b, 4b \n" \
76 : "=r" (ret), "=&r" (oldval), \
77 "=" GCC_OFF_SMALL_ASM() (*uaddr) \
78 : "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
86 arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
94 __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
98 __futex_atomic_op("addu $1, %1, %z5",
99 ret, oldval, uaddr, oparg);
102 __futex_atomic_op("or $1, %1, %z5",
103 ret, oldval, uaddr, oparg);
106 __futex_atomic_op("and $1, %1, %z5",
107 ret, oldval, uaddr, ~oparg);
110 __futex_atomic_op("xor $1, %1, %z5",
111 ret, oldval, uaddr, oparg);
126 futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
127 u32 oldval, u32 newval)
132 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
135 if (cpu_has_llsc && R10000_LLSC_WAR) {
136 __asm__ __volatile__(
137 "# futex_atomic_cmpxchg_inatomic \n"
141 " .set arch=r4000 \n"
143 " bne %1, %z4, 3f \n"
146 " .set arch=r4000 \n"
153 " .section .fixup,\"ax\" \n"
157 " .section __ex_table,\"a\" \n"
158 " "__UA_ADDR "\t1b, 4b \n"
159 " "__UA_ADDR "\t2b, 4b \n"
161 : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
162 : GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
165 } else if (cpu_has_llsc) {
166 __asm__ __volatile__(
167 "# futex_atomic_cmpxchg_inatomic \n"
171 " .set "MIPS_ISA_ARCH_LEVEL" \n"
172 "1: "user_ll("%1", "%3")" \n"
173 " bne %1, %z4, 3f \n"
176 " .set "MIPS_ISA_ARCH_LEVEL" \n"
177 "2: "user_sc("$1", "%2")" \n"
183 " .section .fixup,\"ax\" \n"
187 " .section __ex_table,\"a\" \n"
188 " "__UA_ADDR "\t1b, 4b \n"
189 " "__UA_ADDR "\t2b, 4b \n"
191 : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
192 : GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
203 #endif /* _ASM_FUTEX_H */