2 * Atomic operations that C can't guarantee us. Useful for
3 * resource counting etc..
5 * But use these as seldom as possible since they are much more slower
6 * than regular operations.
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 * Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle
17 #include <linux/irqflags.h>
18 #include <linux/types.h>
19 #include <asm/barrier.h>
20 #include <asm/compiler.h>
21 #include <asm/cpu-features.h>
22 #include <asm/cmpxchg.h>
26 * Using a branch-likely instruction to check the result of an sc instruction
27 * works around a bug present in R10000 CPUs prior to revision 3.0 that could
28 * cause ll-sc sequences to execute non-atomically.
31 # define __scbeqz "beqzl"
33 # define __scbeqz "beqz"
36 #define ATOMIC_INIT(i) { (i) }
39 * atomic_read - read atomic variable
40 * @v: pointer of type atomic_t
42 * Atomically reads the value of @v.
44 #define atomic_read(v) READ_ONCE((v)->counter)
47 * atomic_set - set atomic variable
48 * @v: pointer of type atomic_t
51 * Atomically sets the value of @v to @i.
53 #define atomic_set(v, i) WRITE_ONCE((v)->counter, (i))
55 #define ATOMIC_OP(op, c_op, asm_op) \
56 static __inline__ void atomic_##op(int i, atomic_t * v) \
58 if (kernel_uses_llsc) { \
61 __asm__ __volatile__( \
62 " .set "MIPS_ISA_LEVEL" \n" \
63 "1: ll %0, %1 # atomic_" #op " \n" \
64 " " #asm_op " %0, %2 \n" \
66 "\t" __scbeqz " %0, 1b \n" \
68 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
71 unsigned long flags; \
73 raw_local_irq_save(flags); \
75 raw_local_irq_restore(flags); \
79 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
80 static __inline__ int atomic_##op##_return_relaxed(int i, atomic_t * v) \
84 if (kernel_uses_llsc) { \
87 __asm__ __volatile__( \
88 " .set "MIPS_ISA_LEVEL" \n" \
89 "1: ll %1, %2 # atomic_" #op "_return \n" \
90 " " #asm_op " %0, %1, %3 \n" \
92 "\t" __scbeqz " %0, 1b \n" \
93 " " #asm_op " %0, %1, %3 \n" \
95 : "=&r" (result), "=&r" (temp), \
96 "+" GCC_OFF_SMALL_ASM() (v->counter) \
99 unsigned long flags; \
101 raw_local_irq_save(flags); \
102 result = v->counter; \
104 v->counter = result; \
105 raw_local_irq_restore(flags); \
111 #define ATOMIC_FETCH_OP(op, c_op, asm_op) \
112 static __inline__ int atomic_fetch_##op##_relaxed(int i, atomic_t * v) \
116 if (kernel_uses_llsc) { \
119 __asm__ __volatile__( \
120 " .set "MIPS_ISA_LEVEL" \n" \
121 "1: ll %1, %2 # atomic_fetch_" #op " \n" \
122 " " #asm_op " %0, %1, %3 \n" \
124 "\t" __scbeqz " %0, 1b \n" \
127 : "=&r" (result), "=&r" (temp), \
128 "+" GCC_OFF_SMALL_ASM() (v->counter) \
131 unsigned long flags; \
133 raw_local_irq_save(flags); \
134 result = v->counter; \
136 raw_local_irq_restore(flags); \
142 #define ATOMIC_OPS(op, c_op, asm_op) \
143 ATOMIC_OP(op, c_op, asm_op) \
144 ATOMIC_OP_RETURN(op, c_op, asm_op) \
145 ATOMIC_FETCH_OP(op, c_op, asm_op)
147 ATOMIC_OPS(add, +=, addu)
148 ATOMIC_OPS(sub, -=, subu)
150 #define atomic_add_return_relaxed atomic_add_return_relaxed
151 #define atomic_sub_return_relaxed atomic_sub_return_relaxed
152 #define atomic_fetch_add_relaxed atomic_fetch_add_relaxed
153 #define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed
156 #define ATOMIC_OPS(op, c_op, asm_op) \
157 ATOMIC_OP(op, c_op, asm_op) \
158 ATOMIC_FETCH_OP(op, c_op, asm_op)
160 ATOMIC_OPS(and, &=, and)
161 ATOMIC_OPS(or, |=, or)
162 ATOMIC_OPS(xor, ^=, xor)
164 #define atomic_fetch_and_relaxed atomic_fetch_and_relaxed
165 #define atomic_fetch_or_relaxed atomic_fetch_or_relaxed
166 #define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed
169 #undef ATOMIC_FETCH_OP
170 #undef ATOMIC_OP_RETURN
174 * atomic_sub_if_positive - conditionally subtract integer from atomic variable
175 * @i: integer value to subtract
176 * @v: pointer of type atomic_t
178 * Atomically test @v and subtract @i if @v is greater or equal than @i.
179 * The function returns the old value of @v minus @i.
181 static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
185 smp_mb__before_llsc();
187 if (kernel_uses_llsc) {
190 __asm__ __volatile__(
191 " .set "MIPS_ISA_LEVEL" \n"
192 "1: ll %1, %2 # atomic_sub_if_positive\n"
193 " subu %0, %1, %3 \n"
197 "\t" __scbeqz " %1, 1b \n"
200 : "=&r" (result), "=&r" (temp),
201 "+" GCC_OFF_SMALL_ASM() (v->counter)
206 raw_local_irq_save(flags);
211 raw_local_irq_restore(flags);
219 #define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
220 #define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
223 * atomic_dec_if_positive - decrement by 1 if old value positive
224 * @v: pointer of type atomic_t
226 #define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v)
230 #define ATOMIC64_INIT(i) { (i) }
233 * atomic64_read - read atomic variable
234 * @v: pointer of type atomic64_t
237 #define atomic64_read(v) READ_ONCE((v)->counter)
240 * atomic64_set - set atomic variable
241 * @v: pointer of type atomic64_t
244 #define atomic64_set(v, i) WRITE_ONCE((v)->counter, (i))
246 #define ATOMIC64_OP(op, c_op, asm_op) \
247 static __inline__ void atomic64_##op(long i, atomic64_t * v) \
249 if (kernel_uses_llsc) { \
252 __asm__ __volatile__( \
253 " .set "MIPS_ISA_LEVEL" \n" \
254 "1: lld %0, %1 # atomic64_" #op " \n" \
255 " " #asm_op " %0, %2 \n" \
257 "\t" __scbeqz " %0, 1b \n" \
259 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
262 unsigned long flags; \
264 raw_local_irq_save(flags); \
266 raw_local_irq_restore(flags); \
270 #define ATOMIC64_OP_RETURN(op, c_op, asm_op) \
271 static __inline__ long atomic64_##op##_return_relaxed(long i, atomic64_t * v) \
275 if (kernel_uses_llsc) { \
278 __asm__ __volatile__( \
279 " .set "MIPS_ISA_LEVEL" \n" \
280 "1: lld %1, %2 # atomic64_" #op "_return\n" \
281 " " #asm_op " %0, %1, %3 \n" \
283 "\t" __scbeqz " %0, 1b \n" \
284 " " #asm_op " %0, %1, %3 \n" \
286 : "=&r" (result), "=&r" (temp), \
287 "+" GCC_OFF_SMALL_ASM() (v->counter) \
290 unsigned long flags; \
292 raw_local_irq_save(flags); \
293 result = v->counter; \
295 v->counter = result; \
296 raw_local_irq_restore(flags); \
302 #define ATOMIC64_FETCH_OP(op, c_op, asm_op) \
303 static __inline__ long atomic64_fetch_##op##_relaxed(long i, atomic64_t * v) \
307 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
310 __asm__ __volatile__( \
311 " .set "MIPS_ISA_LEVEL" \n" \
312 "1: lld %1, %2 # atomic64_fetch_" #op "\n" \
313 " " #asm_op " %0, %1, %3 \n" \
315 "\t" __scbeqz " %0, 1b \n" \
318 : "=&r" (result), "=&r" (temp), \
319 "+" GCC_OFF_SMALL_ASM() (v->counter) \
322 unsigned long flags; \
324 raw_local_irq_save(flags); \
325 result = v->counter; \
327 raw_local_irq_restore(flags); \
333 #define ATOMIC64_OPS(op, c_op, asm_op) \
334 ATOMIC64_OP(op, c_op, asm_op) \
335 ATOMIC64_OP_RETURN(op, c_op, asm_op) \
336 ATOMIC64_FETCH_OP(op, c_op, asm_op)
338 ATOMIC64_OPS(add, +=, daddu)
339 ATOMIC64_OPS(sub, -=, dsubu)
341 #define atomic64_add_return_relaxed atomic64_add_return_relaxed
342 #define atomic64_sub_return_relaxed atomic64_sub_return_relaxed
343 #define atomic64_fetch_add_relaxed atomic64_fetch_add_relaxed
344 #define atomic64_fetch_sub_relaxed atomic64_fetch_sub_relaxed
347 #define ATOMIC64_OPS(op, c_op, asm_op) \
348 ATOMIC64_OP(op, c_op, asm_op) \
349 ATOMIC64_FETCH_OP(op, c_op, asm_op)
351 ATOMIC64_OPS(and, &=, and)
352 ATOMIC64_OPS(or, |=, or)
353 ATOMIC64_OPS(xor, ^=, xor)
355 #define atomic64_fetch_and_relaxed atomic64_fetch_and_relaxed
356 #define atomic64_fetch_or_relaxed atomic64_fetch_or_relaxed
357 #define atomic64_fetch_xor_relaxed atomic64_fetch_xor_relaxed
360 #undef ATOMIC64_FETCH_OP
361 #undef ATOMIC64_OP_RETURN
365 * atomic64_sub_if_positive - conditionally subtract integer from atomic
367 * @i: integer value to subtract
368 * @v: pointer of type atomic64_t
370 * Atomically test @v and subtract @i if @v is greater or equal than @i.
371 * The function returns the old value of @v minus @i.
373 static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
377 smp_mb__before_llsc();
379 if (kernel_uses_llsc) {
382 __asm__ __volatile__(
383 " .set "MIPS_ISA_LEVEL" \n"
384 "1: lld %1, %2 # atomic64_sub_if_positive\n"
385 " dsubu %0, %1, %3 \n"
389 "\t" __scbeqz " %1, 1b \n"
392 : "=&r" (result), "=&r" (temp),
393 "+" GCC_OFF_SMALL_ASM() (v->counter)
398 raw_local_irq_save(flags);
403 raw_local_irq_restore(flags);
411 #define atomic64_cmpxchg(v, o, n) \
412 ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
413 #define atomic64_xchg(v, new) (xchg(&((v)->counter), (new)))
416 * atomic64_dec_if_positive - decrement by 1 if old value positive
417 * @v: pointer of type atomic64_t
419 #define atomic64_dec_if_positive(v) atomic64_sub_if_positive(1, v)
421 #endif /* CONFIG_64BIT */
423 #endif /* _ASM_ATOMIC_H */