arch/mips/boot/dts/brcm/bcm7360.dtsi

   1 / {
   2         #address-cells = <1>;
   3         #size-cells = <1>;
   4         compatible = "brcm,bcm7360";
   5
   6         cpus {
   7                 #address-cells = <1>;
   8                 #size-cells = <0>;
   9
  10                 mips-hpt-frequency = <375000000>;
  11
  12                 cpu@0 {
  13                         compatible = "brcm,bmips3300";
  14                         device_type = "cpu";
  15                         reg = <0>;
  16                 };
  17         };
  18
  19         aliases {
  20                 uart0 = &uart0;
  21         };
  22
  23         cpu_intc: cpu_intc {
  24                 #address-cells = <0>;
  25                 compatible = "mti,cpu-interrupt-controller";
  26
  27                 interrupt-controller;
  28                 #interrupt-cells = <1>;
  29         };
  30
  31         clocks {
  32                 uart_clk: uart_clk {
  33                         compatible = "fixed-clock";
  34                         #clock-cells = <0>;
  35                         clock-frequency = <81000000>;
  36                 };
  37         };
  38
  39         rdb {
  40                 #address-cells = <1>;
  41                 #size-cells = <1>;
  42
  43                 compatible = "simple-bus";
  44                 ranges = <0 0x10000000 0x01000000>;
  45
  46                 periph_intc: periph_intc@411400 {
  47                         compatible = "brcm,bcm7038-l1-intc";
  48                         reg = <0x411400 0x30>;
  49
  50                         interrupt-controller;
  51                         #interrupt-cells = <1>;
  52
  53                         interrupt-parent = <&cpu_intc>;
  54                         interrupts = <2>;
  55                 };
  56
  57                 sun_l2_intc: sun_l2_intc@403000 {
  58                         compatible = "brcm,l2-intc";
  59                         reg = <0x403000 0x30>;
  60                         interrupt-controller;
  61                         #interrupt-cells = <1>;
  62                         interrupt-parent = <&periph_intc>;
  63                         interrupts = <48>;
  64                 };
  65
  66                 gisb-arb@400000 {
  67                         compatible = "brcm,bcm7400-gisb-arb";
  68                         reg = <0x400000 0xdc>;
  69                         native-endian;
  70                         interrupt-parent = <&sun_l2_intc>;
  71                         interrupts = <0>, <2>;
  72                         brcm,gisb-arb-master-mask = <0x2f3>;
  73                         brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
  74                                                      "rdc_0", "raaga_0",
  75                                                      "avd_0", "jtag_0";
  76                 };
  77
  78                 upg_irq0_intc: upg_irq0_intc@406600 {
  79                         compatible = "brcm,bcm7120-l2-intc";
  80                         reg = <0x406600 0x8>;
  81
  82                         brcm,int-map-mask = <0x44>, <0x7000000>;
  83                         brcm,int-fwd-mask = <0x70000>;
  84
  85                         interrupt-controller;
  86                         #interrupt-cells = <1>;
  87
  88                         interrupt-parent = <&periph_intc>;
  89                         interrupts = <56>, <54>;
  90                         interrupt-names = "upg_main", "upg_bsc";
  91                 };
  92
  93                 upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
  94                         compatible = "brcm,bcm7120-l2-intc";
  95                         reg = <0x408b80 0x8>;
  96
  97                         brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
  98                         brcm,int-fwd-mask = <0>;
  99                         brcm,irq-can-wake;
 100
 101                         interrupt-controller;
 102                         #interrupt-cells = <1>;
 103
 104                         interrupt-parent = <&periph_intc>;
 105                         interrupts = <57>, <55>, <59>;
 106                         interrupt-names = "upg_main_aon", "upg_bsc_aon",
 107                                           "upg_spi";
 108                 };
 109
 110                 sun_top_ctrl: syscon@404000 {
 111                         compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
 112                         reg = <0x404000 0x51c>;
 113                         native-endian;
 114                 };
 115
 116                 reboot {
 117                         compatible = "brcm,brcmstb-reboot";
 118                         syscon = <&sun_top_ctrl 0x304 0x308>;
 119                 };
 120
 121                 uart0: serial@406800 {
 122                         compatible = "ns16550a";
 123                         reg = <0x406800 0x20>;
 124                         reg-io-width = <0x4>;
 125                         reg-shift = <0x2>;
 126                         native-endian;
 127                         interrupt-parent = <&periph_intc>;
 128                         interrupts = <61>;
 129                         clocks = <&uart_clk>;
 130                         status = "disabled";
 131                 };
 132
 133                 uart1: serial@406840 {
 134                         compatible = "ns16550a";
 135                         reg = <0x406840 0x20>;
 136                         reg-io-width = <0x4>;
 137                         reg-shift = <0x2>;
 138                         native-endian;
 139                         interrupt-parent = <&periph_intc>;
 140                         interrupts = <62>;
 141                         clocks = <&uart_clk>;
 142                         status = "disabled";
 143                 };
 144
 145                 uart2: serial@406880 {
 146                         compatible = "ns16550a";
 147                         reg = <0x406880 0x20>;
 148                         reg-io-width = <0x4>;
 149                         reg-shift = <0x2>;
 150                         native-endian;
 151                         interrupt-parent = <&periph_intc>;
 152                         interrupts = <63>;
 153                         clocks = <&uart_clk>;
 154                         status = "disabled";
 155                 };
 156
 157                 bsca: i2c@406200 {
 158                       clock-frequency = <390000>;
 159                       compatible = "brcm,brcmstb-i2c";
 160                       interrupt-parent = <&upg_irq0_intc>;
 161                       reg = <0x406200 0x58>;
 162                       interrupts = <24>;
 163                       interrupt-names = "upg_bsca";
 164                       status = "disabled";
 165                 };
 166
 167                 bscb: i2c@406280 {
 168                       clock-frequency = <390000>;
 169                       compatible = "brcm,brcmstb-i2c";
 170                       interrupt-parent = <&upg_irq0_intc>;
 171                       reg = <0x406280 0x58>;
 172                       interrupts = <25>;
 173                       interrupt-names = "upg_bscb";
 174                       status = "disabled";
 175                 };
 176
 177                 bscc: i2c@406300 {
 178                       clock-frequency = <390000>;
 179                       compatible = "brcm,brcmstb-i2c";
 180                       interrupt-parent = <&upg_irq0_intc>;
 181                       reg = <0x406300 0x58>;
 182                       interrupts = <26>;
 183                       interrupt-names = "upg_bscc";
 184                       status = "disabled";
 185                 };
 186
 187                 bscd: i2c@408980 {
 188                       clock-frequency = <390000>;
 189                       compatible = "brcm,brcmstb-i2c";
 190                       interrupt-parent = <&upg_aon_irq0_intc>;
 191                       reg = <0x408980 0x58>;
 192                       interrupts = <27>;
 193                       interrupt-names = "upg_bscd";
 194                       status = "disabled";
 195                 };
 196
 197                 enet0: ethernet@430000 {
 198                         phy-mode = "internal";
 199                         phy-handle = <&phy1>;
 200                         mac-address = [ 00 10 18 36 23 1a ];
 201                         compatible = "brcm,genet-v2";
 202                         #address-cells = <0x1>;
 203                         #size-cells = <0x1>;
 204                         reg = <0x430000 0x4c8c>;
 205                         interrupts = <24>, <25>;
 206                         interrupt-parent = <&periph_intc>;
 207                         status = "disabled";
 208
 209                         mdio@e14 {
 210                                 compatible = "brcm,genet-mdio-v2";
 211                                 #address-cells = <0x1>;
 212                                 #size-cells = <0x0>;
 213                                 reg = <0xe14 0x8>;
 214
 215                                 phy1: ethernet-phy@1 {
 216                                         max-speed = <100>;
 217                                         reg = <0x1>;
 218                                         compatible = "brcm,40nm-ephy",
 219                                                 "ethernet-phy-ieee802.3-c22";
 220                                 };
 221                         };
 222                 };
 223
 224                 ehci0: usb@480300 {
 225                         compatible = "brcm,bcm7360-ehci", "generic-ehci";
 226                         reg = <0x480300 0x100>;
 227                         native-endian;
 228                         interrupt-parent = <&periph_intc>;
 229                         interrupts = <65>;
 230                         status = "disabled";
 231                 };
 232
 233                 ohci0: usb@480400 {
 234                         compatible = "brcm,bcm7360-ohci", "generic-ohci";
 235                         reg = <0x480400 0x100>;
 236                         native-endian;
 237                         no-big-frame-no;
 238                         interrupt-parent = <&periph_intc>;
 239                         interrupts = <66>;
 240                         status = "disabled";
 241                 };
 242
 243                 sata: sata@181000 {
 244                         compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
 245                         reg-names = "ahci", "top-ctrl";
 246                         reg = <0x181000 0xa9c>, <0x180020 0x1c>;
 247                         interrupt-parent = <&periph_intc>;
 248                         interrupts = <86>;
 249                         #address-cells = <1>;
 250                         #size-cells = <0>;
 251                         status = "disabled";
 252
 253                         sata0: sata-port@0 {
 254                                 reg = <0>;
 255                                 phys = <&sata_phy0>;
 256                         };
 257
 258                         sata1: sata-port@1 {
 259                                 reg = <1>;
 260                                 phys = <&sata_phy1>;
 261                         };
 262                 };
 263
 264                 sata_phy: sata-phy@180100 {
 265                         compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
 266                         reg = <0x180100 0x0eff>;
 267                         reg-names = "phy";
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270                         status = "disabled";
 271
 272                         sata_phy0: sata-phy@0 {
 273                                 reg = <0>;
 274                                 #phy-cells = <0>;
 275                         };
 276
 277                         sata_phy1: sata-phy@1 {
 278                                 reg = <1>;
 279                                 #phy-cells = <0>;
 280                         };
 281                 };
 282         };
 283 };