arch/mips/boot/dts/brcm/bcm7125.dtsi

   1 / {
   2         #address-cells = <1>;
   3         #size-cells = <1>;
   4         compatible = "brcm,bcm7125";
   5
   6         cpus {
   7                 #address-cells = <1>;
   8                 #size-cells = <0>;
   9
  10                 mips-hpt-frequency = <202500000>;
  11
  12                 cpu@0 {
  13                         compatible = "brcm,bmips4380";
  14                         device_type = "cpu";
  15                         reg = <0>;
  16                 };
  17
  18                 cpu@1 {
  19                         compatible = "brcm,bmips4380";
  20                         device_type = "cpu";
  21                         reg = <1>;
  22                 };
  23         };
  24
  25         aliases {
  26                 uart0 = &uart0;
  27         };
  28
  29         cpu_intc: cpu_intc {
  30                 #address-cells = <0>;
  31                 compatible = "mti,cpu-interrupt-controller";
  32
  33                 interrupt-controller;
  34                 #interrupt-cells = <1>;
  35         };
  36
  37         clocks {
  38                 uart_clk: uart_clk {
  39                         compatible = "fixed-clock";
  40                         #clock-cells = <0>;
  41                         clock-frequency = <81000000>;
  42                 };
  43         };
  44
  45         rdb {
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48
  49                 compatible = "simple-bus";
  50                 ranges = <0 0x10000000 0x01000000>;
  51
  52                 periph_intc: periph_intc@441400 {
  53                         compatible = "brcm,bcm7038-l1-intc";
  54                         reg = <0x441400 0x30>, <0x441600 0x30>;
  55
  56                         interrupt-controller;
  57                         #interrupt-cells = <1>;
  58
  59                         interrupt-parent = <&cpu_intc>;
  60                         interrupts = <2>, <3>;
  61                 };
  62
  63                 sun_l2_intc: sun_l2_intc@401800 {
  64                         compatible = "brcm,l2-intc";
  65                         reg = <0x401800 0x30>;
  66                         interrupt-controller;
  67                         #interrupt-cells = <1>;
  68                         interrupt-parent = <&periph_intc>;
  69                         interrupts = <23>;
  70                 };
  71
  72                 gisb-arb@400000 {
  73                         compatible = "brcm,bcm7400-gisb-arb";
  74                         reg = <0x400000 0xdc>;
  75                         native-endian;
  76                         interrupt-parent = <&sun_l2_intc>;
  77                         interrupts = <0>, <2>;
  78                         brcm,gisb-arb-master-mask = <0x2f7>;
  79                         brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
  80                                                      "bsp_0", "rdc_0", "rptd_0",
  81                                                      "avd_0", "jtag_0";
  82                 };
  83
  84                 upg_irq0_intc: upg_irq0_intc@406780 {
  85                         compatible = "brcm,bcm7120-l2-intc";
  86                         reg = <0x406780 0x8>;
  87
  88                         brcm,int-map-mask = <0x44>, <0xf000000>;
  89                         brcm,int-fwd-mask = <0x70000>;
  90
  91                         interrupt-controller;
  92                         #interrupt-cells = <1>;
  93
  94                         interrupt-parent = <&periph_intc>;
  95                         interrupts = <18>, <19>;
  96                         interrupt-names = "upg_main", "upg_bsc";
  97                 };
  98
  99                 sun_top_ctrl: syscon@404000 {
 100                         compatible = "brcm,bcm7125-sun-top-ctrl", "syscon";
 101                         reg = <0x404000 0x60c>;
 102                         native-endian;
 103                 };
 104
 105                 reboot {
 106                         compatible = "brcm,bcm7038-reboot";
 107                         syscon = <&sun_top_ctrl 0x8 0x14>;
 108                 };
 109
 110                 uart0: serial@406b00 {
 111                         compatible = "ns16550a";
 112                         reg = <0x406b00 0x20>;
 113                         reg-io-width = <0x4>;
 114                         reg-shift = <0x2>;
 115                         native-endian;
 116                         interrupt-parent = <&periph_intc>;
 117                         interrupts = <21>;
 118                         clocks = <&uart_clk>;
 119                         status = "disabled";
 120                 };
 121
 122                 uart1: serial@406b40 {
 123                         compatible = "ns16550a";
 124                         reg = <0x406b40 0x20>;
 125                         reg-io-width = <0x4>;
 126                         reg-shift = <0x2>;
 127                         native-endian;
 128                         interrupt-parent = <&periph_intc>;
 129                         interrupts = <64>;
 130                         clocks = <&uart_clk>;
 131                         status = "disabled";
 132                 };
 133
 134                 uart2: serial@406b80 {
 135                         compatible = "ns16550a";
 136                         reg = <0x406b80 0x20>;
 137                         reg-io-width = <0x4>;
 138                         reg-shift = <0x2>;
 139                         native-endian;
 140                         interrupt-parent = <&periph_intc>;
 141                         interrupts = <65>;
 142                         clocks = <&uart_clk>;
 143                         status = "disabled";
 144                 };
 145
 146                 bsca: i2c@406200 {
 147                       clock-frequency = <390000>;
 148                       compatible = "brcm,brcmstb-i2c";
 149                       interrupt-parent = <&upg_irq0_intc>;
 150                       reg = <0x406200 0x58>;
 151                       interrupts = <24>;
 152                       interrupt-names = "upg_bsca";
 153                       status = "disabled";
 154                 };
 155
 156                 bscb: i2c@406280 {
 157                       clock-frequency = <390000>;
 158                       compatible = "brcm,brcmstb-i2c";
 159                       interrupt-parent = <&upg_irq0_intc>;
 160                       reg = <0x406280 0x58>;
 161                       interrupts = <25>;
 162                       interrupt-names = "upg_bscb";
 163                       status = "disabled";
 164                 };
 165
 166                 bscc: i2c@406300 {
 167                       clock-frequency = <390000>;
 168                       compatible = "brcm,brcmstb-i2c";
 169                       interrupt-parent = <&upg_irq0_intc>;
 170                       reg = <0x406300 0x58>;
 171                       interrupts = <26>;
 172                       interrupt-names = "upg_bscc";
 173                       status = "disabled";
 174                 };
 175
 176                 bscd: i2c@406380 {
 177                       clock-frequency = <390000>;
 178                       compatible = "brcm,brcmstb-i2c";
 179                       interrupt-parent = <&upg_irq0_intc>;
 180                       reg = <0x406380 0x58>;
 181                       interrupts = <27>;
 182                       interrupt-names = "upg_bscd";
 183                       status = "disabled";
 184                 };
 185
 186                 ehci0: usb@488300 {
 187                         compatible = "brcm,bcm7125-ehci", "generic-ehci";
 188                         reg = <0x488300 0x100>;
 189                         native-endian;
 190                         interrupt-parent = <&periph_intc>;
 191                         interrupts = <60>;
 192                         status = "disabled";
 193                 };
 194
 195                 ohci0: usb@488400 {
 196                         compatible = "brcm,bcm7125-ohci", "generic-ohci";
 197                         reg = <0x488400 0x100>;
 198                         native-endian;
 199                         interrupt-parent = <&periph_intc>;
 200                         interrupts = <61>;
 201                         status = "disabled";
 202                 };
 203         };
 204 };