arch/m32r/platforms/oaks32r/setup.c

   1 /*
   2  *  linux/arch/m32r/platforms/oaks32r/setup.c
   3  *
   4  *  Setup routines for OAKS32R Board
   5  *
   6  *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata,
   7  *                           Hitoshi Yamamoto, Mamoru Sakugawa
   8  */
   9
  10 #include <linux/irq.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13
  14 #include <asm/m32r.h>
  15 #include <asm/io.h>
  16
  17 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
  18
  19 icu_data_t icu_data[NR_IRQS];
  20
  21 static void disable_oaks32r_irq(unsigned int irq)
  22 {
  23         unsigned long port, data;
  24
  25         port = irq2port(irq);
  26         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
  27         outl(data, port);
  28 }
  29
  30 static void enable_oaks32r_irq(unsigned int irq)
  31 {
  32         unsigned long port, data;
  33
  34         port = irq2port(irq);
  35         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
  36         outl(data, port);
  37 }
  38
  39 static void mask_oaks32r(struct irq_data *data)
  40 {
  41         disable_oaks32r_irq(data->irq);
  42 }
  43
  44 static void unmask_oaks32r(struct irq_data *data)
  45 {
  46         enable_oaks32r_irq(data->irq);
  47 }
  48
  49 static void shutdown_oaks32r(struct irq_data *data)
  50 {
  51         unsigned long port;
  52
  53         port = irq2port(data->irq);
  54         outl(M32R_ICUCR_ILEVEL7, port);
  55 }
  56
  57 static struct irq_chip oaks32r_irq_type =
  58 {
  59         .name           = "OAKS32R-IRQ",
  60         .irq_shutdown   = shutdown_oaks32r,
  61         .irq_mask       = mask_oaks32r,
  62         .irq_unmask     = unmask_oaks32r,
  63 };
  64
  65 void __init init_IRQ(void)
  66 {
  67         static int once = 0;
  68
  69         if (once)
  70                 return;
  71         else
  72                 once++;
  73
  74 #ifdef CONFIG_NE2000
  75         /* INT3 : LAN controller (RTL8019AS) */
  76         irq_set_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type,
  77                                  handle_level_irq);
  78         icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
  79         disable_oaks32r_irq(M32R_IRQ_INT3);
  80 #endif /* CONFIG_M32R_NE2000 */
  81
  82         /* MFT2 : system timer */
  83         irq_set_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type,
  84                                  handle_level_irq);
  85         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
  86         disable_oaks32r_irq(M32R_IRQ_MFT2);
  87
  88 #ifdef CONFIG_SERIAL_M32R_SIO
  89         /* SIO0_R : uart receive data */
  90         irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type,
  91                                  handle_level_irq);
  92         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
  93         disable_oaks32r_irq(M32R_IRQ_SIO0_R);
  94
  95         /* SIO0_S : uart send data */
  96         irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type,
  97                                  handle_level_irq);
  98         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
  99         disable_oaks32r_irq(M32R_IRQ_SIO0_S);
 100
 101         /* SIO1_R : uart receive data */
 102         irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type,
 103                                  handle_level_irq);
 104         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
 105         disable_oaks32r_irq(M32R_IRQ_SIO1_R);
 106
 107         /* SIO1_S : uart send data */
 108         irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type,
 109                                  handle_level_irq);
 110         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
 111         disable_oaks32r_irq(M32R_IRQ_SIO1_S);
 112 #endif /* CONFIG_SERIAL_M32R_SIO */
 113 }