arch/ia64/sn/kernel/sn2/sn2_smp.c

   1 /*
   2  * SN2 Platform specific SMP Support
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2000-2006 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/threads.h>
  15 #include <linux/sched.h>
  16 #include <linux/mm_types.h>
  17 #include <linux/smp.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <linux/mmzone.h>
  21 #include <linux/module.h>
  22 #include <linux/bitops.h>
  23 #include <linux/nodemask.h>
  24 #include <linux/proc_fs.h>
  25 #include <linux/seq_file.h>
  26
  27 #include <asm/processor.h>
  28 #include <asm/irq.h>
  29 #include <asm/sal.h>
  30 #include <asm/delay.h>
  31 #include <asm/io.h>
  32 #include <asm/smp.h>
  33 #include <asm/tlb.h>
  34 #include <asm/numa.h>
  35 #include <asm/hw_irq.h>
  36 #include <asm/current.h>
  37 #include <asm/sn/sn_cpuid.h>
  38 #include <asm/sn/sn_sal.h>
  39 #include <asm/sn/addrs.h>
  40 #include <asm/sn/shub_mmr.h>
  41 #include <asm/sn/nodepda.h>
  42 #include <asm/sn/rw_mmr.h>
  43 #include <asm/sn/sn_feature_sets.h>
  44
  45 DEFINE_PER_CPU(struct ptc_stats, ptcstats);
  46 DECLARE_PER_CPU(struct ptc_stats, ptcstats);
  47
  48 static  __cacheline_aligned DEFINE_SPINLOCK(sn2_global_ptc_lock);
  49
  50 /* 0 = old algorithm (no IPI flushes), 1 = ipi deadlock flush, 2 = ipi instead of SHUB ptc, >2 = always ipi */
  51 static int sn2_flush_opt = 0;
  52
  53 extern unsigned long
  54 sn2_ptc_deadlock_recovery_core(volatile unsigned long *, unsigned long,
  55                                volatile unsigned long *, unsigned long,
  56                                volatile unsigned long *, unsigned long);
  57 void
  58 sn2_ptc_deadlock_recovery(nodemask_t, short, short, int,
  59                           volatile unsigned long *, unsigned long,
  60                           volatile unsigned long *, unsigned long);
  61
  62 /*
  63  * Note: some is the following is captured here to make degugging easier
  64  * (the macros make more sense if you see the debug patch - not posted)
  65  */
  66 #define sn2_ptctest     0
  67 #define local_node_uses_ptc_ga(sh1)     ((sh1) ? 1 : 0)
  68 #define max_active_pio(sh1)             ((sh1) ? 32 : 7)
  69 #define reset_max_active_on_deadlock()  1
  70 #define PTC_LOCK(sh1)                   ((sh1) ? &sn2_global_ptc_lock : &sn_nodepda->ptc_lock)
  71
  72 struct ptc_stats {
  73         unsigned long ptc_l;
  74         unsigned long change_rid;
  75         unsigned long shub_ptc_flushes;
  76         unsigned long nodes_flushed;
  77         unsigned long deadlocks;
  78         unsigned long deadlocks2;
  79         unsigned long lock_itc_clocks;
  80         unsigned long shub_itc_clocks;
  81         unsigned long shub_itc_clocks_max;
  82         unsigned long shub_ptc_flushes_not_my_mm;
  83         unsigned long shub_ipi_flushes;
  84         unsigned long shub_ipi_flushes_itc_clocks;
  85 };
  86
  87 #define sn2_ptctest     0
  88
  89 static inline unsigned long wait_piowc(void)
  90 {
  91         volatile unsigned long *piows;
  92         unsigned long zeroval, ws;
  93
  94         piows = pda->pio_write_status_addr;
  95         zeroval = pda->pio_write_status_val;
  96         do {
  97                 cpu_relax();
  98         } while (((ws = *piows) & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != zeroval);
  99         return (ws & SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK) != 0;
 100 }
 101
 102 /**
 103  * sn_migrate - SN-specific task migration actions
 104  * @task: Task being migrated to new CPU
 105  *
 106  * SN2 PIO writes from separate CPUs are not guaranteed to arrive in order.
 107  * Context switching user threads which have memory-mapped MMIO may cause
 108  * PIOs to issue from separate CPUs, thus the PIO writes must be drained
 109  * from the previous CPU's Shub before execution resumes on the new CPU.
 110  */
 111 void sn_migrate(struct task_struct *task)
 112 {
 113         pda_t *last_pda = pdacpu(task_thread_info(task)->last_cpu);
 114         volatile unsigned long *adr = last_pda->pio_write_status_addr;
 115         unsigned long val = last_pda->pio_write_status_val;
 116
 117         /* Drain PIO writes from old CPU's Shub */
 118         while (unlikely((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK)
 119                         != val))
 120                 cpu_relax();
 121 }
 122
 123 static void
 124 sn2_ipi_flush_all_tlb(struct mm_struct *mm)
 125 {
 126         unsigned long itc;
 127
 128         itc = ia64_get_itc();
 129         smp_flush_tlb_cpumask(*mm_cpumask(mm));
 130         itc = ia64_get_itc() - itc;
 131         __this_cpu_add(ptcstats.shub_ipi_flushes_itc_clocks, itc);
 132         __this_cpu_inc(ptcstats.shub_ipi_flushes);
 133 }
 134
 135 /**
 136  * sn2_global_tlb_purge - globally purge translation cache of virtual address range
 137  * @mm: mm_struct containing virtual address range
 138  * @start: start of virtual address range
 139  * @end: end of virtual address range
 140  * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
 141  *
 142  * Purges the translation caches of all processors of the given virtual address
 143  * range.
 144  *
 145  * Note:
 146  *      - cpu_vm_mask is a bit mask that indicates which cpus have loaded the context.
 147  *      - cpu_vm_mask is converted into a nodemask of the nodes containing the
 148  *        cpus in cpu_vm_mask.
 149  *      - if only one bit is set in cpu_vm_mask & it is the current cpu & the
 150  *        process is purging its own virtual address range, then only the
 151  *        local TLB needs to be flushed. This flushing can be done using
 152  *        ptc.l. This is the common case & avoids the global spinlock.
 153  *      - if multiple cpus have loaded the context, then flushing has to be
 154  *        done with ptc.g/MMRs under protection of the global ptc_lock.
 155  */
 156
 157 void
 158 sn2_global_tlb_purge(struct mm_struct *mm, unsigned long start,
 159                      unsigned long end, unsigned long nbits)
 160 {
 161         int i, ibegin, shub1, cnode, mynasid, cpu, lcpu = 0, nasid;
 162         int mymm = (mm == current->active_mm && mm == current->mm);
 163         int use_cpu_ptcga;
 164         volatile unsigned long *ptc0, *ptc1;
 165         unsigned long itc, itc2, flags, data0 = 0, data1 = 0, rr_value, old_rr = 0;
 166         short nix;
 167         nodemask_t nodes_flushed;
 168         int active, max_active, deadlock, flush_opt = sn2_flush_opt;
 169
 170         if (flush_opt > 2) {
 171                 sn2_ipi_flush_all_tlb(mm);
 172                 return;
 173         }
 174
 175         nodes_clear(nodes_flushed);
 176         i = 0;
 177
 178         for_each_cpu(cpu, mm_cpumask(mm)) {
 179                 cnode = cpu_to_node(cpu);
 180                 node_set(cnode, nodes_flushed);
 181                 lcpu = cpu;
 182                 i++;
 183         }
 184
 185         if (i == 0)
 186                 return;
 187
 188         preempt_disable();
 189
 190         if (likely(i == 1 && lcpu == smp_processor_id() && mymm)) {
 191                 do {
 192                         ia64_ptcl(start, nbits << 2);
 193                         start += (1UL << nbits);
 194                 } while (start < end);
 195                 ia64_srlz_i();
 196                 __this_cpu_inc(ptcstats.ptc_l);
 197                 preempt_enable();
 198                 return;
 199         }
 200
 201         if (atomic_read(&mm->mm_users) == 1 && mymm) {
 202                 flush_tlb_mm(mm);
 203                 __this_cpu_inc(ptcstats.change_rid);
 204                 preempt_enable();
 205                 return;
 206         }
 207
 208         if (flush_opt == 2) {
 209                 sn2_ipi_flush_all_tlb(mm);
 210                 preempt_enable();
 211                 return;
 212         }
 213
 214         itc = ia64_get_itc();
 215         nix = nodes_weight(nodes_flushed);
 216
 217         rr_value = (mm->context << 3) | REGION_NUMBER(start);
 218
 219         shub1 = is_shub1();
 220         if (shub1) {
 221                 data0 = (1UL << SH1_PTC_0_A_SHFT) |
 222                         (nbits << SH1_PTC_0_PS_SHFT) |
 223                         (rr_value << SH1_PTC_0_RID_SHFT) |
 224                         (1UL << SH1_PTC_0_START_SHFT);
 225                 ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_0);
 226                 ptc1 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_1);
 227         } else {
 228                 data0 = (1UL << SH2_PTC_A_SHFT) |
 229                         (nbits << SH2_PTC_PS_SHFT) |
 230                         (1UL << SH2_PTC_START_SHFT);
 231                 ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH2_PTC +
 232                         (rr_value << SH2_PTC_RID_SHFT));
 233                 ptc1 = NULL;
 234         }
 235
 236
 237         mynasid = get_nasid();
 238         use_cpu_ptcga = local_node_uses_ptc_ga(shub1);
 239         max_active = max_active_pio(shub1);
 240
 241         itc = ia64_get_itc();
 242         spin_lock_irqsave(PTC_LOCK(shub1), flags);
 243         itc2 = ia64_get_itc();
 244
 245         __this_cpu_add(ptcstats.lock_itc_clocks, itc2 - itc);
 246         __this_cpu_inc(ptcstats.shub_ptc_flushes);
 247         __this_cpu_add(ptcstats.nodes_flushed, nix);
 248         if (!mymm)
 249                  __this_cpu_inc(ptcstats.shub_ptc_flushes_not_my_mm);
 250
 251         if (use_cpu_ptcga && !mymm) {
 252                 old_rr = ia64_get_rr(start);
 253                 ia64_set_rr(start, (old_rr & 0xff) | (rr_value << 8));
 254                 ia64_srlz_d();
 255         }
 256
 257         wait_piowc();
 258         do {
 259                 if (shub1)
 260                         data1 = start | (1UL << SH1_PTC_1_START_SHFT);
 261                 else
 262                         data0 = (data0 & ~SH2_PTC_ADDR_MASK) | (start & SH2_PTC_ADDR_MASK);
 263                 deadlock = 0;
 264                 active = 0;
 265                 ibegin = 0;
 266                 i = 0;
 267                 for_each_node_mask(cnode, nodes_flushed) {
 268                         nasid = cnodeid_to_nasid(cnode);
 269                         if (use_cpu_ptcga && unlikely(nasid == mynasid)) {
 270                                 ia64_ptcga(start, nbits << 2);
 271                                 ia64_srlz_i();
 272                         } else {
 273                                 ptc0 = CHANGE_NASID(nasid, ptc0);
 274                                 if (ptc1)
 275                                         ptc1 = CHANGE_NASID(nasid, ptc1);
 276                                 pio_atomic_phys_write_mmrs(ptc0, data0, ptc1, data1);
 277                                 active++;
 278                         }
 279                         if (active >= max_active || i == (nix - 1)) {
 280                                 if ((deadlock = wait_piowc())) {
 281                                         if (flush_opt == 1)
 282                                                 goto done;
 283                                         sn2_ptc_deadlock_recovery(nodes_flushed, ibegin, i, mynasid, ptc0, data0, ptc1, data1);
 284                                         if (reset_max_active_on_deadlock())
 285                                                 max_active = 1;
 286                                 }
 287                                 active = 0;
 288                                 ibegin = i + 1;
 289                         }
 290                         i++;
 291                 }
 292                 start += (1UL << nbits);
 293         } while (start < end);
 294
 295 done:
 296         itc2 = ia64_get_itc() - itc2;
 297         __this_cpu_add(ptcstats.shub_itc_clocks, itc2);
 298         if (itc2 > __this_cpu_read(ptcstats.shub_itc_clocks_max))
 299                 __this_cpu_write(ptcstats.shub_itc_clocks_max, itc2);
 300
 301         if (old_rr) {
 302                 ia64_set_rr(start, old_rr);
 303                 ia64_srlz_d();
 304         }
 305
 306         spin_unlock_irqrestore(PTC_LOCK(shub1), flags);
 307
 308         if (flush_opt == 1 && deadlock) {
 309                 __this_cpu_inc(ptcstats.deadlocks);
 310                 sn2_ipi_flush_all_tlb(mm);
 311         }
 312
 313         preempt_enable();
 314 }
 315
 316 /*
 317  * sn2_ptc_deadlock_recovery
 318  *
 319  * Recover from PTC deadlocks conditions. Recovery requires stepping thru each
 320  * TLB flush transaction.  The recovery sequence is somewhat tricky & is
 321  * coded in assembly language.
 322  */
 323
 324 void
 325 sn2_ptc_deadlock_recovery(nodemask_t nodes, short ib, short ie, int mynasid,
 326                           volatile unsigned long *ptc0, unsigned long data0,
 327                           volatile unsigned long *ptc1, unsigned long data1)
 328 {
 329         short nasid, i;
 330         int cnode;
 331         unsigned long *piows, zeroval, n;
 332
 333         __this_cpu_inc(ptcstats.deadlocks);
 334
 335         piows = (unsigned long *) pda->pio_write_status_addr;
 336         zeroval = pda->pio_write_status_val;
 337
 338         i = 0;
 339         for_each_node_mask(cnode, nodes) {
 340                 if (i < ib)
 341                         goto next;
 342
 343                 if (i > ie)
 344                         break;
 345
 346                 nasid = cnodeid_to_nasid(cnode);
 347                 if (local_node_uses_ptc_ga(is_shub1()) && nasid == mynasid)
 348                         goto next;
 349
 350                 ptc0 = CHANGE_NASID(nasid, ptc0);
 351                 if (ptc1)
 352                         ptc1 = CHANGE_NASID(nasid, ptc1);
 353
 354                 n = sn2_ptc_deadlock_recovery_core(ptc0, data0, ptc1, data1, piows, zeroval);
 355                 __this_cpu_add(ptcstats.deadlocks2, n);
 356 next:
 357                 i++;
 358         }
 359
 360 }
 361
 362 /**
 363  * sn_send_IPI_phys - send an IPI to a Nasid and slice
 364  * @nasid: nasid to receive the interrupt (may be outside partition)
 365  * @physid: physical cpuid to receive the interrupt.
 366  * @vector: command to send
 367  * @delivery_mode: delivery mechanism
 368  *
 369  * Sends an IPI (interprocessor interrupt) to the processor specified by
 370  * @physid
 371  *
 372  * @delivery_mode can be one of the following
 373  *
 374  * %IA64_IPI_DM_INT - pend an interrupt
 375  * %IA64_IPI_DM_PMI - pend a PMI
 376  * %IA64_IPI_DM_NMI - pend an NMI
 377  * %IA64_IPI_DM_INIT - pend an INIT interrupt
 378  */
 379 void sn_send_IPI_phys(int nasid, long physid, int vector, int delivery_mode)
 380 {
 381         long val;
 382         unsigned long flags = 0;
 383         volatile long *p;
 384
 385         p = (long *)GLOBAL_MMR_PHYS_ADDR(nasid, SH_IPI_INT);
 386         val = (1UL << SH_IPI_INT_SEND_SHFT) |
 387             (physid << SH_IPI_INT_PID_SHFT) |
 388             ((long)delivery_mode << SH_IPI_INT_TYPE_SHFT) |
 389             ((long)vector << SH_IPI_INT_IDX_SHFT) |
 390             (0x000feeUL << SH_IPI_INT_BASE_SHFT);
 391
 392         mb();
 393         if (enable_shub_wars_1_1()) {
 394                 spin_lock_irqsave(&sn2_global_ptc_lock, flags);
 395         }
 396         pio_phys_write_mmr(p, val);
 397         if (enable_shub_wars_1_1()) {
 398                 wait_piowc();
 399                 spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
 400         }
 401
 402 }
 403
 404 EXPORT_SYMBOL(sn_send_IPI_phys);
 405
 406 /**
 407  * sn2_send_IPI - send an IPI to a processor
 408  * @cpuid: target of the IPI
 409  * @vector: command to send
 410  * @delivery_mode: delivery mechanism
 411  * @redirect: redirect the IPI?
 412  *
 413  * Sends an IPI (InterProcessor Interrupt) to the processor specified by
 414  * @cpuid.  @vector specifies the command to send, while @delivery_mode can
 415  * be one of the following
 416  *
 417  * %IA64_IPI_DM_INT - pend an interrupt
 418  * %IA64_IPI_DM_PMI - pend a PMI
 419  * %IA64_IPI_DM_NMI - pend an NMI
 420  * %IA64_IPI_DM_INIT - pend an INIT interrupt
 421  */
 422 void sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
 423 {
 424         long physid;
 425         int nasid;
 426
 427         physid = cpu_physical_id(cpuid);
 428         nasid = cpuid_to_nasid(cpuid);
 429
 430         /* the following is used only when starting cpus at boot time */
 431         if (unlikely(nasid == -1))
 432                 ia64_sn_get_sapic_info(physid, &nasid, NULL, NULL);
 433
 434         sn_send_IPI_phys(nasid, physid, vector, delivery_mode);
 435 }
 436
 437 #ifdef CONFIG_HOTPLUG_CPU
 438 /**
 439  * sn_cpu_disable_allowed - Determine if a CPU can be disabled.
 440  * @cpu - CPU that is requested to be disabled.
 441  *
 442  * CPU disable is only allowed on SHub2 systems running with a PROM
 443  * that supports CPU disable. It is not permitted to disable the boot processor.
 444  */
 445 bool sn_cpu_disable_allowed(int cpu)
 446 {
 447         if (is_shub2() && sn_prom_feature_available(PRF_CPU_DISABLE_SUPPORT)) {
 448                 if (cpu != 0)
 449                         return true;
 450                 else
 451                         printk(KERN_WARNING
 452                               "Disabling the boot processor is not allowed.\n");
 453
 454         } else
 455                 printk(KERN_WARNING
 456                        "CPU disable is not supported on this system.\n");
 457
 458         return false;
 459 }
 460 #endif /* CONFIG_HOTPLUG_CPU */
 461
 462 #ifdef CONFIG_PROC_FS
 463
 464 #define PTC_BASENAME    "sgi_sn/ptc_statistics"
 465
 466 static void *sn2_ptc_seq_start(struct seq_file *file, loff_t * offset)
 467 {
 468         if (*offset < nr_cpu_ids)
 469                 return offset;
 470         return NULL;
 471 }
 472
 473 static void *sn2_ptc_seq_next(struct seq_file *file, void *data, loff_t * offset)
 474 {
 475         (*offset)++;
 476         if (*offset < nr_cpu_ids)
 477                 return offset;
 478         return NULL;
 479 }
 480
 481 static void sn2_ptc_seq_stop(struct seq_file *file, void *data)
 482 {
 483 }
 484
 485 static int sn2_ptc_seq_show(struct seq_file *file, void *data)
 486 {
 487         struct ptc_stats *stat;
 488         int cpu;
 489
 490         cpu = *(loff_t *) data;
 491
 492         if (!cpu) {
 493                 seq_printf(file,
 494                            "# cpu ptc_l newrid ptc_flushes nodes_flushed deadlocks lock_nsec shub_nsec shub_nsec_max not_my_mm deadlock2 ipi_fluches ipi_nsec\n");
 495                 seq_printf(file, "# ptctest %d, flushopt %d\n", sn2_ptctest, sn2_flush_opt);
 496         }
 497
 498         if (cpu < nr_cpu_ids && cpu_online(cpu)) {
 499                 stat = &per_cpu(ptcstats, cpu);
 500                 seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n", cpu, stat->ptc_l,
 501                                 stat->change_rid, stat->shub_ptc_flushes, stat->nodes_flushed,
 502                                 stat->deadlocks,
 503                                 1000 * stat->lock_itc_clocks / per_cpu(ia64_cpu_info, cpu).cyc_per_usec,
 504                                 1000 * stat->shub_itc_clocks / per_cpu(ia64_cpu_info, cpu).cyc_per_usec,
 505                                 1000 * stat->shub_itc_clocks_max / per_cpu(ia64_cpu_info, cpu).cyc_per_usec,
 506                                 stat->shub_ptc_flushes_not_my_mm,
 507                                 stat->deadlocks2,
 508                                 stat->shub_ipi_flushes,
 509                                 1000 * stat->shub_ipi_flushes_itc_clocks / per_cpu(ia64_cpu_info, cpu).cyc_per_usec);
 510         }
 511         return 0;
 512 }
 513
 514 static ssize_t sn2_ptc_proc_write(struct file *file, const char __user *user, size_t count, loff_t *data)
 515 {
 516         int cpu;
 517         char optstr[64];
 518
 519         if (count == 0 || count > sizeof(optstr))
 520                 return -EINVAL;
 521         if (copy_from_user(optstr, user, count))
 522                 return -EFAULT;
 523         optstr[count - 1] = '\0';
 524         sn2_flush_opt = simple_strtoul(optstr, NULL, 0);
 525
 526         for_each_online_cpu(cpu)
 527                 memset(&per_cpu(ptcstats, cpu), 0, sizeof(struct ptc_stats));
 528
 529         return count;
 530 }
 531
 532 static const struct seq_operations sn2_ptc_seq_ops = {
 533         .start = sn2_ptc_seq_start,
 534         .next = sn2_ptc_seq_next,
 535         .stop = sn2_ptc_seq_stop,
 536         .show = sn2_ptc_seq_show
 537 };
 538
 539 static int sn2_ptc_proc_open(struct inode *inode, struct file *file)
 540 {
 541         return seq_open(file, &sn2_ptc_seq_ops);
 542 }
 543
 544 static const struct file_operations proc_sn2_ptc_operations = {
 545         .open = sn2_ptc_proc_open,
 546         .read = seq_read,
 547         .write = sn2_ptc_proc_write,
 548         .llseek = seq_lseek,
 549         .release = seq_release,
 550 };
 551
 552 static struct proc_dir_entry *proc_sn2_ptc;
 553
 554 static int __init sn2_ptc_init(void)
 555 {
 556         if (!ia64_platform_is("sn2"))
 557                 return 0;
 558
 559         proc_sn2_ptc = proc_create(PTC_BASENAME, 0444,
 560                                    NULL, &proc_sn2_ptc_operations);
 561         if (!proc_sn2_ptc) {
 562                 printk(KERN_ERR "unable to create %s proc entry", PTC_BASENAME);
 563                 return -EINVAL;
 564         }
 565         spin_lock_init(&sn2_global_ptc_lock);
 566         return 0;
 567 }
 568
 569 static void __exit sn2_ptc_exit(void)
 570 {
 571         remove_proc_entry(PTC_BASENAME, NULL);
 572 }
 573
 574 module_init(sn2_ptc_init);
 575 module_exit(sn2_ptc_exit);
 576 #endif /* CONFIG_PROC_FS */
 577