1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __iop_fifo_in_defs_h
3 #define __iop_fifo_in_defs_h
6 * This file is autogenerated from
7 * file: ../../inst/io_proc/rtl/iop_fifo_in.r
9 * last modfied: Mon Apr 11 16:10:07 2005
11 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r
12 * id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
13 * Any changes here will be lost.
15 * -*- buffer-read-only: t -*-
17 /* Main access macros */
19 #define REG_RD( scope, inst, reg ) \
20 REG_READ( reg_##scope##_##reg, \
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \
26 REG_WRITE( reg_##scope##_##reg, \
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \
32 REG_READ( reg_##scope##_##reg, \
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 (index) * STRIDE_##scope##_##reg )
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 REG_WRITE( reg_##scope##_##reg, \
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 (index) * STRIDE_##scope##_##reg, (val) )
45 #define REG_RD_INT( scope, inst, reg ) \
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
50 #define REG_WR_INT( scope, inst, reg, val ) \
51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #ifndef REG_RD_INT_VECT
55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 (index) * STRIDE_##scope##_##reg )
60 #ifndef REG_WR_INT_VECT
61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
63 (index) * STRIDE_##scope##_##reg, (val) )
67 #define REG_TYPE_CONV( type, orgtype, val ) \
68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
72 #define reg_page_size 8192
76 #define REG_ADDR( scope, inst, reg ) \
77 ( (inst) + REG_RD_ADDR_##scope##_##reg )
81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
83 (index) * STRIDE_##scope##_##reg )
86 /* C-code for register scope iop_fifo_in */
88 /* Register rw_cfg, scope iop_fifo_in, type rw */
90 unsigned int avail_lim : 3;
91 unsigned int byte_order : 2;
92 unsigned int trig : 2;
93 unsigned int last_dis_dif_in : 1;
94 unsigned int mode : 2;
95 unsigned int dummy1 : 22;
96 } reg_iop_fifo_in_rw_cfg;
97 #define REG_RD_ADDR_iop_fifo_in_rw_cfg 0
98 #define REG_WR_ADDR_iop_fifo_in_rw_cfg 0
100 /* Register rw_ctrl, scope iop_fifo_in, type rw */
102 unsigned int dif_in_en : 1;
103 unsigned int dif_out_en : 1;
104 unsigned int dummy1 : 30;
105 } reg_iop_fifo_in_rw_ctrl;
106 #define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4
107 #define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4
109 /* Register r_stat, scope iop_fifo_in, type r */
111 unsigned int avail_bytes : 4;
112 unsigned int last : 8;
113 unsigned int dif_in_en : 1;
114 unsigned int dif_out_en : 1;
115 unsigned int dummy1 : 18;
116 } reg_iop_fifo_in_r_stat;
117 #define REG_RD_ADDR_iop_fifo_in_r_stat 8
119 /* Register rs_rd1byte, scope iop_fifo_in, type rs */
121 unsigned int data : 8;
122 unsigned int dummy1 : 24;
123 } reg_iop_fifo_in_rs_rd1byte;
124 #define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12
126 /* Register r_rd1byte, scope iop_fifo_in, type r */
128 unsigned int data : 8;
129 unsigned int dummy1 : 24;
130 } reg_iop_fifo_in_r_rd1byte;
131 #define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16
133 /* Register rs_rd2byte, scope iop_fifo_in, type rs */
135 unsigned int data : 16;
136 unsigned int dummy1 : 16;
137 } reg_iop_fifo_in_rs_rd2byte;
138 #define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20
140 /* Register r_rd2byte, scope iop_fifo_in, type r */
142 unsigned int data : 16;
143 unsigned int dummy1 : 16;
144 } reg_iop_fifo_in_r_rd2byte;
145 #define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24
147 /* Register rs_rd3byte, scope iop_fifo_in, type rs */
149 unsigned int data : 24;
150 unsigned int dummy1 : 8;
151 } reg_iop_fifo_in_rs_rd3byte;
152 #define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28
154 /* Register r_rd3byte, scope iop_fifo_in, type r */
156 unsigned int data : 24;
157 unsigned int dummy1 : 8;
158 } reg_iop_fifo_in_r_rd3byte;
159 #define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32
161 /* Register rs_rd4byte, scope iop_fifo_in, type rs */
163 unsigned int data : 32;
164 } reg_iop_fifo_in_rs_rd4byte;
165 #define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36
167 /* Register r_rd4byte, scope iop_fifo_in, type r */
169 unsigned int data : 32;
170 } reg_iop_fifo_in_r_rd4byte;
171 #define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40
173 /* Register rw_set_last, scope iop_fifo_in, type rw */
174 typedef unsigned int reg_iop_fifo_in_rw_set_last;
175 #define REG_RD_ADDR_iop_fifo_in_rw_set_last 44
176 #define REG_WR_ADDR_iop_fifo_in_rw_set_last 44
178 /* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
180 unsigned int last : 2;
181 unsigned int dummy1 : 30;
182 } reg_iop_fifo_in_rw_strb_dif_in;
183 #define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48
184 #define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48
186 /* Register rw_intr_mask, scope iop_fifo_in, type rw */
188 unsigned int urun : 1;
189 unsigned int last_data : 1;
190 unsigned int dav : 1;
191 unsigned int avail : 1;
192 unsigned int orun : 1;
193 unsigned int dummy1 : 27;
194 } reg_iop_fifo_in_rw_intr_mask;
195 #define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52
196 #define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52
198 /* Register rw_ack_intr, scope iop_fifo_in, type rw */
200 unsigned int urun : 1;
201 unsigned int last_data : 1;
202 unsigned int dav : 1;
203 unsigned int avail : 1;
204 unsigned int orun : 1;
205 unsigned int dummy1 : 27;
206 } reg_iop_fifo_in_rw_ack_intr;
207 #define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56
208 #define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56
210 /* Register r_intr, scope iop_fifo_in, type r */
212 unsigned int urun : 1;
213 unsigned int last_data : 1;
214 unsigned int dav : 1;
215 unsigned int avail : 1;
216 unsigned int orun : 1;
217 unsigned int dummy1 : 27;
218 } reg_iop_fifo_in_r_intr;
219 #define REG_RD_ADDR_iop_fifo_in_r_intr 60
221 /* Register r_masked_intr, scope iop_fifo_in, type r */
223 unsigned int urun : 1;
224 unsigned int last_data : 1;
225 unsigned int dav : 1;
226 unsigned int avail : 1;
227 unsigned int orun : 1;
228 unsigned int dummy1 : 27;
229 } reg_iop_fifo_in_r_masked_intr;
230 #define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64
235 regk_iop_fifo_in_dif_in = 0x00000002,
236 regk_iop_fifo_in_hi = 0x00000000,
237 regk_iop_fifo_in_neg = 0x00000002,
238 regk_iop_fifo_in_no = 0x00000000,
239 regk_iop_fifo_in_order16 = 0x00000001,
240 regk_iop_fifo_in_order24 = 0x00000002,
241 regk_iop_fifo_in_order32 = 0x00000003,
242 regk_iop_fifo_in_order8 = 0x00000000,
243 regk_iop_fifo_in_pos = 0x00000001,
244 regk_iop_fifo_in_pos_neg = 0x00000003,
245 regk_iop_fifo_in_rw_cfg_default = 0x00000024,
246 regk_iop_fifo_in_rw_ctrl_default = 0x00000000,
247 regk_iop_fifo_in_rw_intr_mask_default = 0x00000000,
248 regk_iop_fifo_in_rw_set_last_default = 0x00000000,
249 regk_iop_fifo_in_rw_strb_dif_in_default = 0x00000000,
250 regk_iop_fifo_in_size16 = 0x00000002,
251 regk_iop_fifo_in_size24 = 0x00000001,
252 regk_iop_fifo_in_size32 = 0x00000000,
253 regk_iop_fifo_in_size8 = 0x00000003,
254 regk_iop_fifo_in_yes = 0x00000001
256 #endif /* __iop_fifo_in_defs_h */