arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __iop_sap_in_defs_asm_h
   3 #define __iop_sap_in_defs_asm_h
   4
   5 /*
   6  * This file is autogenerated from
   7  *   file:           ../../inst/io_proc/rtl/iop_sap_in.r
   8  *     id:           <not found>
   9  *     last modfied: Mon Apr 11 16:08:45 2005
  10  *
  11  *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r
  12  *      id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
  13  * Any changes here will be lost.
  14  *
  15  * -*- buffer-read-only: t -*-
  16  */
  17
  18 #ifndef REG_FIELD
  19 #define REG_FIELD( scope, reg, field, value ) \
  20   REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
  21 #define REG_FIELD_X_( value, shift ) ((value) << shift)
  22 #endif
  23
  24 #ifndef REG_STATE
  25 #define REG_STATE( scope, reg, field, symbolic_value ) \
  26   REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
  27 #define REG_STATE_X_( k, shift ) (k << shift)
  28 #endif
  29
  30 #ifndef REG_MASK
  31 #define REG_MASK( scope, reg, field ) \
  32   REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
  33 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
  34 #endif
  35
  36 #ifndef REG_LSB
  37 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
  38 #endif
  39
  40 #ifndef REG_BIT
  41 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
  42 #endif
  43
  44 #ifndef REG_ADDR
  45 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
  46 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
  47 #endif
  48
  49 #ifndef REG_ADDR_VECT
  50 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  51          REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
  52                          STRIDE_##scope##_##reg )
  53 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
  54                           ((inst) + offs + (index) * stride)
  55 #endif
  56
  57 /* Register rw_bus0_sync, scope iop_sap_in, type rw */
  58 #define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0
  59 #define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2
  60 #define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2
  61 #define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3
  62 #define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5
  63 #define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2
  64 #define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7
  65 #define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1
  66 #define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7
  67 #define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8
  68 #define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2
  69 #define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10
  70 #define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3
  71 #define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13
  72 #define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2
  73 #define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15
  74 #define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1
  75 #define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15
  76 #define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16
  77 #define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2
  78 #define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18
  79 #define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3
  80 #define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21
  81 #define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2
  82 #define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23
  83 #define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1
  84 #define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23
  85 #define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24
  86 #define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2
  87 #define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26
  88 #define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3
  89 #define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29
  90 #define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2
  91 #define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31
  92 #define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1
  93 #define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31
  94 #define reg_iop_sap_in_rw_bus0_sync_offset 0
  95
  96 /* Register rw_bus1_sync, scope iop_sap_in, type rw */
  97 #define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0
  98 #define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2
  99 #define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2
 100 #define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3
 101 #define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5
 102 #define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2
 103 #define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7
 104 #define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1
 105 #define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7
 106 #define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8
 107 #define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2
 108 #define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10
 109 #define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3
 110 #define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13
 111 #define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2
 112 #define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15
 113 #define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1
 114 #define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15
 115 #define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16
 116 #define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2
 117 #define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18
 118 #define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3
 119 #define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21
 120 #define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2
 121 #define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23
 122 #define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1
 123 #define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23
 124 #define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24
 125 #define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2
 126 #define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26
 127 #define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3
 128 #define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29
 129 #define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2
 130 #define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31
 131 #define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1
 132 #define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31
 133 #define reg_iop_sap_in_rw_bus1_sync_offset 4
 134
 135 #define STRIDE_iop_sap_in_rw_gio 4
 136 /* Register rw_gio, scope iop_sap_in, type rw */
 137 #define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
 138 #define reg_iop_sap_in_rw_gio___sync_sel___width 2
 139 #define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
 140 #define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
 141 #define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
 142 #define reg_iop_sap_in_rw_gio___sync_edge___width 2
 143 #define reg_iop_sap_in_rw_gio___delay___lsb 7
 144 #define reg_iop_sap_in_rw_gio___delay___width 1
 145 #define reg_iop_sap_in_rw_gio___delay___bit 7
 146 #define reg_iop_sap_in_rw_gio___logic___lsb 8
 147 #define reg_iop_sap_in_rw_gio___logic___width 2
 148 #define reg_iop_sap_in_rw_gio_offset 8
 149
 150
 151 /* Constants */
 152 #define regk_iop_sap_in_and                       0x00000002
 153 #define regk_iop_sap_in_ext_clk200                0x00000003
 154 #define regk_iop_sap_in_gio1                      0x00000000
 155 #define regk_iop_sap_in_gio13                     0x00000005
 156 #define regk_iop_sap_in_gio18                     0x00000003
 157 #define regk_iop_sap_in_gio19                     0x00000004
 158 #define regk_iop_sap_in_gio21                     0x00000006
 159 #define regk_iop_sap_in_gio23                     0x00000005
 160 #define regk_iop_sap_in_gio29                     0x00000007
 161 #define regk_iop_sap_in_gio5                      0x00000004
 162 #define regk_iop_sap_in_gio6                      0x00000001
 163 #define regk_iop_sap_in_gio7                      0x00000002
 164 #define regk_iop_sap_in_inv                       0x00000001
 165 #define regk_iop_sap_in_neg                       0x00000002
 166 #define regk_iop_sap_in_no                        0x00000000
 167 #define regk_iop_sap_in_no_del_ext_clk200         0x00000001
 168 #define regk_iop_sap_in_none                      0x00000000
 169 #define regk_iop_sap_in_or                        0x00000003
 170 #define regk_iop_sap_in_pos                       0x00000001
 171 #define regk_iop_sap_in_pos_neg                   0x00000003
 172 #define regk_iop_sap_in_rw_bus0_sync_default      0x02020202
 173 #define regk_iop_sap_in_rw_bus1_sync_default      0x02020202
 174 #define regk_iop_sap_in_rw_gio_default            0x00000002
 175 #define regk_iop_sap_in_rw_gio_size               0x00000020
 176 #define regk_iop_sap_in_timer_grp0_tmr3           0x00000006
 177 #define regk_iop_sap_in_timer_grp1_tmr3           0x00000004
 178 #define regk_iop_sap_in_timer_grp2_tmr3           0x00000005
 179 #define regk_iop_sap_in_timer_grp3_tmr3           0x00000007
 180 #define regk_iop_sap_in_tmr_clk200                0x00000000
 181 #define regk_iop_sap_in_two_clk200                0x00000002
 182 #define regk_iop_sap_in_yes                       0x00000001
 183 #endif /* __iop_sap_in_defs_asm_h */