2 * Based on arch/arm/mm/proc.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
23 #include <asm/assembler.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/hwcap.h>
26 #include <asm/pgtable.h>
27 #include <asm/pgtable-hwdef.h>
28 #include <asm/cpufeature.h>
29 #include <asm/alternative.h>
31 #ifdef CONFIG_ARM64_64K_PAGES
32 #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
33 #elif defined(CONFIG_ARM64_16K_PAGES)
34 #define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
35 #else /* CONFIG_ARM64_4K_PAGES */
36 #define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
39 #ifdef CONFIG_RANDOMIZE_BASE
40 #define TCR_KASLR_FLAGS TCR_NFD1
42 #define TCR_KASLR_FLAGS 0
45 #define TCR_SMP_FLAGS TCR_SHARED
47 /* PTWs cacheable, inner/outer WBWA */
48 #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
50 #ifdef CONFIG_KASAN_SW_TAGS
51 #define TCR_KASAN_FLAGS TCR_TBI1
53 #define TCR_KASAN_FLAGS 0
56 #define MAIR(attr, mt) ((attr) << ((mt) * 8))
61 * Idle the processor (wait for interrupt).
64 dsb sy // WFI may enter a low-power mode
71 * cpu_do_suspend - save CPU registers context
73 * x0: virtual address of context pointer
78 mrs x4, contextidr_el1
85 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
92 stp x4, xzr, [x0, #16]
95 stp x9, x10, [x0, #64]
96 stp x11, x12, [x0, #80]
98 ENDPROC(cpu_do_suspend)
101 * cpu_do_resume - restore CPU register context
103 * x0: Address of context pointer
105 .pushsection ".idmap.text", "awx"
108 ldp x4, x5, [x0, #16]
109 ldp x6, x8, [x0, #32]
110 ldp x9, x10, [x0, #48]
111 ldp x11, x12, [x0, #64]
112 ldp x13, x14, [x0, #80]
115 msr contextidr_el1, x4
118 /* Don't change t0sz here, mask those bits when restoring */
120 bfi x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
126 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
127 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
128 * exception. Mask them until local_daif_restore() in cpu_suspend()
135 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
142 * Restore oslsr_el1 by writing oslar_el1
144 ubfx x11, x11, #1, #1
146 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
148 alternative_if ARM64_HAS_RAS_EXTN
149 msr_s SYS_DISR_EL1, xzr
150 alternative_else_nop_endif
154 ENDPROC(cpu_do_resume)
159 * cpu_do_switch_mm(pgd_phys, tsk)
161 * Set the translation table base pointer to be pgd_phys.
163 * - pgd_phys - physical address of new TTB
165 ENTRY(cpu_do_switch_mm)
167 mmid x1, x1 // get mm->context.id
170 alternative_if ARM64_HAS_CNP
171 cbz x1, 1f // skip CNP for reserved ASID
172 orr x3, x3, #TTBR_CNP_BIT
174 alternative_else_nop_endif
175 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
176 bfi x3, x1, #48, #16 // set the ASID field in TTBR0
178 bfi x2, x1, #48, #16 // set the ASID
179 msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set)
181 msr ttbr0_el1, x3 // now update TTBR0
183 b post_ttbr_update_workaround // Back to C code...
184 ENDPROC(cpu_do_switch_mm)
186 .pushsection ".idmap.text", "awx"
188 .macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
189 adrp \tmp1, empty_zero_page
190 phys_to_ttbr \tmp2, \tmp1
200 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
202 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
203 * called by anything else. It can only be executed from a TTBR0 mapping.
205 ENTRY(idmap_cpu_replace_ttbr1)
206 save_and_disable_daif flags=x2
208 __idmap_cpu_set_reserved_ttbr1 x1, x3
217 ENDPROC(idmap_cpu_replace_ttbr1)
220 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
221 .pushsection ".idmap.text", "awx"
223 .macro __idmap_kpti_get_pgtable_ent, type
224 dc cvac, cur_\()\type\()p // Ensure any existing dirty
225 dmb sy // lines are written back before
226 ldr \type, [cur_\()\type\()p] // loading the entry
227 tbz \type, #0, skip_\()\type // Skip invalid and
228 tbnz \type, #11, skip_\()\type // non-global entries
231 .macro __idmap_kpti_put_pgtable_ent_ng, type
232 orr \type, \type, #PTE_NG // Same bit for blocks and pages
233 str \type, [cur_\()\type\()p] // Update the entry and ensure
234 dmb sy // that it is visible to all
235 dc civac, cur_\()\type\()p // CPUs.
239 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
241 * Called exactly once from stop_machine context by each CPU found during boot.
245 ENTRY(idmap_kpti_install_ng_mappings)
264 mrs swapper_ttb, ttbr1_el1
265 restore_ttbr1 swapper_ttb
266 adr flag_ptr, __idmap_kpti_flag
268 cbnz cpu, __idmap_kpti_secondary
270 /* We're the boot CPU. Wait for the others to catch up */
273 ldaxr w18, [flag_ptr]
274 eor w18, w18, num_cpus
277 /* We need to walk swapper, so turn off the MMU. */
278 pre_disable_mmu_workaround
280 bic x18, x18, #SCTLR_ELx_M
284 /* Everybody is enjoying the idmap, so we can rewrite swapper. */
286 mov cur_pgdp, swapper_pa
287 add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
288 do_pgd: __idmap_kpti_get_pgtable_ent pgd
289 tbnz pgd, #1, walk_puds
291 __idmap_kpti_put_pgtable_ent_ng pgd
293 add cur_pgdp, cur_pgdp, #8
294 cmp cur_pgdp, end_pgdp
297 /* Publish the updated tables and nuke all the TLBs */
303 /* We're done: fire up the MMU again */
305 orr x18, x18, #SCTLR_ELx_M
309 /* Set the flag to zero to indicate that we're all done */
315 .if CONFIG_PGTABLE_LEVELS > 3
316 pte_to_phys cur_pudp, pgd
317 add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
318 do_pud: __idmap_kpti_get_pgtable_ent pud
319 tbnz pud, #1, walk_pmds
321 __idmap_kpti_put_pgtable_ent_ng pud
323 add cur_pudp, cur_pudp, 8
324 cmp cur_pudp, end_pudp
327 .else /* CONFIG_PGTABLE_LEVELS <= 3 */
336 .if CONFIG_PGTABLE_LEVELS > 2
337 pte_to_phys cur_pmdp, pud
338 add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
339 do_pmd: __idmap_kpti_get_pgtable_ent pmd
340 tbnz pmd, #1, walk_ptes
342 __idmap_kpti_put_pgtable_ent_ng pmd
344 add cur_pmdp, cur_pmdp, #8
345 cmp cur_pmdp, end_pmdp
348 .else /* CONFIG_PGTABLE_LEVELS <= 2 */
357 pte_to_phys cur_ptep, pmd
358 add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
359 do_pte: __idmap_kpti_get_pgtable_ent pte
360 __idmap_kpti_put_pgtable_ent_ng pte
362 add cur_ptep, cur_ptep, #8
363 cmp cur_ptep, end_ptep
367 /* Secondary CPUs end up here */
368 __idmap_kpti_secondary:
369 /* Uninstall swapper before surgery begins */
370 __idmap_cpu_set_reserved_ttbr1 x18, x17
372 /* Increment the flag to let the boot CPU we're ready */
373 1: ldxr w18, [flag_ptr]
375 stxr w17, w18, [flag_ptr]
378 /* Wait for the boot CPU to finish messing around with swapper */
384 /* All done, act like nothing happened */
385 offset_ttbr1 swapper_ttb
386 msr ttbr1_el1, swapper_ttb
407 ENDPROC(idmap_kpti_install_ng_mappings)
414 * Initialise the processor for turning the MMU on. Return in x0 the
415 * value of the SCTLR_EL1 register.
417 .pushsection ".idmap.text", "awx"
419 tlbi vmalle1 // Invalidate local TLB
423 msr cpacr_el1, x0 // Enable FP/ASIMD
424 mov x0, #1 << 12 // Reset mdscr_el1 and disable
425 msr mdscr_el1, x0 // access to the DCC from EL0
426 isb // Unmask debug exceptions now,
427 enable_dbg // since this is per-cpu
428 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
430 * Memory region attributes for LPAE:
434 * DEVICE_nGnRnE 000 00000000
435 * DEVICE_nGnRE 001 00000100
436 * DEVICE_GRE 010 00001100
437 * NORMAL_NC 011 01000100
438 * NORMAL 100 11111111
439 * NORMAL_WT 101 10111011
441 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
442 MAIR(0x04, MT_DEVICE_nGnRE) | \
443 MAIR(0x0c, MT_DEVICE_GRE) | \
444 MAIR(0x44, MT_NORMAL_NC) | \
445 MAIR(0xff, MT_NORMAL) | \
446 MAIR(0xbb, MT_NORMAL_WT)
451 mov_q x0, SCTLR_EL1_SET
453 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
454 * both user and kernel.
456 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
457 TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
458 TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS
460 #ifdef CONFIG_ARM64_USER_VA_BITS_52
461 ldr_l x9, vabits_user
470 * Set the IPS bits in TCR_EL1.
472 tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
473 #ifdef CONFIG_ARM64_HW_AFDBM
475 * Enable hardware update of the Access Flags bit.
476 * Hardware dirty bit management is enabled later,
479 mrs x9, ID_AA64MMFR1_EL1
482 orr x10, x10, #TCR_HA // hardware Access flag update
484 #endif /* CONFIG_ARM64_HW_AFDBM */
486 ret // return to head.S