2 * Copyright (C) 2015 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/arm-smccc.h>
19 #include <linux/types.h>
20 #include <linux/jump_label.h>
21 #include <uapi/linux/psci.h>
23 #include <kvm/arm_psci.h>
25 #include <asm/cpufeature.h>
26 #include <asm/kvm_asm.h>
27 #include <asm/kvm_emulate.h>
28 #include <asm/kvm_host.h>
29 #include <asm/kvm_hyp.h>
30 #include <asm/kvm_mmu.h>
31 #include <asm/fpsimd.h>
32 #include <asm/debug-monitors.h>
33 #include <asm/processor.h>
34 #include <asm/thread_info.h>
36 /* Check whether the FP regs were dirtied while in the host-side run loop: */
37 static bool __hyp_text update_fp_enabled(struct kvm_vcpu *vcpu)
39 if (vcpu->arch.host_thread_info->flags & _TIF_FOREIGN_FPSTATE)
40 vcpu->arch.flags &= ~(KVM_ARM64_FP_ENABLED |
43 return !!(vcpu->arch.flags & KVM_ARM64_FP_ENABLED);
46 /* Save the 32-bit only FPSIMD system register state */
47 static void __hyp_text __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
49 if (!vcpu_el1_is_32bit(vcpu))
52 vcpu->arch.ctxt.sys_regs[FPEXC32_EL2] = read_sysreg(fpexc32_el2);
55 static void __hyp_text __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
58 * We are about to set CPTR_EL2.TFP to trap all floating point
59 * register accesses to EL2, however, the ARM ARM clearly states that
60 * traps are only taken to EL2 if the operation would not otherwise
61 * trap to EL1. Therefore, always make sure that for 32-bit guests,
62 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
63 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
64 * it will cause an exception.
66 if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
67 write_sysreg(1 << 30, fpexc32_el2);
72 static void __hyp_text __activate_traps_common(struct kvm_vcpu *vcpu)
74 /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
75 write_sysreg(1 << 15, hstr_el2);
78 * Make sure we trap PMU access from EL0 to EL2. Also sanitize
79 * PMSELR_EL0 to make sure it never contains the cycle
80 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
81 * EL1 instead of being trapped to EL2.
83 write_sysreg(0, pmselr_el0);
84 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
85 write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
88 static void __hyp_text __deactivate_traps_common(void)
90 write_sysreg(0, hstr_el2);
91 write_sysreg(0, pmuserenr_el0);
94 static void activate_traps_vhe(struct kvm_vcpu *vcpu)
98 val = read_sysreg(cpacr_el1);
100 val &= ~CPACR_EL1_ZEN;
101 if (!update_fp_enabled(vcpu)) {
102 val &= ~CPACR_EL1_FPEN;
103 __activate_traps_fpsimd32(vcpu);
106 write_sysreg(val, cpacr_el1);
108 write_sysreg(kvm_get_hyp_vector(), vbar_el1);
111 static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu)
115 __activate_traps_common(vcpu);
117 val = CPTR_EL2_DEFAULT;
118 val |= CPTR_EL2_TTA | CPTR_EL2_TZ;
119 if (!update_fp_enabled(vcpu)) {
121 __activate_traps_fpsimd32(vcpu);
124 write_sysreg(val, cptr_el2);
127 static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
129 u64 hcr = vcpu->arch.hcr_el2;
131 write_sysreg(hcr, hcr_el2);
133 if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
134 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
137 activate_traps_vhe(vcpu);
139 __activate_traps_nvhe(vcpu);
142 static void deactivate_traps_vhe(void)
144 extern char vectors[]; /* kernel exception vectors */
145 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
148 * ARM erratum 1165522 requires the actual execution of the above
149 * before we can switch to the EL2/EL0 translation regime used by
152 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_1165522));
154 write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
155 write_sysreg(vectors, vbar_el1);
158 static void __hyp_text __deactivate_traps_nvhe(void)
160 u64 mdcr_el2 = read_sysreg(mdcr_el2);
162 __deactivate_traps_common();
164 mdcr_el2 &= MDCR_EL2_HPMN_MASK;
165 mdcr_el2 |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT;
167 write_sysreg(mdcr_el2, mdcr_el2);
168 write_sysreg(HCR_RW, hcr_el2);
169 write_sysreg(CPTR_EL2_DEFAULT, cptr_el2);
172 static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
175 * If we pended a virtual abort, preserve it until it gets
176 * cleared. See D1.14.3 (Virtual Interrupts) for details, but
177 * the crucial bit is "On taking a vSError interrupt,
178 * HCR_EL2.VSE is cleared to 0."
180 if (vcpu->arch.hcr_el2 & HCR_VSE)
181 vcpu->arch.hcr_el2 = read_sysreg(hcr_el2);
184 deactivate_traps_vhe();
186 __deactivate_traps_nvhe();
189 void activate_traps_vhe_load(struct kvm_vcpu *vcpu)
191 __activate_traps_common(vcpu);
194 void deactivate_traps_vhe_put(void)
196 u64 mdcr_el2 = read_sysreg(mdcr_el2);
198 mdcr_el2 &= MDCR_EL2_HPMN_MASK |
199 MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT |
202 write_sysreg(mdcr_el2, mdcr_el2);
204 __deactivate_traps_common();
207 static void __hyp_text __activate_vm(struct kvm *kvm)
209 __load_guest_stage2(kvm);
212 static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
214 write_sysreg(0, vttbr_el2);
217 /* Save VGICv3 state on non-VHE systems */
218 static void __hyp_text __hyp_vgic_save_state(struct kvm_vcpu *vcpu)
220 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
221 __vgic_v3_save_state(vcpu);
222 __vgic_v3_deactivate_traps(vcpu);
226 /* Restore VGICv3 state on non_VEH systems */
227 static void __hyp_text __hyp_vgic_restore_state(struct kvm_vcpu *vcpu)
229 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
230 __vgic_v3_activate_traps(vcpu);
231 __vgic_v3_restore_state(vcpu);
235 static bool __hyp_text __true_value(void)
240 static bool __hyp_text __false_value(void)
245 static hyp_alternate_select(__check_arm_834220,
246 __false_value, __true_value,
247 ARM64_WORKAROUND_834220);
249 static bool __hyp_text __translate_far_to_hpfar(u64 far, u64 *hpfar)
254 * Resolve the IPA the hard way using the guest VA.
256 * Stage-1 translation already validated the memory access
257 * rights. As such, we can use the EL1 translation regime, and
258 * don't have to distinguish between EL0 and EL1 access.
260 * We do need to save/restore PAR_EL1 though, as we haven't
261 * saved the guest context yet, and we may return early...
263 par = read_sysreg(par_el1);
264 asm volatile("at s1e1r, %0" : : "r" (far));
267 tmp = read_sysreg(par_el1);
268 write_sysreg(par, par_el1);
270 if (unlikely(tmp & 1))
271 return false; /* Translation failed, back to guest */
273 /* Convert PAR to HPFAR format */
274 *hpfar = PAR_TO_HPFAR(tmp);
278 static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
284 esr = vcpu->arch.fault.esr_el2;
285 ec = ESR_ELx_EC(esr);
287 if (ec != ESR_ELx_EC_DABT_LOW && ec != ESR_ELx_EC_IABT_LOW)
290 far = read_sysreg_el2(far);
293 * The HPFAR can be invalid if the stage 2 fault did not
294 * happen during a stage 1 page table walk (the ESR_EL2.S1PTW
295 * bit is clear) and one of the two following cases are true:
296 * 1. The fault was due to a permission fault
297 * 2. The processor carries errata 834220
299 * Therefore, for all non S1PTW faults where we either have a
300 * permission fault or the errata workaround is enabled, we
301 * resolve the IPA using the AT instruction.
303 if (!(esr & ESR_ELx_S1PTW) &&
304 (__check_arm_834220()() || (esr & ESR_ELx_FSC_TYPE) == FSC_PERM)) {
305 if (!__translate_far_to_hpfar(far, &hpfar))
308 hpfar = read_sysreg(hpfar_el2);
311 vcpu->arch.fault.far_el2 = far;
312 vcpu->arch.fault.hpfar_el2 = hpfar;
316 /* Skip an instruction which has been emulated. Returns true if
317 * execution can continue or false if we need to exit hyp mode because
318 * single-step was in effect.
320 static bool __hyp_text __skip_instr(struct kvm_vcpu *vcpu)
322 *vcpu_pc(vcpu) = read_sysreg_el2(elr);
324 if (vcpu_mode_is_32bit(vcpu)) {
325 vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(spsr);
326 kvm_skip_instr32(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
327 write_sysreg_el2(vcpu->arch.ctxt.gp_regs.regs.pstate, spsr);
332 write_sysreg_el2(*vcpu_pc(vcpu), elr);
334 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
335 vcpu->arch.fault.esr_el2 =
336 (ESR_ELx_EC_SOFTSTP_LOW << ESR_ELx_EC_SHIFT) | 0x22;
343 static bool __hyp_text __hyp_switch_fpsimd(struct kvm_vcpu *vcpu)
345 struct user_fpsimd_state *host_fpsimd = vcpu->arch.host_fpsimd_state;
348 write_sysreg(read_sysreg(cpacr_el1) | CPACR_EL1_FPEN,
351 write_sysreg(read_sysreg(cptr_el2) & ~(u64)CPTR_EL2_TFP,
356 if (vcpu->arch.flags & KVM_ARM64_FP_HOST) {
358 * In the SVE case, VHE is assumed: it is enforced by
359 * Kconfig and kvm_arch_init().
361 if (system_supports_sve() &&
362 (vcpu->arch.flags & KVM_ARM64_HOST_SVE_IN_USE)) {
363 struct thread_struct *thread = container_of(
365 struct thread_struct, uw.fpsimd_state);
367 sve_save_state(sve_pffr(thread), &host_fpsimd->fpsr);
369 __fpsimd_save_state(host_fpsimd);
372 vcpu->arch.flags &= ~KVM_ARM64_FP_HOST;
375 __fpsimd_restore_state(&vcpu->arch.ctxt.gp_regs.fp_regs);
377 /* Skip restoring fpexc32 for AArch64 guests */
378 if (!(read_sysreg(hcr_el2) & HCR_RW))
379 write_sysreg(vcpu->arch.ctxt.sys_regs[FPEXC32_EL2],
382 vcpu->arch.flags |= KVM_ARM64_FP_ENABLED;
388 * Return true when we were able to fixup the guest exit and should return to
389 * the guest, false when we should restore the host state and return to the
392 static bool __hyp_text fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
394 if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
395 vcpu->arch.fault.esr_el2 = read_sysreg_el2(esr);
398 * We're using the raw exception code in order to only process
399 * the trap if no SError is pending. We will come back to the
400 * same PC once the SError has been injected, and replay the
401 * trapping instruction.
403 if (*exit_code != ARM_EXCEPTION_TRAP)
407 * We trap the first access to the FP/SIMD to save the host context
408 * and restore the guest context lazily.
409 * If FP/SIMD is not implemented, handle the trap and inject an
410 * undefined instruction exception to the guest.
412 if (system_supports_fpsimd() &&
413 kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_FP_ASIMD)
414 return __hyp_switch_fpsimd(vcpu);
416 if (!__populate_fault_info(vcpu))
419 if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
422 valid = kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_DABT_LOW &&
423 kvm_vcpu_trap_get_fault_type(vcpu) == FSC_FAULT &&
424 kvm_vcpu_dabt_isvalid(vcpu) &&
425 !kvm_vcpu_dabt_isextabt(vcpu) &&
426 !kvm_vcpu_dabt_iss1tw(vcpu);
429 int ret = __vgic_v2_perform_cpuif_access(vcpu);
431 if (ret == 1 && __skip_instr(vcpu))
435 /* Promote an illegal access to an
436 * SError. If we would be returning
437 * due to single-step clear the SS
438 * bit so handle_exit knows what to
439 * do after dealing with the error.
441 if (!__skip_instr(vcpu))
442 *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
443 *exit_code = ARM_EXCEPTION_EL1_SERROR;
450 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
451 (kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 ||
452 kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_CP15_32)) {
453 int ret = __vgic_v3_perform_cpuif_access(vcpu);
455 if (ret == 1 && __skip_instr(vcpu))
460 /* Return to the host kernel and handle the exit */
464 static inline bool __hyp_text __needs_ssbd_off(struct kvm_vcpu *vcpu)
466 if (!cpus_have_const_cap(ARM64_SSBD))
469 return !(vcpu->arch.workaround_flags & VCPU_WORKAROUND_2_FLAG);
472 static void __hyp_text __set_guest_arch_workaround_state(struct kvm_vcpu *vcpu)
474 #ifdef CONFIG_ARM64_SSBD
476 * The host runs with the workaround always present. If the
477 * guest wants it disabled, so be it...
479 if (__needs_ssbd_off(vcpu) &&
480 __hyp_this_cpu_read(arm64_ssbd_callback_required))
481 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 0, NULL);
485 static void __hyp_text __set_host_arch_workaround_state(struct kvm_vcpu *vcpu)
487 #ifdef CONFIG_ARM64_SSBD
489 * If the guest has disabled the workaround, bring it back on.
491 if (__needs_ssbd_off(vcpu) &&
492 __hyp_this_cpu_read(arm64_ssbd_callback_required))
493 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 1, NULL);
497 /* Switch to the guest for VHE systems running in EL2 */
498 int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
500 struct kvm_cpu_context *host_ctxt;
501 struct kvm_cpu_context *guest_ctxt;
504 host_ctxt = vcpu->arch.host_cpu_context;
505 host_ctxt->__hyp_running_vcpu = vcpu;
506 guest_ctxt = &vcpu->arch.ctxt;
508 sysreg_save_host_state_vhe(host_ctxt);
511 * ARM erratum 1165522 requires us to configure both stage 1 and
512 * stage 2 translation for the guest context before we clear
515 * We have already configured the guest's stage 1 translation in
516 * kvm_vcpu_load_sysregs above. We must now call __activate_vm
517 * before __activate_traps, because __activate_vm configures
518 * stage 2 translation, and __activate_traps clear HCR_EL2.TGE
519 * (among other things).
521 __activate_vm(vcpu->kvm);
522 __activate_traps(vcpu);
524 sysreg_restore_guest_state_vhe(guest_ctxt);
525 __debug_switch_to_guest(vcpu);
527 __set_guest_arch_workaround_state(vcpu);
530 /* Jump in the fire! */
531 exit_code = __guest_enter(vcpu, host_ctxt);
533 /* And we're baaack! */
534 } while (fixup_guest_exit(vcpu, &exit_code));
536 __set_host_arch_workaround_state(vcpu);
538 sysreg_save_guest_state_vhe(guest_ctxt);
540 __deactivate_traps(vcpu);
542 sysreg_restore_host_state_vhe(host_ctxt);
544 if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
545 __fpsimd_save_fpexc32(vcpu);
547 __debug_switch_to_host(vcpu);
552 /* Switch to the guest for legacy non-VHE systems */
553 int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)
555 struct kvm_cpu_context *host_ctxt;
556 struct kvm_cpu_context *guest_ctxt;
559 vcpu = kern_hyp_va(vcpu);
561 host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
562 host_ctxt->__hyp_running_vcpu = vcpu;
563 guest_ctxt = &vcpu->arch.ctxt;
565 __sysreg_save_state_nvhe(host_ctxt);
567 __activate_vm(kern_hyp_va(vcpu->kvm));
568 __activate_traps(vcpu);
570 __hyp_vgic_restore_state(vcpu);
571 __timer_enable_traps(vcpu);
574 * We must restore the 32-bit state before the sysregs, thanks
575 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
577 __sysreg32_restore_state(vcpu);
578 __sysreg_restore_state_nvhe(guest_ctxt);
579 __debug_switch_to_guest(vcpu);
581 __set_guest_arch_workaround_state(vcpu);
584 /* Jump in the fire! */
585 exit_code = __guest_enter(vcpu, host_ctxt);
587 /* And we're baaack! */
588 } while (fixup_guest_exit(vcpu, &exit_code));
590 __set_host_arch_workaround_state(vcpu);
592 __sysreg_save_state_nvhe(guest_ctxt);
593 __sysreg32_save_state(vcpu);
594 __timer_disable_traps(vcpu);
595 __hyp_vgic_save_state(vcpu);
597 __deactivate_traps(vcpu);
598 __deactivate_vm(vcpu);
600 __sysreg_restore_state_nvhe(host_ctxt);
602 if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
603 __fpsimd_save_fpexc32(vcpu);
606 * This must come after restoring the host sysregs, since a non-VHE
607 * system may enable SPE here and make use of the TTBRs.
609 __debug_switch_to_host(vcpu);
614 static const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n";
616 static void __hyp_text __hyp_call_panic_nvhe(u64 spsr, u64 elr, u64 par,
617 struct kvm_cpu_context *__host_ctxt)
619 struct kvm_vcpu *vcpu;
620 unsigned long str_va;
622 vcpu = __host_ctxt->__hyp_running_vcpu;
624 if (read_sysreg(vttbr_el2)) {
625 __timer_disable_traps(vcpu);
626 __deactivate_traps(vcpu);
627 __deactivate_vm(vcpu);
628 __sysreg_restore_state_nvhe(__host_ctxt);
632 * Force the panic string to be loaded from the literal pool,
633 * making sure it is a kernel address and not a PC-relative
636 asm volatile("ldr %0, =__hyp_panic_string" : "=r" (str_va));
638 __hyp_do_panic(str_va,
640 read_sysreg(esr_el2), read_sysreg_el2(far),
641 read_sysreg(hpfar_el2), par, vcpu);
644 static void __hyp_call_panic_vhe(u64 spsr, u64 elr, u64 par,
645 struct kvm_cpu_context *host_ctxt)
647 struct kvm_vcpu *vcpu;
648 vcpu = host_ctxt->__hyp_running_vcpu;
650 __deactivate_traps(vcpu);
651 sysreg_restore_host_state_vhe(host_ctxt);
653 panic(__hyp_panic_string,
655 read_sysreg_el2(esr), read_sysreg_el2(far),
656 read_sysreg(hpfar_el2), par, vcpu);
659 void __hyp_text __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt)
661 u64 spsr = read_sysreg_el2(spsr);
662 u64 elr = read_sysreg_el2(elr);
663 u64 par = read_sysreg(par_el1);
666 __hyp_call_panic_nvhe(spsr, elr, par, host_ctxt);
668 __hyp_call_panic_vhe(spsr, elr, par, host_ctxt);