arch/arm64/kvm/hyp/switch.c

   1 /*
   2  * Copyright (C) 2015 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/arm-smccc.h>
  19 #include <linux/types.h>
  20 #include <linux/jump_label.h>
  21 #include <uapi/linux/psci.h>
  22
  23 #include <kvm/arm_psci.h>
  24
  25 #include <asm/cpufeature.h>
  26 #include <asm/kvm_asm.h>
  27 #include <asm/kvm_emulate.h>
  28 #include <asm/kvm_host.h>
  29 #include <asm/kvm_hyp.h>
  30 #include <asm/kvm_mmu.h>
  31 #include <asm/fpsimd.h>
  32 #include <asm/debug-monitors.h>
  33 #include <asm/processor.h>
  34 #include <asm/thread_info.h>
  35
  36 /* Check whether the FP regs were dirtied while in the host-side run loop: */
  37 static bool __hyp_text update_fp_enabled(struct kvm_vcpu *vcpu)
  38 {
  39         if (vcpu->arch.host_thread_info->flags & _TIF_FOREIGN_FPSTATE)
  40                 vcpu->arch.flags &= ~(KVM_ARM64_FP_ENABLED |
  41                                       KVM_ARM64_FP_HOST);
  42
  43         return !!(vcpu->arch.flags & KVM_ARM64_FP_ENABLED);
  44 }
  45
  46 /* Save the 32-bit only FPSIMD system register state */
  47 static void __hyp_text __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
  48 {
  49         if (!vcpu_el1_is_32bit(vcpu))
  50                 return;
  51
  52         vcpu->arch.ctxt.sys_regs[FPEXC32_EL2] = read_sysreg(fpexc32_el2);
  53 }
  54
  55 static void __hyp_text __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
  56 {
  57         /*
  58          * We are about to set CPTR_EL2.TFP to trap all floating point
  59          * register accesses to EL2, however, the ARM ARM clearly states that
  60          * traps are only taken to EL2 if the operation would not otherwise
  61          * trap to EL1.  Therefore, always make sure that for 32-bit guests,
  62          * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
  63          * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
  64          * it will cause an exception.
  65          */
  66         if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
  67                 write_sysreg(1 << 30, fpexc32_el2);
  68                 isb();
  69         }
  70 }
  71
  72 static void __hyp_text __activate_traps_common(struct kvm_vcpu *vcpu)
  73 {
  74         /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
  75         write_sysreg(1 << 15, hstr_el2);
  76
  77         /*
  78          * Make sure we trap PMU access from EL0 to EL2. Also sanitize
  79          * PMSELR_EL0 to make sure it never contains the cycle
  80          * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
  81          * EL1 instead of being trapped to EL2.
  82          */
  83         write_sysreg(0, pmselr_el0);
  84         write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
  85         write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
  86 }
  87
  88 static void __hyp_text __deactivate_traps_common(void)
  89 {
  90         write_sysreg(0, hstr_el2);
  91         write_sysreg(0, pmuserenr_el0);
  92 }
  93
  94 static void activate_traps_vhe(struct kvm_vcpu *vcpu)
  95 {
  96         u64 val;
  97
  98         val = read_sysreg(cpacr_el1);
  99         val |= CPACR_EL1_TTA;
 100         val &= ~CPACR_EL1_ZEN;
 101         if (!update_fp_enabled(vcpu)) {
 102                 val &= ~CPACR_EL1_FPEN;
 103                 __activate_traps_fpsimd32(vcpu);
 104         }
 105
 106         write_sysreg(val, cpacr_el1);
 107
 108         write_sysreg(kvm_get_hyp_vector(), vbar_el1);
 109 }
 110
 111 static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu)
 112 {
 113         u64 val;
 114
 115         __activate_traps_common(vcpu);
 116
 117         val = CPTR_EL2_DEFAULT;
 118         val |= CPTR_EL2_TTA | CPTR_EL2_TZ;
 119         if (!update_fp_enabled(vcpu)) {
 120                 val |= CPTR_EL2_TFP;
 121                 __activate_traps_fpsimd32(vcpu);
 122         }
 123
 124         write_sysreg(val, cptr_el2);
 125 }
 126
 127 static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
 128 {
 129         u64 hcr = vcpu->arch.hcr_el2;
 130
 131         write_sysreg(hcr, hcr_el2);
 132
 133         if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
 134                 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
 135
 136         if (has_vhe())
 137                 activate_traps_vhe(vcpu);
 138         else
 139                 __activate_traps_nvhe(vcpu);
 140 }
 141
 142 static void deactivate_traps_vhe(void)
 143 {
 144         extern char vectors[];  /* kernel exception vectors */
 145         write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
 146         write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
 147         write_sysreg(vectors, vbar_el1);
 148 }
 149
 150 static void __hyp_text __deactivate_traps_nvhe(void)
 151 {
 152         u64 mdcr_el2 = read_sysreg(mdcr_el2);
 153
 154         __deactivate_traps_common();
 155
 156         mdcr_el2 &= MDCR_EL2_HPMN_MASK;
 157         mdcr_el2 |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT;
 158
 159         write_sysreg(mdcr_el2, mdcr_el2);
 160         write_sysreg(HCR_RW, hcr_el2);
 161         write_sysreg(CPTR_EL2_DEFAULT, cptr_el2);
 162 }
 163
 164 static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
 165 {
 166         /*
 167          * If we pended a virtual abort, preserve it until it gets
 168          * cleared. See D1.14.3 (Virtual Interrupts) for details, but
 169          * the crucial bit is "On taking a vSError interrupt,
 170          * HCR_EL2.VSE is cleared to 0."
 171          */
 172         if (vcpu->arch.hcr_el2 & HCR_VSE)
 173                 vcpu->arch.hcr_el2 = read_sysreg(hcr_el2);
 174
 175         if (has_vhe())
 176                 deactivate_traps_vhe();
 177         else
 178                 __deactivate_traps_nvhe();
 179 }
 180
 181 void activate_traps_vhe_load(struct kvm_vcpu *vcpu)
 182 {
 183         __activate_traps_common(vcpu);
 184 }
 185
 186 void deactivate_traps_vhe_put(void)
 187 {
 188         u64 mdcr_el2 = read_sysreg(mdcr_el2);
 189
 190         mdcr_el2 &= MDCR_EL2_HPMN_MASK |
 191                     MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT |
 192                     MDCR_EL2_TPMS;
 193
 194         write_sysreg(mdcr_el2, mdcr_el2);
 195
 196         __deactivate_traps_common();
 197 }
 198
 199 static void __hyp_text __activate_vm(struct kvm *kvm)
 200 {
 201         __load_guest_stage2(kvm);
 202 }
 203
 204 static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
 205 {
 206         write_sysreg(0, vttbr_el2);
 207 }
 208
 209 /* Save VGICv3 state on non-VHE systems */
 210 static void __hyp_text __hyp_vgic_save_state(struct kvm_vcpu *vcpu)
 211 {
 212         if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
 213                 __vgic_v3_save_state(vcpu);
 214                 __vgic_v3_deactivate_traps(vcpu);
 215         }
 216 }
 217
 218 /* Restore VGICv3 state on non_VEH systems */
 219 static void __hyp_text __hyp_vgic_restore_state(struct kvm_vcpu *vcpu)
 220 {
 221         if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
 222                 __vgic_v3_activate_traps(vcpu);
 223                 __vgic_v3_restore_state(vcpu);
 224         }
 225 }
 226
 227 static bool __hyp_text __true_value(void)
 228 {
 229         return true;
 230 }
 231
 232 static bool __hyp_text __false_value(void)
 233 {
 234         return false;
 235 }
 236
 237 static hyp_alternate_select(__check_arm_834220,
 238                             __false_value, __true_value,
 239                             ARM64_WORKAROUND_834220);
 240
 241 static bool __hyp_text __translate_far_to_hpfar(u64 far, u64 *hpfar)
 242 {
 243         u64 par, tmp;
 244
 245         /*
 246          * Resolve the IPA the hard way using the guest VA.
 247          *
 248          * Stage-1 translation already validated the memory access
 249          * rights. As such, we can use the EL1 translation regime, and
 250          * don't have to distinguish between EL0 and EL1 access.
 251          *
 252          * We do need to save/restore PAR_EL1 though, as we haven't
 253          * saved the guest context yet, and we may return early...
 254          */
 255         par = read_sysreg(par_el1);
 256         asm volatile("at s1e1r, %0" : : "r" (far));
 257         isb();
 258
 259         tmp = read_sysreg(par_el1);
 260         write_sysreg(par, par_el1);
 261
 262         if (unlikely(tmp & 1))
 263                 return false; /* Translation failed, back to guest */
 264
 265         /* Convert PAR to HPFAR format */
 266         *hpfar = PAR_TO_HPFAR(tmp);
 267         return true;
 268 }
 269
 270 static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
 271 {
 272         u8 ec;
 273         u64 esr;
 274         u64 hpfar, far;
 275
 276         esr = vcpu->arch.fault.esr_el2;
 277         ec = ESR_ELx_EC(esr);
 278
 279         if (ec != ESR_ELx_EC_DABT_LOW && ec != ESR_ELx_EC_IABT_LOW)
 280                 return true;
 281
 282         far = read_sysreg_el2(far);
 283
 284         /*
 285          * The HPFAR can be invalid if the stage 2 fault did not
 286          * happen during a stage 1 page table walk (the ESR_EL2.S1PTW
 287          * bit is clear) and one of the two following cases are true:
 288          *   1. The fault was due to a permission fault
 289          *   2. The processor carries errata 834220
 290          *
 291          * Therefore, for all non S1PTW faults where we either have a
 292          * permission fault or the errata workaround is enabled, we
 293          * resolve the IPA using the AT instruction.
 294          */
 295         if (!(esr & ESR_ELx_S1PTW) &&
 296             (__check_arm_834220()() || (esr & ESR_ELx_FSC_TYPE) == FSC_PERM)) {
 297                 if (!__translate_far_to_hpfar(far, &hpfar))
 298                         return false;
 299         } else {
 300                 hpfar = read_sysreg(hpfar_el2);
 301         }
 302
 303         vcpu->arch.fault.far_el2 = far;
 304         vcpu->arch.fault.hpfar_el2 = hpfar;
 305         return true;
 306 }
 307
 308 /* Skip an instruction which has been emulated. Returns true if
 309  * execution can continue or false if we need to exit hyp mode because
 310  * single-step was in effect.
 311  */
 312 static bool __hyp_text __skip_instr(struct kvm_vcpu *vcpu)
 313 {
 314         *vcpu_pc(vcpu) = read_sysreg_el2(elr);
 315
 316         if (vcpu_mode_is_32bit(vcpu)) {
 317                 vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(spsr);
 318                 kvm_skip_instr32(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 319                 write_sysreg_el2(vcpu->arch.ctxt.gp_regs.regs.pstate, spsr);
 320         } else {
 321                 *vcpu_pc(vcpu) += 4;
 322         }
 323
 324         write_sysreg_el2(*vcpu_pc(vcpu), elr);
 325
 326         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
 327                 vcpu->arch.fault.esr_el2 =
 328                         (ESR_ELx_EC_SOFTSTP_LOW << ESR_ELx_EC_SHIFT) | 0x22;
 329                 return false;
 330         } else {
 331                 return true;
 332         }
 333 }
 334
 335 static bool __hyp_text __hyp_switch_fpsimd(struct kvm_vcpu *vcpu)
 336 {
 337         struct user_fpsimd_state *host_fpsimd = vcpu->arch.host_fpsimd_state;
 338
 339         if (has_vhe())
 340                 write_sysreg(read_sysreg(cpacr_el1) | CPACR_EL1_FPEN,
 341                              cpacr_el1);
 342         else
 343                 write_sysreg(read_sysreg(cptr_el2) & ~(u64)CPTR_EL2_TFP,
 344                              cptr_el2);
 345
 346         isb();
 347
 348         if (vcpu->arch.flags & KVM_ARM64_FP_HOST) {
 349                 /*
 350                  * In the SVE case, VHE is assumed: it is enforced by
 351                  * Kconfig and kvm_arch_init().
 352                  */
 353                 if (system_supports_sve() &&
 354                     (vcpu->arch.flags & KVM_ARM64_HOST_SVE_IN_USE)) {
 355                         struct thread_struct *thread = container_of(
 356                                 host_fpsimd,
 357                                 struct thread_struct, uw.fpsimd_state);
 358
 359                         sve_save_state(sve_pffr(thread), &host_fpsimd->fpsr);
 360                 } else {
 361                         __fpsimd_save_state(host_fpsimd);
 362                 }
 363
 364                 vcpu->arch.flags &= ~KVM_ARM64_FP_HOST;
 365         }
 366
 367         __fpsimd_restore_state(&vcpu->arch.ctxt.gp_regs.fp_regs);
 368
 369         /* Skip restoring fpexc32 for AArch64 guests */
 370         if (!(read_sysreg(hcr_el2) & HCR_RW))
 371                 write_sysreg(vcpu->arch.ctxt.sys_regs[FPEXC32_EL2],
 372                              fpexc32_el2);
 373
 374         vcpu->arch.flags |= KVM_ARM64_FP_ENABLED;
 375
 376         return true;
 377 }
 378
 379 /*
 380  * Return true when we were able to fixup the guest exit and should return to
 381  * the guest, false when we should restore the host state and return to the
 382  * main run loop.
 383  */
 384 static bool __hyp_text fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
 385 {
 386         if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
 387                 vcpu->arch.fault.esr_el2 = read_sysreg_el2(esr);
 388
 389         /*
 390          * We're using the raw exception code in order to only process
 391          * the trap if no SError is pending. We will come back to the
 392          * same PC once the SError has been injected, and replay the
 393          * trapping instruction.
 394          */
 395         if (*exit_code != ARM_EXCEPTION_TRAP)
 396                 goto exit;
 397
 398         /*
 399          * We trap the first access to the FP/SIMD to save the host context
 400          * and restore the guest context lazily.
 401          * If FP/SIMD is not implemented, handle the trap and inject an
 402          * undefined instruction exception to the guest.
 403          */
 404         if (system_supports_fpsimd() &&
 405             kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_FP_ASIMD)
 406                 return __hyp_switch_fpsimd(vcpu);
 407
 408         if (!__populate_fault_info(vcpu))
 409                 return true;
 410
 411         if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
 412                 bool valid;
 413
 414                 valid = kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_DABT_LOW &&
 415                         kvm_vcpu_trap_get_fault_type(vcpu) == FSC_FAULT &&
 416                         kvm_vcpu_dabt_isvalid(vcpu) &&
 417                         !kvm_vcpu_dabt_isextabt(vcpu) &&
 418                         !kvm_vcpu_dabt_iss1tw(vcpu);
 419
 420                 if (valid) {
 421                         int ret = __vgic_v2_perform_cpuif_access(vcpu);
 422
 423                         if (ret ==  1 && __skip_instr(vcpu))
 424                                 return true;
 425
 426                         if (ret == -1) {
 427                                 /* Promote an illegal access to an
 428                                  * SError. If we would be returning
 429                                  * due to single-step clear the SS
 430                                  * bit so handle_exit knows what to
 431                                  * do after dealing with the error.
 432                                  */
 433                                 if (!__skip_instr(vcpu))
 434                                         *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
 435                                 *exit_code = ARM_EXCEPTION_EL1_SERROR;
 436                         }
 437
 438                         goto exit;
 439                 }
 440         }
 441
 442         if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
 443             (kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 ||
 444              kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_CP15_32)) {
 445                 int ret = __vgic_v3_perform_cpuif_access(vcpu);
 446
 447                 if (ret == 1 && __skip_instr(vcpu))
 448                         return true;
 449         }
 450
 451 exit:
 452         /* Return to the host kernel and handle the exit */
 453         return false;
 454 }
 455
 456 static inline bool __hyp_text __needs_ssbd_off(struct kvm_vcpu *vcpu)
 457 {
 458         if (!cpus_have_const_cap(ARM64_SSBD))
 459                 return false;
 460
 461         return !(vcpu->arch.workaround_flags & VCPU_WORKAROUND_2_FLAG);
 462 }
 463
 464 static void __hyp_text __set_guest_arch_workaround_state(struct kvm_vcpu *vcpu)
 465 {
 466 #ifdef CONFIG_ARM64_SSBD
 467         /*
 468          * The host runs with the workaround always present. If the
 469          * guest wants it disabled, so be it...
 470          */
 471         if (__needs_ssbd_off(vcpu) &&
 472             __hyp_this_cpu_read(arm64_ssbd_callback_required))
 473                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 0, NULL);
 474 #endif
 475 }
 476
 477 static void __hyp_text __set_host_arch_workaround_state(struct kvm_vcpu *vcpu)
 478 {
 479 #ifdef CONFIG_ARM64_SSBD
 480         /*
 481          * If the guest has disabled the workaround, bring it back on.
 482          */
 483         if (__needs_ssbd_off(vcpu) &&
 484             __hyp_this_cpu_read(arm64_ssbd_callback_required))
 485                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 1, NULL);
 486 #endif
 487 }
 488
 489 /* Switch to the guest for VHE systems running in EL2 */
 490 int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
 491 {
 492         struct kvm_cpu_context *host_ctxt;
 493         struct kvm_cpu_context *guest_ctxt;
 494         u64 exit_code;
 495
 496         host_ctxt = vcpu->arch.host_cpu_context;
 497         host_ctxt->__hyp_running_vcpu = vcpu;
 498         guest_ctxt = &vcpu->arch.ctxt;
 499
 500         sysreg_save_host_state_vhe(host_ctxt);
 501
 502         __activate_traps(vcpu);
 503         __activate_vm(vcpu->kvm);
 504
 505         sysreg_restore_guest_state_vhe(guest_ctxt);
 506         __debug_switch_to_guest(vcpu);
 507
 508         __set_guest_arch_workaround_state(vcpu);
 509
 510         do {
 511                 /* Jump in the fire! */
 512                 exit_code = __guest_enter(vcpu, host_ctxt);
 513
 514                 /* And we're baaack! */
 515         } while (fixup_guest_exit(vcpu, &exit_code));
 516
 517         __set_host_arch_workaround_state(vcpu);
 518
 519         sysreg_save_guest_state_vhe(guest_ctxt);
 520
 521         __deactivate_traps(vcpu);
 522
 523         sysreg_restore_host_state_vhe(host_ctxt);
 524
 525         if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
 526                 __fpsimd_save_fpexc32(vcpu);
 527
 528         __debug_switch_to_host(vcpu);
 529
 530         return exit_code;
 531 }
 532
 533 /* Switch to the guest for legacy non-VHE systems */
 534 int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)
 535 {
 536         struct kvm_cpu_context *host_ctxt;
 537         struct kvm_cpu_context *guest_ctxt;
 538         u64 exit_code;
 539
 540         vcpu = kern_hyp_va(vcpu);
 541
 542         host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
 543         host_ctxt->__hyp_running_vcpu = vcpu;
 544         guest_ctxt = &vcpu->arch.ctxt;
 545
 546         __sysreg_save_state_nvhe(host_ctxt);
 547
 548         __activate_traps(vcpu);
 549         __activate_vm(kern_hyp_va(vcpu->kvm));
 550
 551         __hyp_vgic_restore_state(vcpu);
 552         __timer_enable_traps(vcpu);
 553
 554         /*
 555          * We must restore the 32-bit state before the sysregs, thanks
 556          * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
 557          */
 558         __sysreg32_restore_state(vcpu);
 559         __sysreg_restore_state_nvhe(guest_ctxt);
 560         __debug_switch_to_guest(vcpu);
 561
 562         __set_guest_arch_workaround_state(vcpu);
 563
 564         do {
 565                 /* Jump in the fire! */
 566                 exit_code = __guest_enter(vcpu, host_ctxt);
 567
 568                 /* And we're baaack! */
 569         } while (fixup_guest_exit(vcpu, &exit_code));
 570
 571         __set_host_arch_workaround_state(vcpu);
 572
 573         __sysreg_save_state_nvhe(guest_ctxt);
 574         __sysreg32_save_state(vcpu);
 575         __timer_disable_traps(vcpu);
 576         __hyp_vgic_save_state(vcpu);
 577
 578         __deactivate_traps(vcpu);
 579         __deactivate_vm(vcpu);
 580
 581         __sysreg_restore_state_nvhe(host_ctxt);
 582
 583         if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
 584                 __fpsimd_save_fpexc32(vcpu);
 585
 586         /*
 587          * This must come after restoring the host sysregs, since a non-VHE
 588          * system may enable SPE here and make use of the TTBRs.
 589          */
 590         __debug_switch_to_host(vcpu);
 591
 592         return exit_code;
 593 }
 594
 595 static const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n";
 596
 597 static void __hyp_text __hyp_call_panic_nvhe(u64 spsr, u64 elr, u64 par,
 598                                              struct kvm_cpu_context *__host_ctxt)
 599 {
 600         struct kvm_vcpu *vcpu;
 601         unsigned long str_va;
 602
 603         vcpu = __host_ctxt->__hyp_running_vcpu;
 604
 605         if (read_sysreg(vttbr_el2)) {
 606                 __timer_disable_traps(vcpu);
 607                 __deactivate_traps(vcpu);
 608                 __deactivate_vm(vcpu);
 609                 __sysreg_restore_state_nvhe(__host_ctxt);
 610         }
 611
 612         /*
 613          * Force the panic string to be loaded from the literal pool,
 614          * making sure it is a kernel address and not a PC-relative
 615          * reference.
 616          */
 617         asm volatile("ldr %0, =__hyp_panic_string" : "=r" (str_va));
 618
 619         __hyp_do_panic(str_va,
 620                        spsr,  elr,
 621                        read_sysreg(esr_el2),   read_sysreg_el2(far),
 622                        read_sysreg(hpfar_el2), par, vcpu);
 623 }
 624
 625 static void __hyp_call_panic_vhe(u64 spsr, u64 elr, u64 par,
 626                                  struct kvm_cpu_context *host_ctxt)
 627 {
 628         struct kvm_vcpu *vcpu;
 629         vcpu = host_ctxt->__hyp_running_vcpu;
 630
 631         __deactivate_traps(vcpu);
 632         sysreg_restore_host_state_vhe(host_ctxt);
 633
 634         panic(__hyp_panic_string,
 635               spsr,  elr,
 636               read_sysreg_el2(esr),   read_sysreg_el2(far),
 637               read_sysreg(hpfar_el2), par, vcpu);
 638 }
 639
 640 void __hyp_text __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt)
 641 {
 642         u64 spsr = read_sysreg_el2(spsr);
 643         u64 elr = read_sysreg_el2(elr);
 644         u64 par = read_sysreg(par_el1);
 645
 646         if (!has_vhe())
 647                 __hyp_call_panic_nvhe(spsr, elr, par, host_ctxt);
 648         else
 649                 __hyp_call_panic_vhe(spsr, elr, par, host_ctxt);
 650
 651         unreachable();
 652 }