arch/arm64/kernel/traps.c

   1 /*
   2  * Based on arch/arm/kernel/traps.c
   3  *
   4  * Copyright (C) 1995-2009 Russell King
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/bug.h>
  21 #include <linux/signal.h>
  22 #include <linux/personality.h>
  23 #include <linux/kallsyms.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/hardirq.h>
  27 #include <linux/kdebug.h>
  28 #include <linux/module.h>
  29 #include <linux/kexec.h>
  30 #include <linux/delay.h>
  31 #include <linux/init.h>
  32 #include <linux/sched/signal.h>
  33 #include <linux/sched/debug.h>
  34 #include <linux/sched/task_stack.h>
  35 #include <linux/sizes.h>
  36 #include <linux/syscalls.h>
  37 #include <linux/mm_types.h>
  38
  39 #include <asm/atomic.h>
  40 #include <asm/bug.h>
  41 #include <asm/cpufeature.h>
  42 #include <asm/daifflags.h>
  43 #include <asm/debug-monitors.h>
  44 #include <asm/esr.h>
  45 #include <asm/insn.h>
  46 #include <asm/traps.h>
  47 #include <asm/smp.h>
  48 #include <asm/stack_pointer.h>
  49 #include <asm/stacktrace.h>
  50 #include <asm/exception.h>
  51 #include <asm/system_misc.h>
  52 #include <asm/sysreg.h>
  53
  54 static const char *handler[]= {
  55         "Synchronous Abort",
  56         "IRQ",
  57         "FIQ",
  58         "Error"
  59 };
  60
  61 int show_unhandled_signals = 0;
  62
  63 static void dump_backtrace_entry(unsigned long where)
  64 {
  65         printk(" %pS\n", (void *)where);
  66 }
  67
  68 static void __dump_instr(const char *lvl, struct pt_regs *regs)
  69 {
  70         unsigned long addr = instruction_pointer(regs);
  71         char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
  72         int i;
  73
  74         for (i = -4; i < 1; i++) {
  75                 unsigned int val, bad;
  76
  77                 bad = get_user(val, &((u32 *)addr)[i]);
  78
  79                 if (!bad)
  80                         p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
  81                 else {
  82                         p += sprintf(p, "bad PC value");
  83                         break;
  84                 }
  85         }
  86         printk("%sCode: %s\n", lvl, str);
  87 }
  88
  89 static void dump_instr(const char *lvl, struct pt_regs *regs)
  90 {
  91         if (!user_mode(regs)) {
  92                 mm_segment_t fs = get_fs();
  93                 set_fs(KERNEL_DS);
  94                 __dump_instr(lvl, regs);
  95                 set_fs(fs);
  96         } else {
  97                 __dump_instr(lvl, regs);
  98         }
  99 }
 100
 101 void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
 102 {
 103         struct stackframe frame;
 104         int skip;
 105
 106         pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
 107
 108         if (!tsk)
 109                 tsk = current;
 110
 111         if (!try_get_task_stack(tsk))
 112                 return;
 113
 114         if (tsk == current) {
 115                 frame.fp = (unsigned long)__builtin_frame_address(0);
 116                 frame.pc = (unsigned long)dump_backtrace;
 117         } else {
 118                 /*
 119                  * task blocked in __switch_to
 120                  */
 121                 frame.fp = thread_saved_fp(tsk);
 122                 frame.pc = thread_saved_pc(tsk);
 123         }
 124 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
 125         frame.graph = tsk->curr_ret_stack;
 126 #endif
 127
 128         skip = !!regs;
 129         printk("Call trace:\n");
 130         do {
 131                 /* skip until specified stack frame */
 132                 if (!skip) {
 133                         dump_backtrace_entry(frame.pc);
 134                 } else if (frame.fp == regs->regs[29]) {
 135                         skip = 0;
 136                         /*
 137                          * Mostly, this is the case where this function is
 138                          * called in panic/abort. As exception handler's
 139                          * stack frame does not contain the corresponding pc
 140                          * at which an exception has taken place, use regs->pc
 141                          * instead.
 142                          */
 143                         dump_backtrace_entry(regs->pc);
 144                 }
 145         } while (!unwind_frame(tsk, &frame));
 146
 147         put_task_stack(tsk);
 148 }
 149
 150 void show_stack(struct task_struct *tsk, unsigned long *sp)
 151 {
 152         dump_backtrace(NULL, tsk);
 153         barrier();
 154 }
 155
 156 #ifdef CONFIG_PREEMPT
 157 #define S_PREEMPT " PREEMPT"
 158 #else
 159 #define S_PREEMPT ""
 160 #endif
 161 #define S_SMP " SMP"
 162
 163 static int __die(const char *str, int err, struct pt_regs *regs)
 164 {
 165         struct task_struct *tsk = current;
 166         static int die_counter;
 167         int ret;
 168
 169         pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n",
 170                  str, err, ++die_counter);
 171
 172         /* trap and error numbers are mostly meaningless on ARM */
 173         ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV);
 174         if (ret == NOTIFY_STOP)
 175                 return ret;
 176
 177         print_modules();
 178         __show_regs(regs);
 179         pr_emerg("Process %.*s (pid: %d, stack limit = 0x%p)\n",
 180                  TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk),
 181                  end_of_stack(tsk));
 182
 183         if (!user_mode(regs)) {
 184                 dump_backtrace(regs, tsk);
 185                 dump_instr(KERN_EMERG, regs);
 186         }
 187
 188         return ret;
 189 }
 190
 191 static DEFINE_RAW_SPINLOCK(die_lock);
 192
 193 /*
 194  * This function is protected against re-entrancy.
 195  */
 196 void die(const char *str, struct pt_regs *regs, int err)
 197 {
 198         int ret;
 199         unsigned long flags;
 200
 201         raw_spin_lock_irqsave(&die_lock, flags);
 202
 203         oops_enter();
 204
 205         console_verbose();
 206         bust_spinlocks(1);
 207         ret = __die(str, err, regs);
 208
 209         if (regs && kexec_should_crash(current))
 210                 crash_kexec(regs);
 211
 212         bust_spinlocks(0);
 213         add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
 214         oops_exit();
 215
 216         if (in_interrupt())
 217                 panic("Fatal exception in interrupt");
 218         if (panic_on_oops)
 219                 panic("Fatal exception");
 220
 221         raw_spin_unlock_irqrestore(&die_lock, flags);
 222
 223         if (ret != NOTIFY_STOP)
 224                 do_exit(SIGSEGV);
 225 }
 226
 227 static bool show_unhandled_signals_ratelimited(void)
 228 {
 229         static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
 230                                       DEFAULT_RATELIMIT_BURST);
 231         return show_unhandled_signals && __ratelimit(&rs);
 232 }
 233
 234 void arm64_force_sig_info(struct siginfo *info, const char *str,
 235                           struct task_struct *tsk)
 236 {
 237         unsigned int esr = tsk->thread.fault_code;
 238         struct pt_regs *regs = task_pt_regs(tsk);
 239
 240         if (!unhandled_signal(tsk, info->si_signo))
 241                 goto send_sig;
 242
 243         if (!show_unhandled_signals_ratelimited())
 244                 goto send_sig;
 245
 246         pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk));
 247         if (esr)
 248                 pr_cont("%s, ESR 0x%08x, ", esr_get_class_string(esr), esr);
 249
 250         pr_cont("%s", str);
 251         print_vma_addr(KERN_CONT " in ", regs->pc);
 252         pr_cont("\n");
 253         __show_regs(regs);
 254
 255 send_sig:
 256         force_sig_info(info->si_signo, info, tsk);
 257 }
 258
 259 void arm64_notify_die(const char *str, struct pt_regs *regs,
 260                       struct siginfo *info, int err)
 261 {
 262         if (user_mode(regs)) {
 263                 WARN_ON(regs != current_pt_regs());
 264                 current->thread.fault_address = 0;
 265                 current->thread.fault_code = err;
 266                 arm64_force_sig_info(info, str, current);
 267         } else {
 268                 die(str, regs, err);
 269         }
 270 }
 271
 272 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size)
 273 {
 274         regs->pc += size;
 275
 276         /*
 277          * If we were single stepping, we want to get the step exception after
 278          * we return from the trap.
 279          */
 280         if (user_mode(regs))
 281                 user_fastforward_single_step(current);
 282 }
 283
 284 static LIST_HEAD(undef_hook);
 285 static DEFINE_RAW_SPINLOCK(undef_lock);
 286
 287 void register_undef_hook(struct undef_hook *hook)
 288 {
 289         unsigned long flags;
 290
 291         raw_spin_lock_irqsave(&undef_lock, flags);
 292         list_add(&hook->node, &undef_hook);
 293         raw_spin_unlock_irqrestore(&undef_lock, flags);
 294 }
 295
 296 void unregister_undef_hook(struct undef_hook *hook)
 297 {
 298         unsigned long flags;
 299
 300         raw_spin_lock_irqsave(&undef_lock, flags);
 301         list_del(&hook->node);
 302         raw_spin_unlock_irqrestore(&undef_lock, flags);
 303 }
 304
 305 static int call_undef_hook(struct pt_regs *regs)
 306 {
 307         struct undef_hook *hook;
 308         unsigned long flags;
 309         u32 instr;
 310         int (*fn)(struct pt_regs *regs, u32 instr) = NULL;
 311         void __user *pc = (void __user *)instruction_pointer(regs);
 312
 313         if (!user_mode(regs)) {
 314                 __le32 instr_le;
 315                 if (probe_kernel_address((__force __le32 *)pc, instr_le))
 316                         goto exit;
 317                 instr = le32_to_cpu(instr_le);
 318         } else if (compat_thumb_mode(regs)) {
 319                 /* 16-bit Thumb instruction */
 320                 __le16 instr_le;
 321                 if (get_user(instr_le, (__le16 __user *)pc))
 322                         goto exit;
 323                 instr = le16_to_cpu(instr_le);
 324                 if (aarch32_insn_is_wide(instr)) {
 325                         u32 instr2;
 326
 327                         if (get_user(instr_le, (__le16 __user *)(pc + 2)))
 328                                 goto exit;
 329                         instr2 = le16_to_cpu(instr_le);
 330                         instr = (instr << 16) | instr2;
 331                 }
 332         } else {
 333                 /* 32-bit ARM instruction */
 334                 __le32 instr_le;
 335                 if (get_user(instr_le, (__le32 __user *)pc))
 336                         goto exit;
 337                 instr = le32_to_cpu(instr_le);
 338         }
 339
 340         raw_spin_lock_irqsave(&undef_lock, flags);
 341         list_for_each_entry(hook, &undef_hook, node)
 342                 if ((instr & hook->instr_mask) == hook->instr_val &&
 343                         (regs->pstate & hook->pstate_mask) == hook->pstate_val)
 344                         fn = hook->fn;
 345
 346         raw_spin_unlock_irqrestore(&undef_lock, flags);
 347 exit:
 348         return fn ? fn(regs, instr) : 1;
 349 }
 350
 351 void force_signal_inject(int signal, int code, unsigned long address)
 352 {
 353         siginfo_t info;
 354         const char *desc;
 355         struct pt_regs *regs = current_pt_regs();
 356
 357         if (WARN_ON(!user_mode(regs)))
 358                 return;
 359
 360         clear_siginfo(&info);
 361
 362         switch (signal) {
 363         case SIGILL:
 364                 desc = "undefined instruction";
 365                 break;
 366         case SIGSEGV:
 367                 desc = "illegal memory access";
 368                 break;
 369         default:
 370                 desc = "unknown or unrecoverable error";
 371                 break;
 372         }
 373
 374         /* Force signals we don't understand to SIGKILL */
 375         if (WARN_ON(signal != SIGKILL &&
 376                     siginfo_layout(signal, code) != SIL_FAULT)) {
 377                 signal = SIGKILL;
 378         }
 379
 380         info.si_signo = signal;
 381         info.si_errno = 0;
 382         info.si_code  = code;
 383         info.si_addr  = (void __user *)address;
 384
 385         arm64_notify_die(desc, regs, &info, 0);
 386 }
 387
 388 /*
 389  * Set up process info to signal segmentation fault - called on access error.
 390  */
 391 void arm64_notify_segfault(unsigned long addr)
 392 {
 393         int code;
 394
 395         down_read(&current->mm->mmap_sem);
 396         if (find_vma(current->mm, addr) == NULL)
 397                 code = SEGV_MAPERR;
 398         else
 399                 code = SEGV_ACCERR;
 400         up_read(&current->mm->mmap_sem);
 401
 402         force_signal_inject(SIGSEGV, code, addr);
 403 }
 404
 405 asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
 406 {
 407         /* check for AArch32 breakpoint instructions */
 408         if (!aarch32_break_handler(regs))
 409                 return;
 410
 411         if (call_undef_hook(regs) == 0)
 412                 return;
 413
 414         BUG_ON(!user_mode(regs));
 415         force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
 416 }
 417
 418 #define __user_cache_maint(insn, address, res)                  \
 419         if (address >= user_addr_max()) {                       \
 420                 res = -EFAULT;                                  \
 421         } else {                                                \
 422                 uaccess_ttbr0_enable();                         \
 423                 asm volatile (                                  \
 424                         "1:     " insn ", %1\n"                 \
 425                         "       mov     %w0, #0\n"              \
 426                         "2:\n"                                  \
 427                         "       .pushsection .fixup,\"ax\"\n"   \
 428                         "       .align  2\n"                    \
 429                         "3:     mov     %w0, %w2\n"             \
 430                         "       b       2b\n"                   \
 431                         "       .popsection\n"                  \
 432                         _ASM_EXTABLE(1b, 3b)                    \
 433                         : "=r" (res)                            \
 434                         : "r" (address), "i" (-EFAULT));        \
 435                 uaccess_ttbr0_disable();                        \
 436         }
 437
 438 static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
 439 {
 440         unsigned long address;
 441         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 442         int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
 443         int ret = 0;
 444
 445         address = untagged_addr(pt_regs_read_reg(regs, rt));
 446
 447         switch (crm) {
 448         case ESR_ELx_SYS64_ISS_CRM_DC_CVAU:     /* DC CVAU, gets promoted */
 449                 __user_cache_maint("dc civac", address, ret);
 450                 break;
 451         case ESR_ELx_SYS64_ISS_CRM_DC_CVAC:     /* DC CVAC, gets promoted */
 452                 __user_cache_maint("dc civac", address, ret);
 453                 break;
 454         case ESR_ELx_SYS64_ISS_CRM_DC_CVAP:     /* DC CVAP */
 455                 __user_cache_maint("sys 3, c7, c12, 1", address, ret);
 456                 break;
 457         case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC:    /* DC CIVAC */
 458                 __user_cache_maint("dc civac", address, ret);
 459                 break;
 460         case ESR_ELx_SYS64_ISS_CRM_IC_IVAU:     /* IC IVAU */
 461                 __user_cache_maint("ic ivau", address, ret);
 462                 break;
 463         default:
 464                 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
 465                 return;
 466         }
 467
 468         if (ret)
 469                 arm64_notify_segfault(address);
 470         else
 471                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 472 }
 473
 474 static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
 475 {
 476         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 477         unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
 478
 479         pt_regs_write_reg(regs, rt, val);
 480
 481         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 482 }
 483
 484 static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
 485 {
 486         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 487
 488         pt_regs_write_reg(regs, rt, arch_counter_get_cntvct());
 489         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 490 }
 491
 492 static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
 493 {
 494         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 495
 496         pt_regs_write_reg(regs, rt, arch_timer_get_rate());
 497         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 498 }
 499
 500 static void mrs_handler(unsigned int esr, struct pt_regs *regs)
 501 {
 502         u32 sysreg, rt;
 503
 504         rt = ESR_ELx_SYS64_ISS_RT(esr);
 505         sysreg = esr_sys64_to_sysreg(esr);
 506
 507         if (do_emulate_mrs(regs, sysreg, rt) != 0)
 508                 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
 509 }
 510
 511 static void wfi_handler(unsigned int esr, struct pt_regs *regs)
 512 {
 513         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 514 }
 515
 516 struct sys64_hook {
 517         unsigned int esr_mask;
 518         unsigned int esr_val;
 519         void (*handler)(unsigned int esr, struct pt_regs *regs);
 520 };
 521
 522 static struct sys64_hook sys64_hooks[] = {
 523         {
 524                 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK,
 525                 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL,
 526                 .handler = user_cache_maint_handler,
 527         },
 528         {
 529                 /* Trap read access to CTR_EL0 */
 530                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 531                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
 532                 .handler = ctr_read_handler,
 533         },
 534         {
 535                 /* Trap read access to CNTVCT_EL0 */
 536                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 537                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT,
 538                 .handler = cntvct_read_handler,
 539         },
 540         {
 541                 /* Trap read access to CNTFRQ_EL0 */
 542                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 543                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ,
 544                 .handler = cntfrq_read_handler,
 545         },
 546         {
 547                 /* Trap read access to CPUID registers */
 548                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK,
 549                 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL,
 550                 .handler = mrs_handler,
 551         },
 552         {
 553                 /* Trap WFI instructions executed in userspace */
 554                 .esr_mask = ESR_ELx_WFx_MASK,
 555                 .esr_val = ESR_ELx_WFx_WFI_VAL,
 556                 .handler = wfi_handler,
 557         },
 558         {},
 559 };
 560
 561
 562 #ifdef CONFIG_COMPAT
 563 #define PSTATE_IT_1_0_SHIFT     25
 564 #define PSTATE_IT_1_0_MASK      (0x3 << PSTATE_IT_1_0_SHIFT)
 565 #define PSTATE_IT_7_2_SHIFT     10
 566 #define PSTATE_IT_7_2_MASK      (0x3f << PSTATE_IT_7_2_SHIFT)
 567
 568 static u32 compat_get_it_state(struct pt_regs *regs)
 569 {
 570         u32 it, pstate = regs->pstate;
 571
 572         it  = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT;
 573         it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2;
 574
 575         return it;
 576 }
 577
 578 static void compat_set_it_state(struct pt_regs *regs, u32 it)
 579 {
 580         u32 pstate_it;
 581
 582         pstate_it  = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK;
 583         pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK;
 584
 585         regs->pstate &= ~PSR_AA32_IT_MASK;
 586         regs->pstate |= pstate_it;
 587 }
 588
 589 static bool cp15_cond_valid(unsigned int esr, struct pt_regs *regs)
 590 {
 591         int cond;
 592
 593         /* Only a T32 instruction can trap without CV being set */
 594         if (!(esr & ESR_ELx_CV)) {
 595                 u32 it;
 596
 597                 it = compat_get_it_state(regs);
 598                 if (!it)
 599                         return true;
 600
 601                 cond = it >> 4;
 602         } else {
 603                 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
 604         }
 605
 606         return aarch32_opcode_cond_checks[cond](regs->pstate);
 607 }
 608
 609 static void advance_itstate(struct pt_regs *regs)
 610 {
 611         u32 it;
 612
 613         /* ARM mode */
 614         if (!(regs->pstate & PSR_AA32_T_BIT) ||
 615             !(regs->pstate & PSR_AA32_IT_MASK))
 616                 return;
 617
 618         it  = compat_get_it_state(regs);
 619
 620         /*
 621          * If this is the last instruction of the block, wipe the IT
 622          * state. Otherwise advance it.
 623          */
 624         if (!(it & 7))
 625                 it = 0;
 626         else
 627                 it = (it & 0xe0) | ((it << 1) & 0x1f);
 628
 629         compat_set_it_state(regs, it);
 630 }
 631
 632 static void arm64_compat_skip_faulting_instruction(struct pt_regs *regs,
 633                                                    unsigned int sz)
 634 {
 635         advance_itstate(regs);
 636         arm64_skip_faulting_instruction(regs, sz);
 637 }
 638
 639 static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
 640 {
 641         int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT;
 642
 643         pt_regs_write_reg(regs, reg, arch_timer_get_rate());
 644         arm64_compat_skip_faulting_instruction(regs, 4);
 645 }
 646
 647 static struct sys64_hook cp15_32_hooks[] = {
 648         {
 649                 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK,
 650                 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ,
 651                 .handler = compat_cntfrq_read_handler,
 652         },
 653         {},
 654 };
 655
 656 static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
 657 {
 658         int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT;
 659         int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT;
 660         u64 val = arch_counter_get_cntvct();
 661
 662         pt_regs_write_reg(regs, rt, lower_32_bits(val));
 663         pt_regs_write_reg(regs, rt2, upper_32_bits(val));
 664         arm64_compat_skip_faulting_instruction(regs, 4);
 665 }
 666
 667 static struct sys64_hook cp15_64_hooks[] = {
 668         {
 669                 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK,
 670                 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT,
 671                 .handler = compat_cntvct_read_handler,
 672         },
 673         {},
 674 };
 675
 676 asmlinkage void __exception do_cp15instr(unsigned int esr, struct pt_regs *regs)
 677 {
 678         struct sys64_hook *hook, *hook_base;
 679
 680         if (!cp15_cond_valid(esr, regs)) {
 681                 /*
 682                  * There is no T16 variant of a CP access, so we
 683                  * always advance PC by 4 bytes.
 684                  */
 685                 arm64_compat_skip_faulting_instruction(regs, 4);
 686                 return;
 687         }
 688
 689         switch (ESR_ELx_EC(esr)) {
 690         case ESR_ELx_EC_CP15_32:
 691                 hook_base = cp15_32_hooks;
 692                 break;
 693         case ESR_ELx_EC_CP15_64:
 694                 hook_base = cp15_64_hooks;
 695                 break;
 696         default:
 697                 do_undefinstr(regs);
 698                 return;
 699         }
 700
 701         for (hook = hook_base; hook->handler; hook++)
 702                 if ((hook->esr_mask & esr) == hook->esr_val) {
 703                         hook->handler(esr, regs);
 704                         return;
 705                 }
 706
 707         /*
 708          * New cp15 instructions may previously have been undefined at
 709          * EL0. Fall back to our usual undefined instruction handler
 710          * so that we handle these consistently.
 711          */
 712         do_undefinstr(regs);
 713 }
 714 #endif
 715
 716 asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs)
 717 {
 718         struct sys64_hook *hook;
 719
 720         for (hook = sys64_hooks; hook->handler; hook++)
 721                 if ((hook->esr_mask & esr) == hook->esr_val) {
 722                         hook->handler(esr, regs);
 723                         return;
 724                 }
 725
 726         /*
 727          * New SYS instructions may previously have been undefined at EL0. Fall
 728          * back to our usual undefined instruction handler so that we handle
 729          * these consistently.
 730          */
 731         do_undefinstr(regs);
 732 }
 733
 734 static const char *esr_class_str[] = {
 735         [0 ... ESR_ELx_EC_MAX]          = "UNRECOGNIZED EC",
 736         [ESR_ELx_EC_UNKNOWN]            = "Unknown/Uncategorized",
 737         [ESR_ELx_EC_WFx]                = "WFI/WFE",
 738         [ESR_ELx_EC_CP15_32]            = "CP15 MCR/MRC",
 739         [ESR_ELx_EC_CP15_64]            = "CP15 MCRR/MRRC",
 740         [ESR_ELx_EC_CP14_MR]            = "CP14 MCR/MRC",
 741         [ESR_ELx_EC_CP14_LS]            = "CP14 LDC/STC",
 742         [ESR_ELx_EC_FP_ASIMD]           = "ASIMD",
 743         [ESR_ELx_EC_CP10_ID]            = "CP10 MRC/VMRS",
 744         [ESR_ELx_EC_CP14_64]            = "CP14 MCRR/MRRC",
 745         [ESR_ELx_EC_ILL]                = "PSTATE.IL",
 746         [ESR_ELx_EC_SVC32]              = "SVC (AArch32)",
 747         [ESR_ELx_EC_HVC32]              = "HVC (AArch32)",
 748         [ESR_ELx_EC_SMC32]              = "SMC (AArch32)",
 749         [ESR_ELx_EC_SVC64]              = "SVC (AArch64)",
 750         [ESR_ELx_EC_HVC64]              = "HVC (AArch64)",
 751         [ESR_ELx_EC_SMC64]              = "SMC (AArch64)",
 752         [ESR_ELx_EC_SYS64]              = "MSR/MRS (AArch64)",
 753         [ESR_ELx_EC_SVE]                = "SVE",
 754         [ESR_ELx_EC_IMP_DEF]            = "EL3 IMP DEF",
 755         [ESR_ELx_EC_IABT_LOW]           = "IABT (lower EL)",
 756         [ESR_ELx_EC_IABT_CUR]           = "IABT (current EL)",
 757         [ESR_ELx_EC_PC_ALIGN]           = "PC Alignment",
 758         [ESR_ELx_EC_DABT_LOW]           = "DABT (lower EL)",
 759         [ESR_ELx_EC_DABT_CUR]           = "DABT (current EL)",
 760         [ESR_ELx_EC_SP_ALIGN]           = "SP Alignment",
 761         [ESR_ELx_EC_FP_EXC32]           = "FP (AArch32)",
 762         [ESR_ELx_EC_FP_EXC64]           = "FP (AArch64)",
 763         [ESR_ELx_EC_SERROR]             = "SError",
 764         [ESR_ELx_EC_BREAKPT_LOW]        = "Breakpoint (lower EL)",
 765         [ESR_ELx_EC_BREAKPT_CUR]        = "Breakpoint (current EL)",
 766         [ESR_ELx_EC_SOFTSTP_LOW]        = "Software Step (lower EL)",
 767         [ESR_ELx_EC_SOFTSTP_CUR]        = "Software Step (current EL)",
 768         [ESR_ELx_EC_WATCHPT_LOW]        = "Watchpoint (lower EL)",
 769         [ESR_ELx_EC_WATCHPT_CUR]        = "Watchpoint (current EL)",
 770         [ESR_ELx_EC_BKPT32]             = "BKPT (AArch32)",
 771         [ESR_ELx_EC_VECTOR32]           = "Vector catch (AArch32)",
 772         [ESR_ELx_EC_BRK64]              = "BRK (AArch64)",
 773 };
 774
 775 const char *esr_get_class_string(u32 esr)
 776 {
 777         return esr_class_str[ESR_ELx_EC(esr)];
 778 }
 779
 780 /*
 781  * bad_mode handles the impossible case in the exception vector. This is always
 782  * fatal.
 783  */
 784 asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
 785 {
 786         console_verbose();
 787
 788         pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n",
 789                 handler[reason], smp_processor_id(), esr,
 790                 esr_get_class_string(esr));
 791
 792         local_daif_mask();
 793         panic("bad mode");
 794 }
 795
 796 /*
 797  * bad_el0_sync handles unexpected, but potentially recoverable synchronous
 798  * exceptions taken from EL0. Unlike bad_mode, this returns.
 799  */
 800 asmlinkage void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr)
 801 {
 802         siginfo_t info;
 803         void __user *pc = (void __user *)instruction_pointer(regs);
 804
 805         clear_siginfo(&info);
 806         info.si_signo = SIGILL;
 807         info.si_errno = 0;
 808         info.si_code  = ILL_ILLOPC;
 809         info.si_addr  = pc;
 810
 811         current->thread.fault_address = 0;
 812         current->thread.fault_code = esr;
 813
 814         arm64_force_sig_info(&info, "Bad EL0 synchronous exception", current);
 815 }
 816
 817 #ifdef CONFIG_VMAP_STACK
 818
 819 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack)
 820         __aligned(16);
 821
 822 asmlinkage void handle_bad_stack(struct pt_regs *regs)
 823 {
 824         unsigned long tsk_stk = (unsigned long)current->stack;
 825         unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr);
 826         unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack);
 827         unsigned int esr = read_sysreg(esr_el1);
 828         unsigned long far = read_sysreg(far_el1);
 829
 830         console_verbose();
 831         pr_emerg("Insufficient stack space to handle exception!");
 832
 833         pr_emerg("ESR: 0x%08x -- %s\n", esr, esr_get_class_string(esr));
 834         pr_emerg("FAR: 0x%016lx\n", far);
 835
 836         pr_emerg("Task stack:     [0x%016lx..0x%016lx]\n",
 837                  tsk_stk, tsk_stk + THREAD_SIZE);
 838         pr_emerg("IRQ stack:      [0x%016lx..0x%016lx]\n",
 839                  irq_stk, irq_stk + THREAD_SIZE);
 840         pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n",
 841                  ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE);
 842
 843         __show_regs(regs);
 844
 845         /*
 846          * We use nmi_panic to limit the potential for recusive overflows, and
 847          * to get a better stack trace.
 848          */
 849         nmi_panic(NULL, "kernel stack overflow");
 850         cpu_park_loop();
 851 }
 852 #endif
 853
 854 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr)
 855 {
 856         console_verbose();
 857
 858         pr_crit("SError Interrupt on CPU%d, code 0x%08x -- %s\n",
 859                 smp_processor_id(), esr, esr_get_class_string(esr));
 860         if (regs)
 861                 __show_regs(regs);
 862
 863         nmi_panic(regs, "Asynchronous SError Interrupt");
 864
 865         cpu_park_loop();
 866         unreachable();
 867 }
 868
 869 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr)
 870 {
 871         u32 aet = arm64_ras_serror_get_severity(esr);
 872
 873         switch (aet) {
 874         case ESR_ELx_AET_CE:    /* corrected error */
 875         case ESR_ELx_AET_UEO:   /* restartable, not yet consumed */
 876                 /*
 877                  * The CPU can make progress. We may take UEO again as
 878                  * a more severe error.
 879                  */
 880                 return false;
 881
 882         case ESR_ELx_AET_UEU:   /* Uncorrected Unrecoverable */
 883         case ESR_ELx_AET_UER:   /* Uncorrected Recoverable */
 884                 /*
 885                  * The CPU can't make progress. The exception may have
 886                  * been imprecise.
 887                  */
 888                 return true;
 889
 890         case ESR_ELx_AET_UC:    /* Uncontainable or Uncategorized error */
 891         default:
 892                 /* Error has been silently propagated */
 893                 arm64_serror_panic(regs, esr);
 894         }
 895 }
 896
 897 asmlinkage void do_serror(struct pt_regs *regs, unsigned int esr)
 898 {
 899         nmi_enter();
 900
 901         /* non-RAS errors are not containable */
 902         if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr))
 903                 arm64_serror_panic(regs, esr);
 904
 905         nmi_exit();
 906 }
 907
 908 void __pte_error(const char *file, int line, unsigned long val)
 909 {
 910         pr_err("%s:%d: bad pte %016lx.\n", file, line, val);
 911 }
 912
 913 void __pmd_error(const char *file, int line, unsigned long val)
 914 {
 915         pr_err("%s:%d: bad pmd %016lx.\n", file, line, val);
 916 }
 917
 918 void __pud_error(const char *file, int line, unsigned long val)
 919 {
 920         pr_err("%s:%d: bad pud %016lx.\n", file, line, val);
 921 }
 922
 923 void __pgd_error(const char *file, int line, unsigned long val)
 924 {
 925         pr_err("%s:%d: bad pgd %016lx.\n", file, line, val);
 926 }
 927
 928 /* GENERIC_BUG traps */
 929
 930 int is_valid_bugaddr(unsigned long addr)
 931 {
 932         /*
 933          * bug_handler() only called for BRK #BUG_BRK_IMM.
 934          * So the answer is trivial -- any spurious instances with no
 935          * bug table entry will be rejected by report_bug() and passed
 936          * back to the debug-monitors code and handled as a fatal
 937          * unexpected debug exception.
 938          */
 939         return 1;
 940 }
 941
 942 static int bug_handler(struct pt_regs *regs, unsigned int esr)
 943 {
 944         if (user_mode(regs))
 945                 return DBG_HOOK_ERROR;
 946
 947         switch (report_bug(regs->pc, regs)) {
 948         case BUG_TRAP_TYPE_BUG:
 949                 die("Oops - BUG", regs, 0);
 950                 break;
 951
 952         case BUG_TRAP_TYPE_WARN:
 953                 break;
 954
 955         default:
 956                 /* unknown/unrecognised bug trap type */
 957                 return DBG_HOOK_ERROR;
 958         }
 959
 960         /* If thread survives, skip over the BUG instruction and continue: */
 961         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 962         return DBG_HOOK_HANDLED;
 963 }
 964
 965 static struct break_hook bug_break_hook = {
 966         .esr_val = 0xf2000000 | BUG_BRK_IMM,
 967         .esr_mask = 0xffffffff,
 968         .fn = bug_handler,
 969 };
 970
 971 /*
 972  * Initial handler for AArch64 BRK exceptions
 973  * This handler only used until debug_traps_init().
 974  */
 975 int __init early_brk64(unsigned long addr, unsigned int esr,
 976                 struct pt_regs *regs)
 977 {
 978         return bug_handler(regs, esr) != DBG_HOOK_HANDLED;
 979 }
 980
 981 /* This registration must happen early, before debug_traps_init(). */
 982 void __init trap_init(void)
 983 {
 984         register_break_hook(&bug_break_hook);
 985 }