2 * Based on arch/arm/kernel/setup.c
4 * Copyright (C) 1995-2001 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/export.h>
21 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/ioport.h>
24 #include <linux/delay.h>
25 #include <linux/utsname.h>
26 #include <linux/initrd.h>
27 #include <linux/console.h>
28 #include <linux/cache.h>
29 #include <linux/bootmem.h>
30 #include <linux/seq_file.h>
31 #include <linux/screen_info.h>
32 #include <linux/init.h>
33 #include <linux/kexec.h>
34 #include <linux/crash_dump.h>
35 #include <linux/root_dev.h>
36 #include <linux/clk-provider.h>
37 #include <linux/cpu.h>
38 #include <linux/interrupt.h>
39 #include <linux/smp.h>
41 #include <linux/proc_fs.h>
42 #include <linux/memblock.h>
43 #include <linux/of_fdt.h>
44 #include <linux/of_platform.h>
45 #include <linux/efi.h>
47 #include <asm/fixmap.h>
49 #include <asm/cputype.h>
51 #include <asm/cputable.h>
52 #include <asm/cpu_ops.h>
53 #include <asm/sections.h>
54 #include <asm/setup.h>
55 #include <asm/smp_plat.h>
56 #include <asm/cacheflush.h>
57 #include <asm/tlbflush.h>
58 #include <asm/traps.h>
59 #include <asm/memblock.h>
63 unsigned int processor_id;
64 EXPORT_SYMBOL(processor_id);
66 unsigned long elf_hwcap __read_mostly;
67 EXPORT_SYMBOL_GPL(elf_hwcap);
70 #define COMPAT_ELF_HWCAP_DEFAULT \
71 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
72 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
73 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
74 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
75 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV)
76 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
77 unsigned int compat_elf_hwcap2 __read_mostly;
80 static const char *cpu_name;
81 static const char *machine_name;
82 phys_addr_t __fdt_pointer __initdata;
85 * Standard memory resources
87 static struct resource mem_res[] = {
89 .name = "Kernel code",
92 .flags = IORESOURCE_MEM
95 .name = "Kernel data",
98 .flags = IORESOURCE_MEM
102 #define kernel_code mem_res[0]
103 #define kernel_data mem_res[1]
105 void __init early_print(const char *str, ...)
111 vsnprintf(buf, sizeof(buf), str, ap);
117 void __init smp_setup_processor_id(void)
120 * clear __my_cpu_offset on boot CPU to avoid hang caused by
121 * using percpu variable early, for example, lockdep will
122 * access percpu variable inside lock_release
124 set_my_cpu_offset(0);
127 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
129 return phys_id == cpu_logical_map(cpu);
132 struct mpidr_hash mpidr_hash;
135 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
136 * level in order to build a linear index from an
137 * MPIDR value. Resulting algorithm is a collision
138 * free hash carried out through shifting and ORing
140 static void __init smp_build_mpidr_hash(void)
142 u32 i, affinity, fs[4], bits[4], ls;
145 * Pre-scan the list of MPIDRS and filter out bits that do
146 * not contribute to affinity levels, ie they never toggle.
148 for_each_possible_cpu(i)
149 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
150 pr_debug("mask of set bits %#llx\n", mask);
152 * Find and stash the last and first bit set at all affinity levels to
153 * check how many bits are required to represent them.
155 for (i = 0; i < 4; i++) {
156 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
158 * Find the MSB bit and LSB bits position
159 * to determine how many bits are required
160 * to express the affinity level.
163 fs[i] = affinity ? ffs(affinity) - 1 : 0;
164 bits[i] = ls - fs[i];
167 * An index can be created from the MPIDR_EL1 by isolating the
168 * significant bits at each affinity level and by shifting
169 * them in order to compress the 32 bits values space to a
170 * compressed set of values. This is equivalent to hashing
171 * the MPIDR_EL1 through shifting and ORing. It is a collision free
172 * hash though not minimal since some levels might contain a number
173 * of CPUs that is not an exact power of 2 and their bit
174 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
176 mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
177 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
178 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
180 mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
181 fs[3] - (bits[2] + bits[1] + bits[0]);
182 mpidr_hash.mask = mask;
183 mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
184 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
185 mpidr_hash.shift_aff[0],
186 mpidr_hash.shift_aff[1],
187 mpidr_hash.shift_aff[2],
188 mpidr_hash.shift_aff[3],
192 * 4x is an arbitrary value used to warn on a hash table much bigger
193 * than expected on most systems.
195 if (mpidr_hash_size() > 4 * num_possible_cpus())
196 pr_warn("Large number of MPIDR hash buckets detected\n");
197 __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash));
201 static void __init setup_processor(void)
203 struct cpu_info *cpu_info;
208 cpu_info = lookup_processor_type(read_cpuid_id());
210 printk("CPU configuration botched (ID %08x), unable to continue.\n",
215 cpu_name = cpu_info->cpu_name;
217 printk("CPU: %s [%08x] revision %d\n",
218 cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
220 sprintf(init_utsname()->machine, ELF_PLATFORM);
223 cpuinfo_store_boot_cpu();
226 * Check for sane CTR_EL0.CWG value.
228 cwg = cache_type_cwg();
229 cls = cache_line_size();
231 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
233 if (L1_CACHE_BYTES < cls)
234 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
235 L1_CACHE_BYTES, cls);
238 * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
239 * The blocks we test below represent incremental functionality
240 * for non-negative values. Negative values are reserved.
242 features = read_cpuid(ID_AA64ISAR0_EL1);
243 block = (features >> 4) & 0xf;
244 if (!(block & 0x8)) {
248 elf_hwcap |= HWCAP_PMULL;
250 elf_hwcap |= HWCAP_AES;
256 block = (features >> 8) & 0xf;
257 if (block && !(block & 0x8))
258 elf_hwcap |= HWCAP_SHA1;
260 block = (features >> 12) & 0xf;
261 if (block && !(block & 0x8))
262 elf_hwcap |= HWCAP_SHA2;
264 block = (features >> 16) & 0xf;
265 if (block && !(block & 0x8))
266 elf_hwcap |= HWCAP_CRC32;
270 * ID_ISAR5_EL1 carries similar information as above, but pertaining to
271 * the Aarch32 32-bit execution state.
273 features = read_cpuid(ID_ISAR5_EL1);
274 block = (features >> 4) & 0xf;
275 if (!(block & 0x8)) {
279 compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL;
281 compat_elf_hwcap2 |= COMPAT_HWCAP2_AES;
287 block = (features >> 8) & 0xf;
288 if (block && !(block & 0x8))
289 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1;
291 block = (features >> 12) & 0xf;
292 if (block && !(block & 0x8))
293 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2;
295 block = (features >> 16) & 0xf;
296 if (block && !(block & 0x8))
297 compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32;
301 static void __init setup_machine_fdt(phys_addr_t dt_phys)
303 if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) {
305 "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
306 "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
307 "\nPlease check your bootloader.\n",
308 dt_phys, phys_to_virt(dt_phys));
314 machine_name = of_flat_dt_get_machine_name();
318 * Limit the memory size that was specified via FDT.
320 static int __init early_mem(char *p)
327 limit = memparse(p, &p) & PAGE_MASK;
328 pr_notice("Memory limited to %lldMB\n", limit >> 20);
330 memblock_enforce_memory_limit(limit);
334 early_param("mem", early_mem);
336 static void __init request_standard_resources(void)
338 struct memblock_region *region;
339 struct resource *res;
341 kernel_code.start = virt_to_phys(_text);
342 kernel_code.end = virt_to_phys(_etext - 1);
343 kernel_data.start = virt_to_phys(_sdata);
344 kernel_data.end = virt_to_phys(_end - 1);
346 for_each_memblock(memory, region) {
347 res = alloc_bootmem_low(sizeof(*res));
348 res->name = "System RAM";
349 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
350 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
351 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
353 request_resource(&iomem_resource, res);
355 if (kernel_code.start >= res->start &&
356 kernel_code.end <= res->end)
357 request_resource(res, &kernel_code);
358 if (kernel_data.start >= res->start &&
359 kernel_data.end <= res->end)
360 request_resource(res, &kernel_data);
364 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
366 void __init setup_arch(char **cmdline_p)
370 setup_machine_fdt(__fdt_pointer);
372 init_mm.start_code = (unsigned long) _text;
373 init_mm.end_code = (unsigned long) _etext;
374 init_mm.end_data = (unsigned long) _edata;
375 init_mm.brk = (unsigned long) _end;
377 *cmdline_p = boot_command_line;
379 early_ioremap_init();
384 * Unmask asynchronous aborts after bringing up possible earlycon.
385 * (Report possible System Errors once we can report this occurred)
387 local_async_enable();
390 arm64_memblock_init();
393 request_standard_resources();
397 unflatten_device_tree();
401 cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
402 cpu_read_bootcpu_ops();
405 smp_build_mpidr_hash();
409 #if defined(CONFIG_VGA_CONSOLE)
410 conswitchp = &vga_con;
411 #elif defined(CONFIG_DUMMY_CONSOLE)
412 conswitchp = &dummy_con;
417 static int __init arm64_device_init(void)
419 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
422 arch_initcall_sync(arm64_device_init);
424 static int __init topology_init(void)
428 for_each_possible_cpu(i) {
429 struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
430 cpu->hotpluggable = 1;
431 register_cpu(cpu, i);
436 subsys_initcall(topology_init);
438 static const char *hwcap_str[] = {
450 static int c_show(struct seq_file *m, void *v)
454 seq_printf(m, "Processor\t: %s rev %d (%s)\n",
455 cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
457 for_each_online_cpu(i) {
459 * glibc reads /proc/cpuinfo to determine the number of
460 * online processors, looking for lines beginning with
461 * "processor". Give glibc what it expects.
464 seq_printf(m, "processor\t: %d\n", i);
468 /* dump out the processor features */
469 seq_puts(m, "Features\t: ");
471 for (i = 0; hwcap_str[i]; i++)
472 if (elf_hwcap & (1 << i))
473 seq_printf(m, "%s ", hwcap_str[i]);
475 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
476 seq_printf(m, "CPU architecture: AArch64\n");
477 seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
478 seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
479 seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
483 seq_printf(m, "Hardware\t: %s\n", machine_name);
488 static void *c_start(struct seq_file *m, loff_t *pos)
490 return *pos < 1 ? (void *)1 : NULL;
493 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
499 static void c_stop(struct seq_file *m, void *v)
503 const struct seq_operations cpuinfo_op = {