arch/arm64/kernel/perf_event.c

   1 /*
   2  * PMU support
   3  *
   4  * Copyright (C) 2012 ARM Limited
   5  * Author: Will Deacon <will.deacon@arm.com>
   6  *
   7  * This code is based heavily on the ARMv7 perf event code.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21 #define pr_fmt(fmt) "hw perfevents: " fmt
  22
  23 #include <linux/bitmap.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/kernel.h>
  27 #include <linux/export.h>
  28 #include <linux/perf_event.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/uaccess.h>
  32
  33 #include <asm/cputype.h>
  34 #include <asm/irq.h>
  35 #include <asm/irq_regs.h>
  36 #include <asm/pmu.h>
  37 #include <asm/stacktrace.h>
  38
  39 /*
  40  * ARMv8 supports a maximum of 32 events.
  41  * The cycle counter is included in this total.
  42  */
  43 #define ARMPMU_MAX_HWEVENTS             32
  44
  45 static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
  46 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
  47 static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
  48
  49 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
  50
  51 /* Set at runtime when we know what CPU type we are. */
  52 static struct arm_pmu *cpu_pmu;
  53
  54 int
  55 armpmu_get_max_events(void)
  56 {
  57         int max_events = 0;
  58
  59         if (cpu_pmu != NULL)
  60                 max_events = cpu_pmu->num_events;
  61
  62         return max_events;
  63 }
  64 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
  65
  66 int perf_num_counters(void)
  67 {
  68         return armpmu_get_max_events();
  69 }
  70 EXPORT_SYMBOL_GPL(perf_num_counters);
  71
  72 #define HW_OP_UNSUPPORTED               0xFFFF
  73
  74 #define C(_x) \
  75         PERF_COUNT_HW_CACHE_##_x
  76
  77 #define CACHE_OP_UNSUPPORTED            0xFFFF
  78
  79 static int
  80 armpmu_map_cache_event(const unsigned (*cache_map)
  81                                       [PERF_COUNT_HW_CACHE_MAX]
  82                                       [PERF_COUNT_HW_CACHE_OP_MAX]
  83                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
  84                        u64 config)
  85 {
  86         unsigned int cache_type, cache_op, cache_result, ret;
  87
  88         cache_type = (config >>  0) & 0xff;
  89         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  90                 return -EINVAL;
  91
  92         cache_op = (config >>  8) & 0xff;
  93         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  94                 return -EINVAL;
  95
  96         cache_result = (config >> 16) & 0xff;
  97         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  98                 return -EINVAL;
  99
 100         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
 101
 102         if (ret == CACHE_OP_UNSUPPORTED)
 103                 return -ENOENT;
 104
 105         return ret;
 106 }
 107
 108 static int
 109 armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
 110 {
 111         int mapping;
 112
 113         if (config >= PERF_COUNT_HW_MAX)
 114                 return -EINVAL;
 115
 116         mapping = (*event_map)[config];
 117         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
 118 }
 119
 120 static int
 121 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
 122 {
 123         return (int)(config & raw_event_mask);
 124 }
 125
 126 static int map_cpu_event(struct perf_event *event,
 127                          const unsigned (*event_map)[PERF_COUNT_HW_MAX],
 128                          const unsigned (*cache_map)
 129                                         [PERF_COUNT_HW_CACHE_MAX]
 130                                         [PERF_COUNT_HW_CACHE_OP_MAX]
 131                                         [PERF_COUNT_HW_CACHE_RESULT_MAX],
 132                          u32 raw_event_mask)
 133 {
 134         u64 config = event->attr.config;
 135
 136         switch (event->attr.type) {
 137         case PERF_TYPE_HARDWARE:
 138                 return armpmu_map_event(event_map, config);
 139         case PERF_TYPE_HW_CACHE:
 140                 return armpmu_map_cache_event(cache_map, config);
 141         case PERF_TYPE_RAW:
 142                 return armpmu_map_raw_event(raw_event_mask, config);
 143         }
 144
 145         return -ENOENT;
 146 }
 147
 148 int
 149 armpmu_event_set_period(struct perf_event *event,
 150                         struct hw_perf_event *hwc,
 151                         int idx)
 152 {
 153         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 154         s64 left = local64_read(&hwc->period_left);
 155         s64 period = hwc->sample_period;
 156         int ret = 0;
 157
 158         if (unlikely(left <= -period)) {
 159                 left = period;
 160                 local64_set(&hwc->period_left, left);
 161                 hwc->last_period = period;
 162                 ret = 1;
 163         }
 164
 165         if (unlikely(left <= 0)) {
 166                 left += period;
 167                 local64_set(&hwc->period_left, left);
 168                 hwc->last_period = period;
 169                 ret = 1;
 170         }
 171
 172         /*
 173          * Limit the maximum period to prevent the counter value
 174          * from overtaking the one we are about to program. In
 175          * effect we are reducing max_period to account for
 176          * interrupt latency (and we are being very conservative).
 177          */
 178         if (left > (armpmu->max_period >> 1))
 179                 left = armpmu->max_period >> 1;
 180
 181         local64_set(&hwc->prev_count, (u64)-left);
 182
 183         armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
 184
 185         perf_event_update_userpage(event);
 186
 187         return ret;
 188 }
 189
 190 u64
 191 armpmu_event_update(struct perf_event *event,
 192                     struct hw_perf_event *hwc,
 193                     int idx)
 194 {
 195         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 196         u64 delta, prev_raw_count, new_raw_count;
 197
 198 again:
 199         prev_raw_count = local64_read(&hwc->prev_count);
 200         new_raw_count = armpmu->read_counter(idx);
 201
 202         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 203                              new_raw_count) != prev_raw_count)
 204                 goto again;
 205
 206         delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
 207
 208         local64_add(delta, &event->count);
 209         local64_sub(delta, &hwc->period_left);
 210
 211         return new_raw_count;
 212 }
 213
 214 static void
 215 armpmu_read(struct perf_event *event)
 216 {
 217         struct hw_perf_event *hwc = &event->hw;
 218
 219         /* Don't read disabled counters! */
 220         if (hwc->idx < 0)
 221                 return;
 222
 223         armpmu_event_update(event, hwc, hwc->idx);
 224 }
 225
 226 static void
 227 armpmu_stop(struct perf_event *event, int flags)
 228 {
 229         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 230         struct hw_perf_event *hwc = &event->hw;
 231
 232         /*
 233          * ARM pmu always has to update the counter, so ignore
 234          * PERF_EF_UPDATE, see comments in armpmu_start().
 235          */
 236         if (!(hwc->state & PERF_HES_STOPPED)) {
 237                 armpmu->disable(hwc, hwc->idx);
 238                 barrier(); /* why? */
 239                 armpmu_event_update(event, hwc, hwc->idx);
 240                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 241         }
 242 }
 243
 244 static void
 245 armpmu_start(struct perf_event *event, int flags)
 246 {
 247         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 248         struct hw_perf_event *hwc = &event->hw;
 249
 250         /*
 251          * ARM pmu always has to reprogram the period, so ignore
 252          * PERF_EF_RELOAD, see the comment below.
 253          */
 254         if (flags & PERF_EF_RELOAD)
 255                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 256
 257         hwc->state = 0;
 258         /*
 259          * Set the period again. Some counters can't be stopped, so when we
 260          * were stopped we simply disabled the IRQ source and the counter
 261          * may have been left counting. If we don't do this step then we may
 262          * get an interrupt too soon or *way* too late if the overflow has
 263          * happened since disabling.
 264          */
 265         armpmu_event_set_period(event, hwc, hwc->idx);
 266         armpmu->enable(hwc, hwc->idx);
 267 }
 268
 269 static void
 270 armpmu_del(struct perf_event *event, int flags)
 271 {
 272         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 273         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 274         struct hw_perf_event *hwc = &event->hw;
 275         int idx = hwc->idx;
 276
 277         WARN_ON(idx < 0);
 278
 279         armpmu_stop(event, PERF_EF_UPDATE);
 280         hw_events->events[idx] = NULL;
 281         clear_bit(idx, hw_events->used_mask);
 282
 283         perf_event_update_userpage(event);
 284 }
 285
 286 static int
 287 armpmu_add(struct perf_event *event, int flags)
 288 {
 289         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 290         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 291         struct hw_perf_event *hwc = &event->hw;
 292         int idx;
 293         int err = 0;
 294
 295         perf_pmu_disable(event->pmu);
 296
 297         /* If we don't have a space for the counter then finish early. */
 298         idx = armpmu->get_event_idx(hw_events, hwc);
 299         if (idx < 0) {
 300                 err = idx;
 301                 goto out;
 302         }
 303
 304         /*
 305          * If there is an event in the counter we are going to use then make
 306          * sure it is disabled.
 307          */
 308         event->hw.idx = idx;
 309         armpmu->disable(hwc, idx);
 310         hw_events->events[idx] = event;
 311
 312         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 313         if (flags & PERF_EF_START)
 314                 armpmu_start(event, PERF_EF_RELOAD);
 315
 316         /* Propagate our changes to the userspace mapping. */
 317         perf_event_update_userpage(event);
 318
 319 out:
 320         perf_pmu_enable(event->pmu);
 321         return err;
 322 }
 323
 324 static int
 325 validate_event(struct pmu_hw_events *hw_events,
 326                struct perf_event *event)
 327 {
 328         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 329         struct hw_perf_event fake_event = event->hw;
 330         struct pmu *leader_pmu = event->group_leader->pmu;
 331
 332         if (is_software_event(event))
 333                 return 1;
 334
 335         if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF)
 336                 return 1;
 337
 338         if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
 339                 return 1;
 340
 341         return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
 342 }
 343
 344 static int
 345 validate_group(struct perf_event *event)
 346 {
 347         struct perf_event *sibling, *leader = event->group_leader;
 348         struct pmu_hw_events fake_pmu;
 349         DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
 350
 351         /*
 352          * Initialise the fake PMU. We only need to populate the
 353          * used_mask for the purposes of validation.
 354          */
 355         memset(fake_used_mask, 0, sizeof(fake_used_mask));
 356         fake_pmu.used_mask = fake_used_mask;
 357
 358         if (!validate_event(&fake_pmu, leader))
 359                 return -EINVAL;
 360
 361         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 362                 if (!validate_event(&fake_pmu, sibling))
 363                         return -EINVAL;
 364         }
 365
 366         if (!validate_event(&fake_pmu, event))
 367                 return -EINVAL;
 368
 369         return 0;
 370 }
 371
 372 static void
 373 armpmu_disable_percpu_irq(void *data)
 374 {
 375         unsigned int irq = *(unsigned int *)data;
 376         disable_percpu_irq(irq);
 377 }
 378
 379 static void
 380 armpmu_release_hardware(struct arm_pmu *armpmu)
 381 {
 382         int irq;
 383         unsigned int i, irqs;
 384         struct platform_device *pmu_device = armpmu->plat_device;
 385
 386         irqs = min(pmu_device->num_resources, num_possible_cpus());
 387         if (!irqs)
 388                 return;
 389
 390         irq = platform_get_irq(pmu_device, 0);
 391         if (irq <= 0)
 392                 return;
 393
 394         if (irq_is_percpu(irq)) {
 395                 on_each_cpu(armpmu_disable_percpu_irq, &irq, 1);
 396                 free_percpu_irq(irq, &cpu_hw_events);
 397         } else {
 398                 for (i = 0; i < irqs; ++i) {
 399                         if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
 400                                 continue;
 401                         irq = platform_get_irq(pmu_device, i);
 402                         if (irq > 0)
 403                                 free_irq(irq, armpmu);
 404                 }
 405         }
 406 }
 407
 408 static void
 409 armpmu_enable_percpu_irq(void *data)
 410 {
 411         unsigned int irq = *(unsigned int *)data;
 412         enable_percpu_irq(irq, IRQ_TYPE_NONE);
 413 }
 414
 415 static int
 416 armpmu_reserve_hardware(struct arm_pmu *armpmu)
 417 {
 418         int err, irq;
 419         unsigned int i, irqs;
 420         struct platform_device *pmu_device = armpmu->plat_device;
 421
 422         if (!pmu_device) {
 423                 pr_err("no PMU device registered\n");
 424                 return -ENODEV;
 425         }
 426
 427         irqs = min(pmu_device->num_resources, num_possible_cpus());
 428         if (!irqs) {
 429                 pr_err("no irqs for PMUs defined\n");
 430                 return -ENODEV;
 431         }
 432
 433         irq = platform_get_irq(pmu_device, 0);
 434         if (irq <= 0) {
 435                 pr_err("failed to get valid irq for PMU device\n");
 436                 return -ENODEV;
 437         }
 438
 439         if (irq_is_percpu(irq)) {
 440                 err = request_percpu_irq(irq, armpmu->handle_irq,
 441                                 "arm-pmu", &cpu_hw_events);
 442
 443                 if (err) {
 444                         pr_err("unable to request percpu IRQ%d for ARM PMU counters\n",
 445                                         irq);
 446                         armpmu_release_hardware(armpmu);
 447                         return err;
 448                 }
 449
 450                 on_each_cpu(armpmu_enable_percpu_irq, &irq, 1);
 451         } else {
 452                 for (i = 0; i < irqs; ++i) {
 453                         err = 0;
 454                         irq = platform_get_irq(pmu_device, i);
 455                         if (irq <= 0)
 456                                 continue;
 457
 458                         /*
 459                          * If we have a single PMU interrupt that we can't shift,
 460                          * assume that we're running on a uniprocessor machine and
 461                          * continue. Otherwise, continue without this interrupt.
 462                          */
 463                         if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
 464                                 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
 465                                                 irq, i);
 466                                 continue;
 467                         }
 468
 469                         err = request_irq(irq, armpmu->handle_irq,
 470                                         IRQF_NOBALANCING,
 471                                         "arm-pmu", armpmu);
 472                         if (err) {
 473                                 pr_err("unable to request IRQ%d for ARM PMU counters\n",
 474                                                 irq);
 475                                 armpmu_release_hardware(armpmu);
 476                                 return err;
 477                         }
 478
 479                         cpumask_set_cpu(i, &armpmu->active_irqs);
 480                 }
 481         }
 482
 483         return 0;
 484 }
 485
 486 static void
 487 hw_perf_event_destroy(struct perf_event *event)
 488 {
 489         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 490         atomic_t *active_events  = &armpmu->active_events;
 491         struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
 492
 493         if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
 494                 armpmu_release_hardware(armpmu);
 495                 mutex_unlock(pmu_reserve_mutex);
 496         }
 497 }
 498
 499 static int
 500 event_requires_mode_exclusion(struct perf_event_attr *attr)
 501 {
 502         return attr->exclude_idle || attr->exclude_user ||
 503                attr->exclude_kernel || attr->exclude_hv;
 504 }
 505
 506 static int
 507 __hw_perf_event_init(struct perf_event *event)
 508 {
 509         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 510         struct hw_perf_event *hwc = &event->hw;
 511         int mapping, err;
 512
 513         mapping = armpmu->map_event(event);
 514
 515         if (mapping < 0) {
 516                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 517                          event->attr.config);
 518                 return mapping;
 519         }
 520
 521         /*
 522          * We don't assign an index until we actually place the event onto
 523          * hardware. Use -1 to signify that we haven't decided where to put it
 524          * yet. For SMP systems, each core has it's own PMU so we can't do any
 525          * clever allocation or constraints checking at this point.
 526          */
 527         hwc->idx                = -1;
 528         hwc->config_base        = 0;
 529         hwc->config             = 0;
 530         hwc->event_base         = 0;
 531
 532         /*
 533          * Check whether we need to exclude the counter from certain modes.
 534          */
 535         if ((!armpmu->set_event_filter ||
 536              armpmu->set_event_filter(hwc, &event->attr)) &&
 537              event_requires_mode_exclusion(&event->attr)) {
 538                 pr_debug("ARM performance counters do not support mode exclusion\n");
 539                 return -EPERM;
 540         }
 541
 542         /*
 543          * Store the event encoding into the config_base field.
 544          */
 545         hwc->config_base            |= (unsigned long)mapping;
 546
 547         if (!hwc->sample_period) {
 548                 /*
 549                  * For non-sampling runs, limit the sample_period to half
 550                  * of the counter width. That way, the new counter value
 551                  * is far less likely to overtake the previous one unless
 552                  * you have some serious IRQ latency issues.
 553                  */
 554                 hwc->sample_period  = armpmu->max_period >> 1;
 555                 hwc->last_period    = hwc->sample_period;
 556                 local64_set(&hwc->period_left, hwc->sample_period);
 557         }
 558
 559         err = 0;
 560         if (event->group_leader != event) {
 561                 err = validate_group(event);
 562                 if (err)
 563                         return -EINVAL;
 564         }
 565
 566         return err;
 567 }
 568
 569 static int armpmu_event_init(struct perf_event *event)
 570 {
 571         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 572         int err = 0;
 573         atomic_t *active_events = &armpmu->active_events;
 574
 575         if (armpmu->map_event(event) == -ENOENT)
 576                 return -ENOENT;
 577
 578         event->destroy = hw_perf_event_destroy;
 579
 580         if (!atomic_inc_not_zero(active_events)) {
 581                 mutex_lock(&armpmu->reserve_mutex);
 582                 if (atomic_read(active_events) == 0)
 583                         err = armpmu_reserve_hardware(armpmu);
 584
 585                 if (!err)
 586                         atomic_inc(active_events);
 587                 mutex_unlock(&armpmu->reserve_mutex);
 588         }
 589
 590         if (err)
 591                 return err;
 592
 593         err = __hw_perf_event_init(event);
 594         if (err)
 595                 hw_perf_event_destroy(event);
 596
 597         return err;
 598 }
 599
 600 static void armpmu_enable(struct pmu *pmu)
 601 {
 602         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 603         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 604         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 605
 606         if (enabled)
 607                 armpmu->start();
 608 }
 609
 610 static void armpmu_disable(struct pmu *pmu)
 611 {
 612         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 613         armpmu->stop();
 614 }
 615
 616 static void __init armpmu_init(struct arm_pmu *armpmu)
 617 {
 618         atomic_set(&armpmu->active_events, 0);
 619         mutex_init(&armpmu->reserve_mutex);
 620
 621         armpmu->pmu = (struct pmu) {
 622                 .pmu_enable     = armpmu_enable,
 623                 .pmu_disable    = armpmu_disable,
 624                 .event_init     = armpmu_event_init,
 625                 .add            = armpmu_add,
 626                 .del            = armpmu_del,
 627                 .start          = armpmu_start,
 628                 .stop           = armpmu_stop,
 629                 .read           = armpmu_read,
 630         };
 631 }
 632
 633 int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
 634 {
 635         armpmu_init(armpmu);
 636         return perf_pmu_register(&armpmu->pmu, name, type);
 637 }
 638
 639 /*
 640  * ARMv8 PMUv3 Performance Events handling code.
 641  * Common event types.
 642  */
 643 enum armv8_pmuv3_perf_types {
 644         /* Required events. */
 645         ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR                        = 0x00,
 646         ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL                    = 0x03,
 647         ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS                    = 0x04,
 648         ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED                  = 0x10,
 649         ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES                        = 0x11,
 650         ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED                      = 0x12,
 651
 652         /* At least one of the following is required. */
 653         ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED                      = 0x08,
 654         ARMV8_PMUV3_PERFCTR_OP_SPEC                             = 0x1B,
 655
 656         /* Common architectural events. */
 657         ARMV8_PMUV3_PERFCTR_MEM_READ                            = 0x06,
 658         ARMV8_PMUV3_PERFCTR_MEM_WRITE                           = 0x07,
 659         ARMV8_PMUV3_PERFCTR_EXC_TAKEN                           = 0x09,
 660         ARMV8_PMUV3_PERFCTR_EXC_EXECUTED                        = 0x0A,
 661         ARMV8_PMUV3_PERFCTR_CID_WRITE                           = 0x0B,
 662         ARMV8_PMUV3_PERFCTR_PC_WRITE                            = 0x0C,
 663         ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH                       = 0x0D,
 664         ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN                      = 0x0E,
 665         ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS                = 0x0F,
 666         ARMV8_PMUV3_PERFCTR_TTBR_WRITE                          = 0x1C,
 667
 668         /* Common microarchitectural events. */
 669         ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL                    = 0x01,
 670         ARMV8_PMUV3_PERFCTR_ITLB_REFILL                         = 0x02,
 671         ARMV8_PMUV3_PERFCTR_DTLB_REFILL                         = 0x05,
 672         ARMV8_PMUV3_PERFCTR_MEM_ACCESS                          = 0x13,
 673         ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS                    = 0x14,
 674         ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB                        = 0x15,
 675         ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS                     = 0x16,
 676         ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL                     = 0x17,
 677         ARMV8_PMUV3_PERFCTR_L2_CACHE_WB                         = 0x18,
 678         ARMV8_PMUV3_PERFCTR_BUS_ACCESS                          = 0x19,
 679         ARMV8_PMUV3_PERFCTR_MEM_ERROR                           = 0x1A,
 680         ARMV8_PMUV3_PERFCTR_BUS_CYCLES                          = 0x1D,
 681 };
 682
 683 /* PMUv3 HW events mapping. */
 684 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
 685         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
 686         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
 687         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
 688         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
 689         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = HW_OP_UNSUPPORTED,
 690         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 691         [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
 692         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
 693         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = HW_OP_UNSUPPORTED,
 694 };
 695
 696 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 697                                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 698                                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 699         [C(L1D)] = {
 700                 [C(OP_READ)] = {
 701                         [C(RESULT_ACCESS)]      = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
 702                         [C(RESULT_MISS)]        = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
 703                 },
 704                 [C(OP_WRITE)] = {
 705                         [C(RESULT_ACCESS)]      = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
 706                         [C(RESULT_MISS)]        = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
 707                 },
 708                 [C(OP_PREFETCH)] = {
 709                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 710                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 711                 },
 712         },
 713         [C(L1I)] = {
 714                 [C(OP_READ)] = {
 715                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 716                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 717                 },
 718                 [C(OP_WRITE)] = {
 719                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 720                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 721                 },
 722                 [C(OP_PREFETCH)] = {
 723                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 724                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 725                 },
 726         },
 727         [C(LL)] = {
 728                 [C(OP_READ)] = {
 729                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 730                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 731                 },
 732                 [C(OP_WRITE)] = {
 733                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 734                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 735                 },
 736                 [C(OP_PREFETCH)] = {
 737                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 738                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 739                 },
 740         },
 741         [C(DTLB)] = {
 742                 [C(OP_READ)] = {
 743                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 744                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 745                 },
 746                 [C(OP_WRITE)] = {
 747                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 748                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 749                 },
 750                 [C(OP_PREFETCH)] = {
 751                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 752                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 753                 },
 754         },
 755         [C(ITLB)] = {
 756                 [C(OP_READ)] = {
 757                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 758                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 759                 },
 760                 [C(OP_WRITE)] = {
 761                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 762                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 763                 },
 764                 [C(OP_PREFETCH)] = {
 765                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 766                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 767                 },
 768         },
 769         [C(BPU)] = {
 770                 [C(OP_READ)] = {
 771                         [C(RESULT_ACCESS)]      = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
 772                         [C(RESULT_MISS)]        = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 773                 },
 774                 [C(OP_WRITE)] = {
 775                         [C(RESULT_ACCESS)]      = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
 776                         [C(RESULT_MISS)]        = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 777                 },
 778                 [C(OP_PREFETCH)] = {
 779                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 780                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 781                 },
 782         },
 783         [C(NODE)] = {
 784                 [C(OP_READ)] = {
 785                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 786                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 787                 },
 788                 [C(OP_WRITE)] = {
 789                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 790                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 791                 },
 792                 [C(OP_PREFETCH)] = {
 793                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 794                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 795                 },
 796         },
 797 };
 798
 799 /*
 800  * Perf Events' indices
 801  */
 802 #define ARMV8_IDX_CYCLE_COUNTER 0
 803 #define ARMV8_IDX_COUNTER0      1
 804 #define ARMV8_IDX_COUNTER_LAST  (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
 805
 806 #define ARMV8_MAX_COUNTERS      32
 807 #define ARMV8_COUNTER_MASK      (ARMV8_MAX_COUNTERS - 1)
 808
 809 /*
 810  * ARMv8 low level PMU access
 811  */
 812
 813 /*
 814  * Perf Event to low level counters mapping
 815  */
 816 #define ARMV8_IDX_TO_COUNTER(x) \
 817         (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK)
 818
 819 /*
 820  * Per-CPU PMCR: config reg
 821  */
 822 #define ARMV8_PMCR_E            (1 << 0) /* Enable all counters */
 823 #define ARMV8_PMCR_P            (1 << 1) /* Reset all counters */
 824 #define ARMV8_PMCR_C            (1 << 2) /* Cycle counter reset */
 825 #define ARMV8_PMCR_D            (1 << 3) /* CCNT counts every 64th cpu cycle */
 826 #define ARMV8_PMCR_X            (1 << 4) /* Export to ETM */
 827 #define ARMV8_PMCR_DP           (1 << 5) /* Disable CCNT if non-invasive debug*/
 828 #define ARMV8_PMCR_N_SHIFT      11       /* Number of counters supported */
 829 #define ARMV8_PMCR_N_MASK       0x1f
 830 #define ARMV8_PMCR_MASK         0x3f     /* Mask for writable bits */
 831
 832 /*
 833  * PMOVSR: counters overflow flag status reg
 834  */
 835 #define ARMV8_OVSR_MASK         0xffffffff      /* Mask for writable bits */
 836 #define ARMV8_OVERFLOWED_MASK   ARMV8_OVSR_MASK
 837
 838 /*
 839  * PMXEVTYPER: Event selection reg
 840  */
 841 #define ARMV8_EVTYPE_MASK       0xc80003ff      /* Mask for writable bits */
 842 #define ARMV8_EVTYPE_EVENT      0x3ff           /* Mask for EVENT bits */
 843
 844 /*
 845  * Event filters for PMUv3
 846  */
 847 #define ARMV8_EXCLUDE_EL1       (1 << 31)
 848 #define ARMV8_EXCLUDE_EL0       (1 << 30)
 849 #define ARMV8_INCLUDE_EL2       (1 << 27)
 850
 851 static inline u32 armv8pmu_pmcr_read(void)
 852 {
 853         u32 val;
 854         asm volatile("mrs %0, pmcr_el0" : "=r" (val));
 855         return val;
 856 }
 857
 858 static inline void armv8pmu_pmcr_write(u32 val)
 859 {
 860         val &= ARMV8_PMCR_MASK;
 861         isb();
 862         asm volatile("msr pmcr_el0, %0" :: "r" (val));
 863 }
 864
 865 static inline int armv8pmu_has_overflowed(u32 pmovsr)
 866 {
 867         return pmovsr & ARMV8_OVERFLOWED_MASK;
 868 }
 869
 870 static inline int armv8pmu_counter_valid(int idx)
 871 {
 872         return idx >= ARMV8_IDX_CYCLE_COUNTER && idx <= ARMV8_IDX_COUNTER_LAST;
 873 }
 874
 875 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
 876 {
 877         int ret = 0;
 878         u32 counter;
 879
 880         if (!armv8pmu_counter_valid(idx)) {
 881                 pr_err("CPU%u checking wrong counter %d overflow status\n",
 882                         smp_processor_id(), idx);
 883         } else {
 884                 counter = ARMV8_IDX_TO_COUNTER(idx);
 885                 ret = pmnc & BIT(counter);
 886         }
 887
 888         return ret;
 889 }
 890
 891 static inline int armv8pmu_select_counter(int idx)
 892 {
 893         u32 counter;
 894
 895         if (!armv8pmu_counter_valid(idx)) {
 896                 pr_err("CPU%u selecting wrong PMNC counter %d\n",
 897                         smp_processor_id(), idx);
 898                 return -EINVAL;
 899         }
 900
 901         counter = ARMV8_IDX_TO_COUNTER(idx);
 902         asm volatile("msr pmselr_el0, %0" :: "r" (counter));
 903         isb();
 904
 905         return idx;
 906 }
 907
 908 static inline u32 armv8pmu_read_counter(int idx)
 909 {
 910         u32 value = 0;
 911
 912         if (!armv8pmu_counter_valid(idx))
 913                 pr_err("CPU%u reading wrong counter %d\n",
 914                         smp_processor_id(), idx);
 915         else if (idx == ARMV8_IDX_CYCLE_COUNTER)
 916                 asm volatile("mrs %0, pmccntr_el0" : "=r" (value));
 917         else if (armv8pmu_select_counter(idx) == idx)
 918                 asm volatile("mrs %0, pmxevcntr_el0" : "=r" (value));
 919
 920         return value;
 921 }
 922
 923 static inline void armv8pmu_write_counter(int idx, u32 value)
 924 {
 925         if (!armv8pmu_counter_valid(idx))
 926                 pr_err("CPU%u writing wrong counter %d\n",
 927                         smp_processor_id(), idx);
 928         else if (idx == ARMV8_IDX_CYCLE_COUNTER)
 929                 asm volatile("msr pmccntr_el0, %0" :: "r" (value));
 930         else if (armv8pmu_select_counter(idx) == idx)
 931                 asm volatile("msr pmxevcntr_el0, %0" :: "r" (value));
 932 }
 933
 934 static inline void armv8pmu_write_evtype(int idx, u32 val)
 935 {
 936         if (armv8pmu_select_counter(idx) == idx) {
 937                 val &= ARMV8_EVTYPE_MASK;
 938                 asm volatile("msr pmxevtyper_el0, %0" :: "r" (val));
 939         }
 940 }
 941
 942 static inline int armv8pmu_enable_counter(int idx)
 943 {
 944         u32 counter;
 945
 946         if (!armv8pmu_counter_valid(idx)) {
 947                 pr_err("CPU%u enabling wrong PMNC counter %d\n",
 948                         smp_processor_id(), idx);
 949                 return -EINVAL;
 950         }
 951
 952         counter = ARMV8_IDX_TO_COUNTER(idx);
 953         asm volatile("msr pmcntenset_el0, %0" :: "r" (BIT(counter)));
 954         return idx;
 955 }
 956
 957 static inline int armv8pmu_disable_counter(int idx)
 958 {
 959         u32 counter;
 960
 961         if (!armv8pmu_counter_valid(idx)) {
 962                 pr_err("CPU%u disabling wrong PMNC counter %d\n",
 963                         smp_processor_id(), idx);
 964                 return -EINVAL;
 965         }
 966
 967         counter = ARMV8_IDX_TO_COUNTER(idx);
 968         asm volatile("msr pmcntenclr_el0, %0" :: "r" (BIT(counter)));
 969         return idx;
 970 }
 971
 972 static inline int armv8pmu_enable_intens(int idx)
 973 {
 974         u32 counter;
 975
 976         if (!armv8pmu_counter_valid(idx)) {
 977                 pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
 978                         smp_processor_id(), idx);
 979                 return -EINVAL;
 980         }
 981
 982         counter = ARMV8_IDX_TO_COUNTER(idx);
 983         asm volatile("msr pmintenset_el1, %0" :: "r" (BIT(counter)));
 984         return idx;
 985 }
 986
 987 static inline int armv8pmu_disable_intens(int idx)
 988 {
 989         u32 counter;
 990
 991         if (!armv8pmu_counter_valid(idx)) {
 992                 pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
 993                         smp_processor_id(), idx);
 994                 return -EINVAL;
 995         }
 996
 997         counter = ARMV8_IDX_TO_COUNTER(idx);
 998         asm volatile("msr pmintenclr_el1, %0" :: "r" (BIT(counter)));
 999         isb();
1000         /* Clear the overflow flag in case an interrupt is pending. */
1001         asm volatile("msr pmovsclr_el0, %0" :: "r" (BIT(counter)));
1002         isb();
1003         return idx;
1004 }
1005
1006 static inline u32 armv8pmu_getreset_flags(void)
1007 {
1008         u32 value;
1009
1010         /* Read */
1011         asm volatile("mrs %0, pmovsclr_el0" : "=r" (value));
1012
1013         /* Write to clear flags */
1014         value &= ARMV8_OVSR_MASK;
1015         asm volatile("msr pmovsclr_el0, %0" :: "r" (value));
1016
1017         return value;
1018 }
1019
1020 static void armv8pmu_enable_event(struct hw_perf_event *hwc, int idx)
1021 {
1022         unsigned long flags;
1023         struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1024
1025         /*
1026          * Enable counter and interrupt, and set the counter to count
1027          * the event that we're interested in.
1028          */
1029         raw_spin_lock_irqsave(&events->pmu_lock, flags);
1030
1031         /*
1032          * Disable counter
1033          */
1034         armv8pmu_disable_counter(idx);
1035
1036         /*
1037          * Set event (if destined for PMNx counters).
1038          */
1039         armv8pmu_write_evtype(idx, hwc->config_base);
1040
1041         /*
1042          * Enable interrupt for this counter
1043          */
1044         armv8pmu_enable_intens(idx);
1045
1046         /*
1047          * Enable counter
1048          */
1049         armv8pmu_enable_counter(idx);
1050
1051         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1052 }
1053
1054 static void armv8pmu_disable_event(struct hw_perf_event *hwc, int idx)
1055 {
1056         unsigned long flags;
1057         struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1058
1059         /*
1060          * Disable counter and interrupt
1061          */
1062         raw_spin_lock_irqsave(&events->pmu_lock, flags);
1063
1064         /*
1065          * Disable counter
1066          */
1067         armv8pmu_disable_counter(idx);
1068
1069         /*
1070          * Disable interrupt for this counter
1071          */
1072         armv8pmu_disable_intens(idx);
1073
1074         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1075 }
1076
1077 static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
1078 {
1079         u32 pmovsr;
1080         struct perf_sample_data data;
1081         struct pmu_hw_events *cpuc;
1082         struct pt_regs *regs;
1083         int idx;
1084
1085         /*
1086          * Get and reset the IRQ flags
1087          */
1088         pmovsr = armv8pmu_getreset_flags();
1089
1090         /*
1091          * Did an overflow occur?
1092          */
1093         if (!armv8pmu_has_overflowed(pmovsr))
1094                 return IRQ_NONE;
1095
1096         /*
1097          * Handle the counter(s) overflow(s)
1098          */
1099         regs = get_irq_regs();
1100
1101         cpuc = this_cpu_ptr(&cpu_hw_events);
1102         for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
1103                 struct perf_event *event = cpuc->events[idx];
1104                 struct hw_perf_event *hwc;
1105
1106                 /* Ignore if we don't have an event. */
1107                 if (!event)
1108                         continue;
1109
1110                 /*
1111                  * We have a single interrupt for all counters. Check that
1112                  * each counter has overflowed before we process it.
1113                  */
1114                 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
1115                         continue;
1116
1117                 hwc = &event->hw;
1118                 armpmu_event_update(event, hwc, idx);
1119                 perf_sample_data_init(&data, 0, hwc->last_period);
1120                 if (!armpmu_event_set_period(event, hwc, idx))
1121                         continue;
1122
1123                 if (perf_event_overflow(event, &data, regs))
1124                         cpu_pmu->disable(hwc, idx);
1125         }
1126
1127         /*
1128          * Handle the pending perf events.
1129          *
1130          * Note: this call *must* be run with interrupts disabled. For
1131          * platforms that can have the PMU interrupts raised as an NMI, this
1132          * will not work.
1133          */
1134         irq_work_run();
1135
1136         return IRQ_HANDLED;
1137 }
1138
1139 static void armv8pmu_start(void)
1140 {
1141         unsigned long flags;
1142         struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1143
1144         raw_spin_lock_irqsave(&events->pmu_lock, flags);
1145         /* Enable all counters */
1146         armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMCR_E);
1147         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1148 }
1149
1150 static void armv8pmu_stop(void)
1151 {
1152         unsigned long flags;
1153         struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1154
1155         raw_spin_lock_irqsave(&events->pmu_lock, flags);
1156         /* Disable all counters */
1157         armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMCR_E);
1158         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1159 }
1160
1161 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
1162                                   struct hw_perf_event *event)
1163 {
1164         int idx;
1165         unsigned long evtype = event->config_base & ARMV8_EVTYPE_EVENT;
1166
1167         /* Always place a cycle counter into the cycle counter. */
1168         if (evtype == ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES) {
1169                 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
1170                         return -EAGAIN;
1171
1172                 return ARMV8_IDX_CYCLE_COUNTER;
1173         }
1174
1175         /*
1176          * For anything other than a cycle counter, try and use
1177          * the events counters
1178          */
1179         for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
1180                 if (!test_and_set_bit(idx, cpuc->used_mask))
1181                         return idx;
1182         }
1183
1184         /* The counters are all in use. */
1185         return -EAGAIN;
1186 }
1187
1188 /*
1189  * Add an event filter to a given event. This will only work for PMUv2 PMUs.
1190  */
1191 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
1192                                      struct perf_event_attr *attr)
1193 {
1194         unsigned long config_base = 0;
1195
1196         if (attr->exclude_idle)
1197                 return -EPERM;
1198         if (attr->exclude_user)
1199                 config_base |= ARMV8_EXCLUDE_EL0;
1200         if (attr->exclude_kernel)
1201                 config_base |= ARMV8_EXCLUDE_EL1;
1202         if (!attr->exclude_hv)
1203                 config_base |= ARMV8_INCLUDE_EL2;
1204
1205         /*
1206          * Install the filter into config_base as this is used to
1207          * construct the event type.
1208          */
1209         event->config_base = config_base;
1210
1211         return 0;
1212 }
1213
1214 static void armv8pmu_reset(void *info)
1215 {
1216         u32 idx, nb_cnt = cpu_pmu->num_events;
1217
1218         /* The counter and interrupt enable registers are unknown at reset. */
1219         for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx)
1220                 armv8pmu_disable_event(NULL, idx);
1221
1222         /* Initialize & Reset PMNC: C and P bits. */
1223         armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C);
1224
1225         /* Disable access from userspace. */
1226         asm volatile("msr pmuserenr_el0, %0" :: "r" (0));
1227 }
1228
1229 static int armv8_pmuv3_map_event(struct perf_event *event)
1230 {
1231         return map_cpu_event(event, &armv8_pmuv3_perf_map,
1232                                 &armv8_pmuv3_perf_cache_map,
1233                                 ARMV8_EVTYPE_EVENT);
1234 }
1235
1236 static struct arm_pmu armv8pmu = {
1237         .handle_irq             = armv8pmu_handle_irq,
1238         .enable                 = armv8pmu_enable_event,
1239         .disable                = armv8pmu_disable_event,
1240         .read_counter           = armv8pmu_read_counter,
1241         .write_counter          = armv8pmu_write_counter,
1242         .get_event_idx          = armv8pmu_get_event_idx,
1243         .start                  = armv8pmu_start,
1244         .stop                   = armv8pmu_stop,
1245         .reset                  = armv8pmu_reset,
1246         .max_period             = (1LLU << 32) - 1,
1247 };
1248
1249 static u32 __init armv8pmu_read_num_pmnc_events(void)
1250 {
1251         u32 nb_cnt;
1252
1253         /* Read the nb of CNTx counters supported from PMNC */
1254         nb_cnt = (armv8pmu_pmcr_read() >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
1255
1256         /* Add the CPU cycles counter and return */
1257         return nb_cnt + 1;
1258 }
1259
1260 static struct arm_pmu *__init armv8_pmuv3_pmu_init(void)
1261 {
1262         armv8pmu.name                   = "arm/armv8-pmuv3";
1263         armv8pmu.map_event              = armv8_pmuv3_map_event;
1264         armv8pmu.num_events             = armv8pmu_read_num_pmnc_events();
1265         armv8pmu.set_event_filter       = armv8pmu_set_event_filter;
1266         return &armv8pmu;
1267 }
1268
1269 /*
1270  * Ensure the PMU has sane values out of reset.
1271  * This requires SMP to be available, so exists as a separate initcall.
1272  */
1273 static int __init
1274 cpu_pmu_reset(void)
1275 {
1276         if (cpu_pmu && cpu_pmu->reset)
1277                 return on_each_cpu(cpu_pmu->reset, NULL, 1);
1278         return 0;
1279 }
1280 arch_initcall(cpu_pmu_reset);
1281
1282 /*
1283  * PMU platform driver and devicetree bindings.
1284  */
1285 static const struct of_device_id armpmu_of_device_ids[] = {
1286         {.compatible = "arm,armv8-pmuv3"},
1287         {},
1288 };
1289
1290 static int armpmu_device_probe(struct platform_device *pdev)
1291 {
1292         if (!cpu_pmu)
1293                 return -ENODEV;
1294
1295         cpu_pmu->plat_device = pdev;
1296         return 0;
1297 }
1298
1299 static struct platform_driver armpmu_driver = {
1300         .driver         = {
1301                 .name   = "arm-pmu",
1302                 .of_match_table = armpmu_of_device_ids,
1303         },
1304         .probe          = armpmu_device_probe,
1305 };
1306
1307 static int __init register_pmu_driver(void)
1308 {
1309         return platform_driver_register(&armpmu_driver);
1310 }
1311 device_initcall(register_pmu_driver);
1312
1313 static struct pmu_hw_events *armpmu_get_cpu_events(void)
1314 {
1315         return this_cpu_ptr(&cpu_hw_events);
1316 }
1317
1318 static void __init cpu_pmu_init(struct arm_pmu *armpmu)
1319 {
1320         int cpu;
1321         for_each_possible_cpu(cpu) {
1322                 struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
1323                 events->events = per_cpu(hw_events, cpu);
1324                 events->used_mask = per_cpu(used_mask, cpu);
1325                 raw_spin_lock_init(&events->pmu_lock);
1326         }
1327         armpmu->get_hw_events = armpmu_get_cpu_events;
1328 }
1329
1330 static int __init init_hw_perf_events(void)
1331 {
1332         u64 dfr = read_cpuid(ID_AA64DFR0_EL1);
1333
1334         switch ((dfr >> 8) & 0xf) {
1335         case 0x1:       /* PMUv3 */
1336                 cpu_pmu = armv8_pmuv3_pmu_init();
1337                 break;
1338         }
1339
1340         if (cpu_pmu) {
1341                 pr_info("enabled with %s PMU driver, %d counters available\n",
1342                         cpu_pmu->name, cpu_pmu->num_events);
1343                 cpu_pmu_init(cpu_pmu);
1344                 armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
1345         } else {
1346                 pr_info("no hardware support available\n");
1347         }
1348
1349         return 0;
1350 }
1351 early_initcall(init_hw_perf_events);
1352
1353 /*
1354  * Callchain handling code.
1355  */
1356 struct frame_tail {
1357         struct frame_tail       __user *fp;
1358         unsigned long           lr;
1359 } __attribute__((packed));
1360
1361 /*
1362  * Get the return address for a single stackframe and return a pointer to the
1363  * next frame tail.
1364  */
1365 static struct frame_tail __user *
1366 user_backtrace(struct frame_tail __user *tail,
1367                struct perf_callchain_entry *entry)
1368 {
1369         struct frame_tail buftail;
1370         unsigned long err;
1371
1372         /* Also check accessibility of one struct frame_tail beyond */
1373         if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
1374                 return NULL;
1375
1376         pagefault_disable();
1377         err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
1378         pagefault_enable();
1379
1380         if (err)
1381                 return NULL;
1382
1383         perf_callchain_store(entry, buftail.lr);
1384
1385         /*
1386          * Frame pointers should strictly progress back up the stack
1387          * (towards higher addresses).
1388          */
1389         if (tail >= buftail.fp)
1390                 return NULL;
1391
1392         return buftail.fp;
1393 }
1394
1395 #ifdef CONFIG_COMPAT
1396 /*
1397  * The registers we're interested in are at the end of the variable
1398  * length saved register structure. The fp points at the end of this
1399  * structure so the address of this struct is:
1400  * (struct compat_frame_tail *)(xxx->fp)-1
1401  *
1402  * This code has been adapted from the ARM OProfile support.
1403  */
1404 struct compat_frame_tail {
1405         compat_uptr_t   fp; /* a (struct compat_frame_tail *) in compat mode */
1406         u32             sp;
1407         u32             lr;
1408 } __attribute__((packed));
1409
1410 static struct compat_frame_tail __user *
1411 compat_user_backtrace(struct compat_frame_tail __user *tail,
1412                       struct perf_callchain_entry *entry)
1413 {
1414         struct compat_frame_tail buftail;
1415         unsigned long err;
1416
1417         /* Also check accessibility of one struct frame_tail beyond */
1418         if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
1419                 return NULL;
1420
1421         pagefault_disable();
1422         err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
1423         pagefault_enable();
1424
1425         if (err)
1426                 return NULL;
1427
1428         perf_callchain_store(entry, buftail.lr);
1429
1430         /*
1431          * Frame pointers should strictly progress back up the stack
1432          * (towards higher addresses).
1433          */
1434         if (tail + 1 >= (struct compat_frame_tail __user *)
1435                         compat_ptr(buftail.fp))
1436                 return NULL;
1437
1438         return (struct compat_frame_tail __user *)compat_ptr(buftail.fp) - 1;
1439 }
1440 #endif /* CONFIG_COMPAT */
1441
1442 void perf_callchain_user(struct perf_callchain_entry *entry,
1443                          struct pt_regs *regs)
1444 {
1445         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1446                 /* We don't support guest os callchain now */
1447                 return;
1448         }
1449
1450         perf_callchain_store(entry, regs->pc);
1451
1452         if (!compat_user_mode(regs)) {
1453                 /* AARCH64 mode */
1454                 struct frame_tail __user *tail;
1455
1456                 tail = (struct frame_tail __user *)regs->regs[29];
1457
1458                 while (entry->nr < PERF_MAX_STACK_DEPTH &&
1459                        tail && !((unsigned long)tail & 0xf))
1460                         tail = user_backtrace(tail, entry);
1461         } else {
1462 #ifdef CONFIG_COMPAT
1463                 /* AARCH32 compat mode */
1464                 struct compat_frame_tail __user *tail;
1465
1466                 tail = (struct compat_frame_tail __user *)regs->compat_fp - 1;
1467
1468                 while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
1469                         tail && !((unsigned long)tail & 0x3))
1470                         tail = compat_user_backtrace(tail, entry);
1471 #endif
1472         }
1473 }
1474
1475 /*
1476  * Gets called by walk_stackframe() for every stackframe. This will be called
1477  * whist unwinding the stackframe and is like a subroutine return so we use
1478  * the PC.
1479  */
1480 static int callchain_trace(struct stackframe *frame, void *data)
1481 {
1482         struct perf_callchain_entry *entry = data;
1483         perf_callchain_store(entry, frame->pc);
1484         return 0;
1485 }
1486
1487 void perf_callchain_kernel(struct perf_callchain_entry *entry,
1488                            struct pt_regs *regs)
1489 {
1490         struct stackframe frame;
1491
1492         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1493                 /* We don't support guest os callchain now */
1494                 return;
1495         }
1496
1497         frame.fp = regs->regs[29];
1498         frame.sp = regs->sp;
1499         frame.pc = regs->pc;
1500
1501         walk_stackframe(&frame, callchain_trace, entry);
1502 }
1503
1504 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1505 {
1506         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1507                 return perf_guest_cbs->get_guest_ip();
1508
1509         return instruction_pointer(regs);
1510 }
1511
1512 unsigned long perf_misc_flags(struct pt_regs *regs)
1513 {
1514         int misc = 0;
1515
1516         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1517                 if (perf_guest_cbs->is_user_mode())
1518                         misc |= PERF_RECORD_MISC_GUEST_USER;
1519                 else
1520                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1521         } else {
1522                 if (user_mode(regs))
1523                         misc |= PERF_RECORD_MISC_USER;
1524                 else
1525                         misc |= PERF_RECORD_MISC_KERNEL;
1526         }
1527
1528         return misc;
1529 }