arch/arm64/kernel/armv8_deprecated.c

   1 /*
   2  *  Copyright (C) 2014 ARM Limited
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/cpu.h>
  10 #include <linux/init.h>
  11 #include <linux/list.h>
  12 #include <linux/perf_event.h>
  13 #include <linux/sched.h>
  14 #include <linux/slab.h>
  15 #include <linux/sysctl.h>
  16
  17 #include <asm/cpufeature.h>
  18 #include <asm/insn.h>
  19 #include <asm/sysreg.h>
  20 #include <asm/system_misc.h>
  21 #include <asm/traps.h>
  22 #include <asm/kprobes.h>
  23 #include <linux/uaccess.h>
  24 #include <asm/cpufeature.h>
  25
  26 #define CREATE_TRACE_POINTS
  27 #include "trace-events-emulation.h"
  28
  29 /*
  30  * The runtime support for deprecated instruction support can be in one of
  31  * following three states -
  32  *
  33  * 0 = undef
  34  * 1 = emulate (software emulation)
  35  * 2 = hw (supported in hardware)
  36  */
  37 enum insn_emulation_mode {
  38         INSN_UNDEF,
  39         INSN_EMULATE,
  40         INSN_HW,
  41 };
  42
  43 enum legacy_insn_status {
  44         INSN_DEPRECATED,
  45         INSN_OBSOLETE,
  46 };
  47
  48 struct insn_emulation_ops {
  49         const char              *name;
  50         enum legacy_insn_status status;
  51         struct undef_hook       *hooks;
  52         int                     (*set_hw_mode)(bool enable);
  53 };
  54
  55 struct insn_emulation {
  56         struct list_head node;
  57         struct insn_emulation_ops *ops;
  58         int current_mode;
  59         int min;
  60         int max;
  61 };
  62
  63 static LIST_HEAD(insn_emulation);
  64 static int nr_insn_emulated __initdata;
  65 static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
  66
  67 static void register_emulation_hooks(struct insn_emulation_ops *ops)
  68 {
  69         struct undef_hook *hook;
  70
  71         BUG_ON(!ops->hooks);
  72
  73         for (hook = ops->hooks; hook->instr_mask; hook++)
  74                 register_undef_hook(hook);
  75
  76         pr_notice("Registered %s emulation handler\n", ops->name);
  77 }
  78
  79 static void remove_emulation_hooks(struct insn_emulation_ops *ops)
  80 {
  81         struct undef_hook *hook;
  82
  83         BUG_ON(!ops->hooks);
  84
  85         for (hook = ops->hooks; hook->instr_mask; hook++)
  86                 unregister_undef_hook(hook);
  87
  88         pr_notice("Removed %s emulation handler\n", ops->name);
  89 }
  90
  91 static void enable_insn_hw_mode(void *data)
  92 {
  93         struct insn_emulation *insn = (struct insn_emulation *)data;
  94         if (insn->ops->set_hw_mode)
  95                 insn->ops->set_hw_mode(true);
  96 }
  97
  98 static void disable_insn_hw_mode(void *data)
  99 {
 100         struct insn_emulation *insn = (struct insn_emulation *)data;
 101         if (insn->ops->set_hw_mode)
 102                 insn->ops->set_hw_mode(false);
 103 }
 104
 105 /* Run set_hw_mode(mode) on all active CPUs */
 106 static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
 107 {
 108         if (!insn->ops->set_hw_mode)
 109                 return -EINVAL;
 110         if (enable)
 111                 on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
 112         else
 113                 on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
 114         return 0;
 115 }
 116
 117 /*
 118  * Run set_hw_mode for all insns on a starting CPU.
 119  * Returns:
 120  *  0           - If all the hooks ran successfully.
 121  * -EINVAL      - At least one hook is not supported by the CPU.
 122  */
 123 static int run_all_insn_set_hw_mode(unsigned int cpu)
 124 {
 125         int rc = 0;
 126         unsigned long flags;
 127         struct insn_emulation *insn;
 128
 129         raw_spin_lock_irqsave(&insn_emulation_lock, flags);
 130         list_for_each_entry(insn, &insn_emulation, node) {
 131                 bool enable = (insn->current_mode == INSN_HW);
 132                 if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
 133                         pr_warn("CPU[%u] cannot support the emulation of %s",
 134                                 cpu, insn->ops->name);
 135                         rc = -EINVAL;
 136                 }
 137         }
 138         raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
 139         return rc;
 140 }
 141
 142 static int update_insn_emulation_mode(struct insn_emulation *insn,
 143                                        enum insn_emulation_mode prev)
 144 {
 145         int ret = 0;
 146
 147         switch (prev) {
 148         case INSN_UNDEF: /* Nothing to be done */
 149                 break;
 150         case INSN_EMULATE:
 151                 remove_emulation_hooks(insn->ops);
 152                 break;
 153         case INSN_HW:
 154                 if (!run_all_cpu_set_hw_mode(insn, false))
 155                         pr_notice("Disabled %s support\n", insn->ops->name);
 156                 break;
 157         }
 158
 159         switch (insn->current_mode) {
 160         case INSN_UNDEF:
 161                 break;
 162         case INSN_EMULATE:
 163                 register_emulation_hooks(insn->ops);
 164                 break;
 165         case INSN_HW:
 166                 ret = run_all_cpu_set_hw_mode(insn, true);
 167                 if (!ret)
 168                         pr_notice("Enabled %s support\n", insn->ops->name);
 169                 break;
 170         }
 171
 172         return ret;
 173 }
 174
 175 static void __init register_insn_emulation(struct insn_emulation_ops *ops)
 176 {
 177         unsigned long flags;
 178         struct insn_emulation *insn;
 179
 180         insn = kzalloc(sizeof(*insn), GFP_KERNEL);
 181         insn->ops = ops;
 182         insn->min = INSN_UNDEF;
 183
 184         switch (ops->status) {
 185         case INSN_DEPRECATED:
 186                 insn->current_mode = INSN_EMULATE;
 187                 /* Disable the HW mode if it was turned on at early boot time */
 188                 run_all_cpu_set_hw_mode(insn, false);
 189                 insn->max = INSN_HW;
 190                 break;
 191         case INSN_OBSOLETE:
 192                 insn->current_mode = INSN_UNDEF;
 193                 insn->max = INSN_EMULATE;
 194                 break;
 195         }
 196
 197         raw_spin_lock_irqsave(&insn_emulation_lock, flags);
 198         list_add(&insn->node, &insn_emulation);
 199         nr_insn_emulated++;
 200         raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
 201
 202         /* Register any handlers if required */
 203         update_insn_emulation_mode(insn, INSN_UNDEF);
 204 }
 205
 206 static int emulation_proc_handler(struct ctl_table *table, int write,
 207                                   void __user *buffer, size_t *lenp,
 208                                   loff_t *ppos)
 209 {
 210         int ret = 0;
 211         struct insn_emulation *insn = (struct insn_emulation *) table->data;
 212         enum insn_emulation_mode prev_mode = insn->current_mode;
 213
 214         table->data = &insn->current_mode;
 215         ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
 216
 217         if (ret || !write || prev_mode == insn->current_mode)
 218                 goto ret;
 219
 220         ret = update_insn_emulation_mode(insn, prev_mode);
 221         if (ret) {
 222                 /* Mode change failed, revert to previous mode. */
 223                 insn->current_mode = prev_mode;
 224                 update_insn_emulation_mode(insn, INSN_UNDEF);
 225         }
 226 ret:
 227         table->data = insn;
 228         return ret;
 229 }
 230
 231 static struct ctl_table ctl_abi[] = {
 232         {
 233                 .procname = "abi",
 234                 .mode = 0555,
 235         },
 236         { }
 237 };
 238
 239 static void __init register_insn_emulation_sysctl(struct ctl_table *table)
 240 {
 241         unsigned long flags;
 242         int i = 0;
 243         struct insn_emulation *insn;
 244         struct ctl_table *insns_sysctl, *sysctl;
 245
 246         insns_sysctl = kzalloc(sizeof(*sysctl) * (nr_insn_emulated + 1),
 247                               GFP_KERNEL);
 248
 249         raw_spin_lock_irqsave(&insn_emulation_lock, flags);
 250         list_for_each_entry(insn, &insn_emulation, node) {
 251                 sysctl = &insns_sysctl[i];
 252
 253                 sysctl->mode = 0644;
 254                 sysctl->maxlen = sizeof(int);
 255
 256                 sysctl->procname = insn->ops->name;
 257                 sysctl->data = insn;
 258                 sysctl->extra1 = &insn->min;
 259                 sysctl->extra2 = &insn->max;
 260                 sysctl->proc_handler = emulation_proc_handler;
 261                 i++;
 262         }
 263         raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
 264
 265         table->child = insns_sysctl;
 266         register_sysctl_table(table);
 267 }
 268
 269 /*
 270  *  Implement emulation of the SWP/SWPB instructions using load-exclusive and
 271  *  store-exclusive.
 272  *
 273  *  Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
 274  *  Where: Rt  = destination
 275  *         Rt2 = source
 276  *         Rn  = address
 277  */
 278
 279 /*
 280  * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
 281  */
 282
 283 /* Arbitrary constant to ensure forward-progress of the LL/SC loop */
 284 #define __SWP_LL_SC_LOOPS       4
 285
 286 #define __user_swpX_asm(data, addr, res, temp, temp2, B)        \
 287 do {                                                            \
 288         uaccess_enable();                                       \
 289         __asm__ __volatile__(                                   \
 290         "       mov             %w3, %w7\n"                     \
 291         "0:     ldxr"B"         %w2, [%4]\n"                    \
 292         "1:     stxr"B"         %w0, %w1, [%4]\n"               \
 293         "       cbz             %w0, 2f\n"                      \
 294         "       sub             %w3, %w3, #1\n"                 \
 295         "       cbnz            %w3, 0b\n"                      \
 296         "       mov             %w0, %w5\n"                     \
 297         "       b               3f\n"                           \
 298         "2:\n"                                                  \
 299         "       mov             %w1, %w2\n"                     \
 300         "3:\n"                                                  \
 301         "       .pushsection     .fixup,\"ax\"\n"               \
 302         "       .align          2\n"                            \
 303         "4:     mov             %w0, %w6\n"                     \
 304         "       b               3b\n"                           \
 305         "       .popsection"                                    \
 306         _ASM_EXTABLE(0b, 4b)                                    \
 307         _ASM_EXTABLE(1b, 4b)                                    \
 308         : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \
 309         : "r" ((unsigned long)addr), "i" (-EAGAIN),             \
 310           "i" (-EFAULT),                                        \
 311           "i" (__SWP_LL_SC_LOOPS)                               \
 312         : "memory");                                            \
 313         uaccess_disable();                                      \
 314 } while (0)
 315
 316 #define __user_swp_asm(data, addr, res, temp, temp2) \
 317         __user_swpX_asm(data, addr, res, temp, temp2, "")
 318 #define __user_swpb_asm(data, addr, res, temp, temp2) \
 319         __user_swpX_asm(data, addr, res, temp, temp2, "b")
 320
 321 /*
 322  * Bit 22 of the instruction encoding distinguishes between
 323  * the SWP and SWPB variants (bit set means SWPB).
 324  */
 325 #define TYPE_SWPB (1 << 22)
 326
 327 static int emulate_swpX(unsigned int address, unsigned int *data,
 328                         unsigned int type)
 329 {
 330         unsigned int res = 0;
 331
 332         if ((type != TYPE_SWPB) && (address & 0x3)) {
 333                 /* SWP to unaligned address not permitted */
 334                 pr_debug("SWP instruction on unaligned pointer!\n");
 335                 return -EFAULT;
 336         }
 337
 338         while (1) {
 339                 unsigned long temp, temp2;
 340
 341                 if (type == TYPE_SWPB)
 342                         __user_swpb_asm(*data, address, res, temp, temp2);
 343                 else
 344                         __user_swp_asm(*data, address, res, temp, temp2);
 345
 346                 if (likely(res != -EAGAIN) || signal_pending(current))
 347                         break;
 348
 349                 cond_resched();
 350         }
 351
 352         return res;
 353 }
 354
 355 #define ARM_OPCODE_CONDTEST_FAIL   0
 356 #define ARM_OPCODE_CONDTEST_PASS   1
 357 #define ARM_OPCODE_CONDTEST_UNCOND 2
 358
 359 #define ARM_OPCODE_CONDITION_UNCOND     0xf
 360
 361 static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
 362 {
 363         u32 cc_bits  = opcode >> 28;
 364
 365         if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
 366                 if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
 367                         return ARM_OPCODE_CONDTEST_PASS;
 368                 else
 369                         return ARM_OPCODE_CONDTEST_FAIL;
 370         }
 371         return ARM_OPCODE_CONDTEST_UNCOND;
 372 }
 373
 374 /*
 375  * swp_handler logs the id of calling process, dissects the instruction, sanity
 376  * checks the memory location, calls emulate_swpX for the actual operation and
 377  * deals with fixup/error handling before returning
 378  */
 379 static int swp_handler(struct pt_regs *regs, u32 instr)
 380 {
 381         u32 destreg, data, type, address = 0;
 382         int rn, rt2, res = 0;
 383
 384         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 385
 386         type = instr & TYPE_SWPB;
 387
 388         switch (aarch32_check_condition(instr, regs->pstate)) {
 389         case ARM_OPCODE_CONDTEST_PASS:
 390                 break;
 391         case ARM_OPCODE_CONDTEST_FAIL:
 392                 /* Condition failed - return to next instruction */
 393                 goto ret;
 394         case ARM_OPCODE_CONDTEST_UNCOND:
 395                 /* If unconditional encoding - not a SWP, undef */
 396                 return -EFAULT;
 397         default:
 398                 return -EINVAL;
 399         }
 400
 401         rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
 402         rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
 403
 404         address = (u32)regs->user_regs.regs[rn];
 405         data    = (u32)regs->user_regs.regs[rt2];
 406         destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
 407
 408         pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
 409                 rn, address, destreg,
 410                 aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
 411
 412         /* Check access in reasonable access range for both SWP and SWPB */
 413         if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
 414                 pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
 415                         address);
 416                 goto fault;
 417         }
 418
 419         res = emulate_swpX(address, &data, type);
 420         if (res == -EFAULT)
 421                 goto fault;
 422         else if (res == 0)
 423                 regs->user_regs.regs[destreg] = data;
 424
 425 ret:
 426         if (type == TYPE_SWPB)
 427                 trace_instruction_emulation("swpb", regs->pc);
 428         else
 429                 trace_instruction_emulation("swp", regs->pc);
 430
 431         pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
 432                         current->comm, (unsigned long)current->pid, regs->pc);
 433
 434         regs->pc += 4;
 435         return 0;
 436
 437 fault:
 438         pr_debug("SWP{B} emulation: access caused memory abort!\n");
 439         arm64_notify_segfault(regs, address);
 440
 441         return 0;
 442 }
 443
 444 /*
 445  * Only emulate SWP/SWPB executed in ARM state/User mode.
 446  * The kernel must be SWP free and SWP{B} does not exist in Thumb.
 447  */
 448 static struct undef_hook swp_hooks[] = {
 449         {
 450                 .instr_mask     = 0x0fb00ff0,
 451                 .instr_val      = 0x01000090,
 452                 .pstate_mask    = COMPAT_PSR_MODE_MASK,
 453                 .pstate_val     = COMPAT_PSR_MODE_USR,
 454                 .fn             = swp_handler
 455         },
 456         { }
 457 };
 458
 459 static struct insn_emulation_ops swp_ops = {
 460         .name = "swp",
 461         .status = INSN_OBSOLETE,
 462         .hooks = swp_hooks,
 463         .set_hw_mode = NULL,
 464 };
 465
 466 static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
 467 {
 468         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 469
 470         switch (aarch32_check_condition(instr, regs->pstate)) {
 471         case ARM_OPCODE_CONDTEST_PASS:
 472                 break;
 473         case ARM_OPCODE_CONDTEST_FAIL:
 474                 /* Condition failed - return to next instruction */
 475                 goto ret;
 476         case ARM_OPCODE_CONDTEST_UNCOND:
 477                 /* If unconditional encoding - not a barrier instruction */
 478                 return -EFAULT;
 479         default:
 480                 return -EINVAL;
 481         }
 482
 483         switch (aarch32_insn_mcr_extract_crm(instr)) {
 484         case 10:
 485                 /*
 486                  * dmb - mcr p15, 0, Rt, c7, c10, 5
 487                  * dsb - mcr p15, 0, Rt, c7, c10, 4
 488                  */
 489                 if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
 490                         dmb(sy);
 491                         trace_instruction_emulation(
 492                                 "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
 493                 } else {
 494                         dsb(sy);
 495                         trace_instruction_emulation(
 496                                 "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
 497                 }
 498                 break;
 499         case 5:
 500                 /*
 501                  * isb - mcr p15, 0, Rt, c7, c5, 4
 502                  *
 503                  * Taking an exception or returning from one acts as an
 504                  * instruction barrier. So no explicit barrier needed here.
 505                  */
 506                 trace_instruction_emulation(
 507                         "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
 508                 break;
 509         }
 510
 511 ret:
 512         pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
 513                         current->comm, (unsigned long)current->pid, regs->pc);
 514
 515         regs->pc += 4;
 516         return 0;
 517 }
 518
 519 static int cp15_barrier_set_hw_mode(bool enable)
 520 {
 521         if (enable)
 522                 config_sctlr_el1(0, SCTLR_EL1_CP15BEN);
 523         else
 524                 config_sctlr_el1(SCTLR_EL1_CP15BEN, 0);
 525         return 0;
 526 }
 527
 528 static struct undef_hook cp15_barrier_hooks[] = {
 529         {
 530                 .instr_mask     = 0x0fff0fdf,
 531                 .instr_val      = 0x0e070f9a,
 532                 .pstate_mask    = COMPAT_PSR_MODE_MASK,
 533                 .pstate_val     = COMPAT_PSR_MODE_USR,
 534                 .fn             = cp15barrier_handler,
 535         },
 536         {
 537                 .instr_mask     = 0x0fff0fff,
 538                 .instr_val      = 0x0e070f95,
 539                 .pstate_mask    = COMPAT_PSR_MODE_MASK,
 540                 .pstate_val     = COMPAT_PSR_MODE_USR,
 541                 .fn             = cp15barrier_handler,
 542         },
 543         { }
 544 };
 545
 546 static struct insn_emulation_ops cp15_barrier_ops = {
 547         .name = "cp15_barrier",
 548         .status = INSN_DEPRECATED,
 549         .hooks = cp15_barrier_hooks,
 550         .set_hw_mode = cp15_barrier_set_hw_mode,
 551 };
 552
 553 static int setend_set_hw_mode(bool enable)
 554 {
 555         if (!cpu_supports_mixed_endian_el0())
 556                 return -EINVAL;
 557
 558         if (enable)
 559                 config_sctlr_el1(SCTLR_EL1_SED, 0);
 560         else
 561                 config_sctlr_el1(0, SCTLR_EL1_SED);
 562         return 0;
 563 }
 564
 565 static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
 566 {
 567         char *insn;
 568
 569         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 570
 571         if (big_endian) {
 572                 insn = "setend be";
 573                 regs->pstate |= COMPAT_PSR_E_BIT;
 574         } else {
 575                 insn = "setend le";
 576                 regs->pstate &= ~COMPAT_PSR_E_BIT;
 577         }
 578
 579         trace_instruction_emulation(insn, regs->pc);
 580         pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
 581                         current->comm, (unsigned long)current->pid, regs->pc);
 582
 583         return 0;
 584 }
 585
 586 static int a32_setend_handler(struct pt_regs *regs, u32 instr)
 587 {
 588         int rc = compat_setend_handler(regs, (instr >> 9) & 1);
 589         regs->pc += 4;
 590         return rc;
 591 }
 592
 593 static int t16_setend_handler(struct pt_regs *regs, u32 instr)
 594 {
 595         int rc = compat_setend_handler(regs, (instr >> 3) & 1);
 596         regs->pc += 2;
 597         return rc;
 598 }
 599
 600 static struct undef_hook setend_hooks[] = {
 601         {
 602                 .instr_mask     = 0xfffffdff,
 603                 .instr_val      = 0xf1010000,
 604                 .pstate_mask    = COMPAT_PSR_MODE_MASK,
 605                 .pstate_val     = COMPAT_PSR_MODE_USR,
 606                 .fn             = a32_setend_handler,
 607         },
 608         {
 609                 /* Thumb mode */
 610                 .instr_mask     = 0x0000fff7,
 611                 .instr_val      = 0x0000b650,
 612                 .pstate_mask    = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_MASK),
 613                 .pstate_val     = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_USR),
 614                 .fn             = t16_setend_handler,
 615         },
 616         {}
 617 };
 618
 619 static struct insn_emulation_ops setend_ops = {
 620         .name = "setend",
 621         .status = INSN_DEPRECATED,
 622         .hooks = setend_hooks,
 623         .set_hw_mode = setend_set_hw_mode,
 624 };
 625
 626 /*
 627  * Invoked as late_initcall, since not needed before init spawned.
 628  */
 629 static int __init armv8_deprecated_init(void)
 630 {
 631         if (IS_ENABLED(CONFIG_SWP_EMULATION))
 632                 register_insn_emulation(&swp_ops);
 633
 634         if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
 635                 register_insn_emulation(&cp15_barrier_ops);
 636
 637         if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
 638                 if(system_supports_mixed_endian_el0())
 639                         register_insn_emulation(&setend_ops);
 640                 else
 641                         pr_info("setend instruction emulation is not supported on this system\n");
 642         }
 643
 644         cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
 645                                   "arm64/isndep:starting",
 646                                   run_all_insn_set_hw_mode, NULL);
 647         register_insn_emulation_sysctl(ctl_abi);
 648
 649         return 0;
 650 }
 651
 652 late_initcall(armv8_deprecated_init);