2 * Copyright (C) 2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <asm/memory.h>
22 #include <asm/sysreg.h>
24 #define ESR_ELx_EC_UNKNOWN (0x00)
25 #define ESR_ELx_EC_WFx (0x01)
26 /* Unallocated EC: 0x02 */
27 #define ESR_ELx_EC_CP15_32 (0x03)
28 #define ESR_ELx_EC_CP15_64 (0x04)
29 #define ESR_ELx_EC_CP14_MR (0x05)
30 #define ESR_ELx_EC_CP14_LS (0x06)
31 #define ESR_ELx_EC_FP_ASIMD (0x07)
32 #define ESR_ELx_EC_CP10_ID (0x08)
33 /* Unallocated EC: 0x09 - 0x0B */
34 #define ESR_ELx_EC_CP14_64 (0x0C)
35 /* Unallocated EC: 0x0d */
36 #define ESR_ELx_EC_ILL (0x0E)
37 /* Unallocated EC: 0x0F - 0x10 */
38 #define ESR_ELx_EC_SVC32 (0x11)
39 #define ESR_ELx_EC_HVC32 (0x12)
40 #define ESR_ELx_EC_SMC32 (0x13)
41 /* Unallocated EC: 0x14 */
42 #define ESR_ELx_EC_SVC64 (0x15)
43 #define ESR_ELx_EC_HVC64 (0x16)
44 #define ESR_ELx_EC_SMC64 (0x17)
45 #define ESR_ELx_EC_SYS64 (0x18)
46 #define ESR_ELx_EC_SVE (0x19)
47 /* Unallocated EC: 0x1A - 0x1E */
48 #define ESR_ELx_EC_IMP_DEF (0x1f)
49 #define ESR_ELx_EC_IABT_LOW (0x20)
50 #define ESR_ELx_EC_IABT_CUR (0x21)
51 #define ESR_ELx_EC_PC_ALIGN (0x22)
52 /* Unallocated EC: 0x23 */
53 #define ESR_ELx_EC_DABT_LOW (0x24)
54 #define ESR_ELx_EC_DABT_CUR (0x25)
55 #define ESR_ELx_EC_SP_ALIGN (0x26)
56 /* Unallocated EC: 0x27 */
57 #define ESR_ELx_EC_FP_EXC32 (0x28)
58 /* Unallocated EC: 0x29 - 0x2B */
59 #define ESR_ELx_EC_FP_EXC64 (0x2C)
60 /* Unallocated EC: 0x2D - 0x2E */
61 #define ESR_ELx_EC_SERROR (0x2F)
62 #define ESR_ELx_EC_BREAKPT_LOW (0x30)
63 #define ESR_ELx_EC_BREAKPT_CUR (0x31)
64 #define ESR_ELx_EC_SOFTSTP_LOW (0x32)
65 #define ESR_ELx_EC_SOFTSTP_CUR (0x33)
66 #define ESR_ELx_EC_WATCHPT_LOW (0x34)
67 #define ESR_ELx_EC_WATCHPT_CUR (0x35)
68 /* Unallocated EC: 0x36 - 0x37 */
69 #define ESR_ELx_EC_BKPT32 (0x38)
70 /* Unallocated EC: 0x39 */
71 #define ESR_ELx_EC_VECTOR32 (0x3A)
72 /* Unallocted EC: 0x3B */
73 #define ESR_ELx_EC_BRK64 (0x3C)
74 /* Unallocated EC: 0x3D - 0x3F */
75 #define ESR_ELx_EC_MAX (0x3F)
77 #define ESR_ELx_EC_SHIFT (26)
78 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
79 #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
81 #define ESR_ELx_IL_SHIFT (25)
82 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
83 #define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1)
85 /* ISS field definitions shared by different classes */
86 #define ESR_ELx_WNR_SHIFT (6)
87 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
89 /* Asynchronous Error Type */
90 #define ESR_ELx_IDS_SHIFT (24)
91 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
92 #define ESR_ELx_AET_SHIFT (10)
93 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
95 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
96 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
97 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
98 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
99 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
101 /* Shared ISS field definitions for Data/Instruction aborts */
102 #define ESR_ELx_SET_SHIFT (11)
103 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
104 #define ESR_ELx_FnV_SHIFT (10)
105 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
106 #define ESR_ELx_EA_SHIFT (9)
107 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
108 #define ESR_ELx_S1PTW_SHIFT (7)
109 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
111 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
112 #define ESR_ELx_FSC (0x3F)
113 #define ESR_ELx_FSC_TYPE (0x3C)
114 #define ESR_ELx_FSC_EXTABT (0x10)
115 #define ESR_ELx_FSC_SERROR (0x11)
116 #define ESR_ELx_FSC_ACCESS (0x08)
117 #define ESR_ELx_FSC_FAULT (0x04)
118 #define ESR_ELx_FSC_PERM (0x0C)
120 /* ISS field definitions for Data Aborts */
121 #define ESR_ELx_ISV_SHIFT (24)
122 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
123 #define ESR_ELx_SAS_SHIFT (22)
124 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
125 #define ESR_ELx_SSE_SHIFT (21)
126 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
127 #define ESR_ELx_SRT_SHIFT (16)
128 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
129 #define ESR_ELx_SF_SHIFT (15)
130 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
131 #define ESR_ELx_AR_SHIFT (14)
132 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
133 #define ESR_ELx_CM_SHIFT (8)
134 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
136 /* ISS field definitions for exceptions taken in to Hyp */
137 #define ESR_ELx_CV (UL(1) << 24)
138 #define ESR_ELx_COND_SHIFT (20)
139 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
140 #define ESR_ELx_WFx_ISS_TI (UL(1) << 0)
141 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
142 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
143 #define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1)
145 #define DISR_EL1_IDS (UL(1) << 24)
147 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
148 * different things in the future...
150 #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
152 /* ESR value templates for specific events */
153 #define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI)
154 #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \
157 /* BRK instruction trap from AArch64 state */
158 #define ESR_ELx_VAL_BRK64(imm) \
159 ((ESR_ELx_EC_BRK64 << ESR_ELx_EC_SHIFT) | ESR_ELx_IL | \
162 /* ISS field definitions for System instruction traps */
163 #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22
164 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
165 #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1
166 #define ESR_ELx_SYS64_ISS_DIR_READ 0x1
167 #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0
169 #define ESR_ELx_SYS64_ISS_RT_SHIFT 5
170 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
171 #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
172 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
173 #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10
174 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
175 #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14
176 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
177 #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17
178 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
179 #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20
180 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
181 #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
182 ESR_ELx_SYS64_ISS_OP1_MASK | \
183 ESR_ELx_SYS64_ISS_OP2_MASK | \
184 ESR_ELx_SYS64_ISS_CRN_MASK | \
185 ESR_ELx_SYS64_ISS_CRM_MASK)
186 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
187 (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
188 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
189 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
190 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
191 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
193 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \
194 ESR_ELx_SYS64_ISS_DIR_MASK)
195 #define ESR_ELx_SYS64_ISS_RT(esr) \
196 (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
198 * User space cache operations have the following sysreg encoding
199 * in System instructions.
200 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 14 }, WRITE (L=0)
202 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14
203 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12
204 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11
205 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10
206 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5
208 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
209 ESR_ELx_SYS64_ISS_OP1_MASK | \
210 ESR_ELx_SYS64_ISS_OP2_MASK | \
211 ESR_ELx_SYS64_ISS_CRN_MASK | \
212 ESR_ELx_SYS64_ISS_DIR_MASK)
213 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
214 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
215 ESR_ELx_SYS64_ISS_DIR_WRITE)
217 * User space MRS operations which are supported for emulation
218 * have the following sysreg encoding in System instructions.
219 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
221 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
222 ESR_ELx_SYS64_ISS_OP1_MASK | \
223 ESR_ELx_SYS64_ISS_CRN_MASK | \
224 ESR_ELx_SYS64_ISS_DIR_MASK)
225 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
226 (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
227 ESR_ELx_SYS64_ISS_DIR_READ)
229 #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
230 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \
231 ESR_ELx_SYS64_ISS_DIR_READ)
233 #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
234 ESR_ELx_SYS64_ISS_DIR_READ)
236 #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
237 ESR_ELx_SYS64_ISS_DIR_READ)
239 #define esr_sys64_to_sysreg(e) \
240 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \
241 ESR_ELx_SYS64_ISS_OP0_SHIFT), \
242 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
243 ESR_ELx_SYS64_ISS_OP1_SHIFT), \
244 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
245 ESR_ELx_SYS64_ISS_CRN_SHIFT), \
246 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
247 ESR_ELx_SYS64_ISS_CRM_SHIFT), \
248 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
249 ESR_ELx_SYS64_ISS_OP2_SHIFT))
251 #define esr_cp15_to_sysreg(e) \
253 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
254 ESR_ELx_SYS64_ISS_OP1_SHIFT), \
255 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
256 ESR_ELx_SYS64_ISS_CRN_SHIFT), \
257 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
258 ESR_ELx_SYS64_ISS_CRM_SHIFT), \
259 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
260 ESR_ELx_SYS64_ISS_OP2_SHIFT))
263 * ISS field definitions for floating-point exception traps
264 * (FP_EXC_32/FP_EXC_64).
266 * (The FPEXC_* constants are used instead for common bits.)
269 #define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
272 * ISS field definitions for CP15 accesses
274 #define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1
275 #define ESR_ELx_CP15_32_ISS_DIR_READ 0x1
276 #define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0
278 #define ESR_ELx_CP15_32_ISS_RT_SHIFT 5
279 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
280 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1
281 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
282 #define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10
283 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
284 #define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14
285 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
286 #define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17
287 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
289 #define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \
290 ESR_ELx_CP15_32_ISS_OP2_MASK | \
291 ESR_ELx_CP15_32_ISS_CRN_MASK | \
292 ESR_ELx_CP15_32_ISS_CRM_MASK | \
293 ESR_ELx_CP15_32_ISS_DIR_MASK)
294 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
295 (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
296 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
297 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
298 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
300 #define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1
301 #define ESR_ELx_CP15_64_ISS_DIR_READ 0x1
302 #define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0
304 #define ESR_ELx_CP15_64_ISS_RT_SHIFT 5
305 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
307 #define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10
308 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
310 #define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16
311 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
312 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1
313 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
315 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
316 (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
317 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
319 #define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \
320 ESR_ELx_CP15_64_ISS_CRM_MASK | \
321 ESR_ELx_CP15_64_ISS_DIR_MASK)
323 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
324 ESR_ELx_CP15_64_ISS_DIR_READ)
326 #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
327 ESR_ELx_CP15_32_ISS_DIR_READ)
330 #include <asm/types.h>
332 static inline bool esr_is_data_abort(u32 esr)
334 const u32 ec = ESR_ELx_EC(esr);
336 return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
339 const char *esr_get_class_string(u32 esr);
340 #endif /* __ASSEMBLY */
342 #endif /* __ASM_ESR_H */