arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier PXs3 SoC
   4 //
   5 // Copyright (C) 2017 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/gpio/uniphier-gpio.h>
  10
  11 /memreserve/ 0x80000000 0x02000000;
  12
  13 / {
  14         compatible = "socionext,uniphier-pxs3";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17         interrupt-parent = <&gic>;
  18
  19         cpus {
  20                 #address-cells = <2>;
  21                 #size-cells = <0>;
  22
  23                 cpu-map {
  24                         cluster0 {
  25                                 core0 {
  26                                         cpu = <&cpu0>;
  27                                 };
  28                                 core1 {
  29                                         cpu = <&cpu1>;
  30                                 };
  31                                 core2 {
  32                                         cpu = <&cpu2>;
  33                                 };
  34                                 core3 {
  35                                         cpu = <&cpu3>;
  36                                 };
  37                         };
  38                 };
  39
  40                 cpu0: cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53";
  43                         reg = <0 0x000>;
  44                         clocks = <&sys_clk 33>;
  45                         enable-method = "psci";
  46                         operating-points-v2 = <&cluster0_opp>;
  47                 };
  48
  49                 cpu1: cpu@1 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a53";
  52                         reg = <0 0x001>;
  53                         clocks = <&sys_clk 33>;
  54                         enable-method = "psci";
  55                         operating-points-v2 = <&cluster0_opp>;
  56                 };
  57
  58                 cpu2: cpu@2 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53";
  61                         reg = <0 0x002>;
  62                         clocks = <&sys_clk 33>;
  63                         enable-method = "psci";
  64                         operating-points-v2 = <&cluster0_opp>;
  65                 };
  66
  67                 cpu3: cpu@3 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a53";
  70                         reg = <0 0x003>;
  71                         clocks = <&sys_clk 33>;
  72                         enable-method = "psci";
  73                         operating-points-v2 = <&cluster0_opp>;
  74                 };
  75         };
  76
  77         cluster0_opp: opp-table {
  78                 compatible = "operating-points-v2";
  79                 opp-shared;
  80
  81                 opp-250000000 {
  82                         opp-hz = /bits/ 64 <250000000>;
  83                         clock-latency-ns = <300>;
  84                 };
  85                 opp-325000000 {
  86                         opp-hz = /bits/ 64 <325000000>;
  87                         clock-latency-ns = <300>;
  88                 };
  89                 opp-500000000 {
  90                         opp-hz = /bits/ 64 <500000000>;
  91                         clock-latency-ns = <300>;
  92                 };
  93                 opp-650000000 {
  94                         opp-hz = /bits/ 64 <650000000>;
  95                         clock-latency-ns = <300>;
  96                 };
  97                 opp-666667000 {
  98                         opp-hz = /bits/ 64 <666667000>;
  99                         clock-latency-ns = <300>;
 100                 };
 101                 opp-866667000 {
 102                         opp-hz = /bits/ 64 <866667000>;
 103                         clock-latency-ns = <300>;
 104                 };
 105                 opp-1000000000 {
 106                         opp-hz = /bits/ 64 <1000000000>;
 107                         clock-latency-ns = <300>;
 108                 };
 109                 opp-1300000000 {
 110                         opp-hz = /bits/ 64 <1300000000>;
 111                         clock-latency-ns = <300>;
 112                 };
 113         };
 114
 115         psci {
 116                 compatible = "arm,psci-1.0";
 117                 method = "smc";
 118         };
 119
 120         clocks {
 121                 refclk: ref {
 122                         compatible = "fixed-clock";
 123                         #clock-cells = <0>;
 124                         clock-frequency = <25000000>;
 125                 };
 126         };
 127
 128         emmc_pwrseq: emmc-pwrseq {
 129                 compatible = "mmc-pwrseq-emmc";
 130                 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
 131         };
 132
 133         timer {
 134                 compatible = "arm,armv8-timer";
 135                 interrupts = <1 13 4>,
 136                              <1 14 4>,
 137                              <1 11 4>,
 138                              <1 10 4>;
 139         };
 140
 141         soc@0 {
 142                 compatible = "simple-bus";
 143                 #address-cells = <1>;
 144                 #size-cells = <1>;
 145                 ranges = <0 0 0 0xffffffff>;
 146
 147                 spi0: spi@54006000 {
 148                         compatible = "socionext,uniphier-scssi";
 149                         status = "disabled";
 150                         reg = <0x54006000 0x100>;
 151                         interrupts = <0 39 4>;
 152                         pinctrl-names = "default";
 153                         pinctrl-0 = <&pinctrl_spi0>;
 154                         clocks = <&peri_clk 11>;
 155                         resets = <&peri_rst 11>;
 156                 };
 157
 158                 spi1: spi@54006100 {
 159                         compatible = "socionext,uniphier-scssi";
 160                         status = "disabled";
 161                         reg = <0x54006100 0x100>;
 162                         interrupts = <0 216 4>;
 163                         pinctrl-names = "default";
 164                         pinctrl-0 = <&pinctrl_spi1>;
 165                         clocks = <&peri_clk 11>;
 166                         resets = <&peri_rst 11>;
 167                 };
 168
 169                 serial0: serial@54006800 {
 170                         compatible = "socionext,uniphier-uart";
 171                         status = "disabled";
 172                         reg = <0x54006800 0x40>;
 173                         interrupts = <0 33 4>;
 174                         pinctrl-names = "default";
 175                         pinctrl-0 = <&pinctrl_uart0>;
 176                         clocks = <&peri_clk 0>;
 177                         resets = <&peri_rst 0>;
 178                 };
 179
 180                 serial1: serial@54006900 {
 181                         compatible = "socionext,uniphier-uart";
 182                         status = "disabled";
 183                         reg = <0x54006900 0x40>;
 184                         interrupts = <0 35 4>;
 185                         pinctrl-names = "default";
 186                         pinctrl-0 = <&pinctrl_uart1>;
 187                         clocks = <&peri_clk 1>;
 188                         resets = <&peri_rst 1>;
 189                 };
 190
 191                 serial2: serial@54006a00 {
 192                         compatible = "socionext,uniphier-uart";
 193                         status = "disabled";
 194                         reg = <0x54006a00 0x40>;
 195                         interrupts = <0 37 4>;
 196                         pinctrl-names = "default";
 197                         pinctrl-0 = <&pinctrl_uart2>;
 198                         clocks = <&peri_clk 2>;
 199                         resets = <&peri_rst 2>;
 200                 };
 201
 202                 serial3: serial@54006b00 {
 203                         compatible = "socionext,uniphier-uart";
 204                         status = "disabled";
 205                         reg = <0x54006b00 0x40>;
 206                         interrupts = <0 177 4>;
 207                         pinctrl-names = "default";
 208                         pinctrl-0 = <&pinctrl_uart3>;
 209                         clocks = <&peri_clk 3>;
 210                         resets = <&peri_rst 3>;
 211                 };
 212
 213                 gpio: gpio@55000000 {
 214                         compatible = "socionext,uniphier-gpio";
 215                         reg = <0x55000000 0x200>;
 216                         interrupt-parent = <&aidet>;
 217                         interrupt-controller;
 218                         #interrupt-cells = <2>;
 219                         gpio-controller;
 220                         #gpio-cells = <2>;
 221                         gpio-ranges = <&pinctrl 0 0 0>,
 222                                       <&pinctrl 104 0 0>,
 223                                       <&pinctrl 168 0 0>;
 224                         gpio-ranges-group-names = "gpio_range0",
 225                                                   "gpio_range1",
 226                                                   "gpio_range2";
 227                         ngpios = <286>;
 228                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 229                                                      <21 217 3>;
 230                 };
 231
 232                 i2c0: i2c@58780000 {
 233                         compatible = "socionext,uniphier-fi2c";
 234                         status = "disabled";
 235                         reg = <0x58780000 0x80>;
 236                         #address-cells = <1>;
 237                         #size-cells = <0>;
 238                         interrupts = <0 41 4>;
 239                         pinctrl-names = "default";
 240                         pinctrl-0 = <&pinctrl_i2c0>;
 241                         clocks = <&peri_clk 4>;
 242                         resets = <&peri_rst 4>;
 243                         clock-frequency = <100000>;
 244                 };
 245
 246                 i2c1: i2c@58781000 {
 247                         compatible = "socionext,uniphier-fi2c";
 248                         status = "disabled";
 249                         reg = <0x58781000 0x80>;
 250                         #address-cells = <1>;
 251                         #size-cells = <0>;
 252                         interrupts = <0 42 4>;
 253                         pinctrl-names = "default";
 254                         pinctrl-0 = <&pinctrl_i2c1>;
 255                         clocks = <&peri_clk 5>;
 256                         resets = <&peri_rst 5>;
 257                         clock-frequency = <100000>;
 258                 };
 259
 260                 i2c2: i2c@58782000 {
 261                         compatible = "socionext,uniphier-fi2c";
 262                         status = "disabled";
 263                         reg = <0x58782000 0x80>;
 264                         #address-cells = <1>;
 265                         #size-cells = <0>;
 266                         interrupts = <0 43 4>;
 267                         pinctrl-names = "default";
 268                         pinctrl-0 = <&pinctrl_i2c2>;
 269                         clocks = <&peri_clk 6>;
 270                         resets = <&peri_rst 6>;
 271                         clock-frequency = <100000>;
 272                 };
 273
 274                 i2c3: i2c@58783000 {
 275                         compatible = "socionext,uniphier-fi2c";
 276                         status = "disabled";
 277                         reg = <0x58783000 0x80>;
 278                         #address-cells = <1>;
 279                         #size-cells = <0>;
 280                         interrupts = <0 44 4>;
 281                         pinctrl-names = "default";
 282                         pinctrl-0 = <&pinctrl_i2c3>;
 283                         clocks = <&peri_clk 7>;
 284                         resets = <&peri_rst 7>;
 285                         clock-frequency = <100000>;
 286                 };
 287
 288                 /* chip-internal connection for HDMI */
 289                 i2c6: i2c@58786000 {
 290                         compatible = "socionext,uniphier-fi2c";
 291                         reg = <0x58786000 0x80>;
 292                         #address-cells = <1>;
 293                         #size-cells = <0>;
 294                         interrupts = <0 26 4>;
 295                         clocks = <&peri_clk 10>;
 296                         resets = <&peri_rst 10>;
 297                         clock-frequency = <400000>;
 298                 };
 299
 300                 system_bus: system-bus@58c00000 {
 301                         compatible = "socionext,uniphier-system-bus";
 302                         status = "disabled";
 303                         reg = <0x58c00000 0x400>;
 304                         #address-cells = <2>;
 305                         #size-cells = <1>;
 306                         pinctrl-names = "default";
 307                         pinctrl-0 = <&pinctrl_system_bus>;
 308                 };
 309
 310                 smpctrl@59801000 {
 311                         compatible = "socionext,uniphier-smpctrl";
 312                         reg = <0x59801000 0x400>;
 313                 };
 314
 315                 sdctrl@59810000 {
 316                         compatible = "socionext,uniphier-pxs3-sdctrl",
 317                                      "simple-mfd", "syscon";
 318                         reg = <0x59810000 0x400>;
 319
 320                         sd_clk: clock {
 321                                 compatible = "socionext,uniphier-pxs3-sd-clock";
 322                                 #clock-cells = <1>;
 323                         };
 324
 325                         sd_rst: reset {
 326                                 compatible = "socionext,uniphier-pxs3-sd-reset";
 327                                 #reset-cells = <1>;
 328                         };
 329                 };
 330
 331                 perictrl@59820000 {
 332                         compatible = "socionext,uniphier-pxs3-perictrl",
 333                                      "simple-mfd", "syscon";
 334                         reg = <0x59820000 0x200>;
 335
 336                         peri_clk: clock {
 337                                 compatible = "socionext,uniphier-pxs3-peri-clock";
 338                                 #clock-cells = <1>;
 339                         };
 340
 341                         peri_rst: reset {
 342                                 compatible = "socionext,uniphier-pxs3-peri-reset";
 343                                 #reset-cells = <1>;
 344                         };
 345                 };
 346
 347                 emmc: sdhc@5a000000 {
 348                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 349                         reg = <0x5a000000 0x400>;
 350                         interrupts = <0 78 4>;
 351                         pinctrl-names = "default";
 352                         pinctrl-0 = <&pinctrl_emmc>;
 353                         clocks = <&sys_clk 4>;
 354                         resets = <&sys_rst 4>;
 355                         bus-width = <8>;
 356                         mmc-ddr-1_8v;
 357                         mmc-hs200-1_8v;
 358                         mmc-pwrseq = <&emmc_pwrseq>;
 359                         cdns,phy-input-delay-legacy = <9>;
 360                         cdns,phy-input-delay-mmc-highspeed = <2>;
 361                         cdns,phy-input-delay-mmc-ddr = <3>;
 362                         cdns,phy-dll-delay-sdclk = <21>;
 363                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 364                 };
 365
 366                 sd: sdhc@5a400000 {
 367                         compatible = "socionext,uniphier-sd-v3.1.1";
 368                         status = "disabled";
 369                         reg = <0x5a400000 0x800>;
 370                         interrupts = <0 76 4>;
 371                         pinctrl-names = "default", "uhs";
 372                         pinctrl-0 = <&pinctrl_sd>;
 373                         pinctrl-1 = <&pinctrl_sd_uhs>;
 374                         clocks = <&sd_clk 0>;
 375                         reset-names = "host";
 376                         resets = <&sd_rst 0>;
 377                         bus-width = <4>;
 378                         cap-sd-highspeed;
 379                         sd-uhs-sdr12;
 380                         sd-uhs-sdr25;
 381                         sd-uhs-sdr50;
 382                 };
 383
 384                 soc_glue: soc-glue@5f800000 {
 385                         compatible = "socionext,uniphier-pxs3-soc-glue",
 386                                      "simple-mfd", "syscon";
 387                         reg = <0x5f800000 0x2000>;
 388
 389                         pinctrl: pinctrl {
 390                                 compatible = "socionext,uniphier-pxs3-pinctrl";
 391                         };
 392                 };
 393
 394                 soc-glue@5f900000 {
 395                         compatible = "socionext,uniphier-pxs3-soc-glue-debug",
 396                                      "simple-mfd";
 397                         #address-cells = <1>;
 398                         #size-cells = <1>;
 399                         ranges = <0 0x5f900000 0x2000>;
 400
 401                         efuse@100 {
 402                                 compatible = "socionext,uniphier-efuse";
 403                                 reg = <0x100 0x28>;
 404                         };
 405
 406                         efuse@200 {
 407                                 compatible = "socionext,uniphier-efuse";
 408                                 reg = <0x200 0x68>;
 409                                 #address-cells = <1>;
 410                                 #size-cells = <1>;
 411
 412                                 /* USB cells */
 413                                 usb_rterm0: trim@54,4 {
 414                                         reg = <0x54 1>;
 415                                         bits = <4 2>;
 416                                 };
 417                                 usb_rterm1: trim@55,4 {
 418                                         reg = <0x55 1>;
 419                                         bits = <4 2>;
 420                                 };
 421                                 usb_rterm2: trim@58,4 {
 422                                         reg = <0x58 1>;
 423                                         bits = <4 2>;
 424                                 };
 425                                 usb_rterm3: trim@59,4 {
 426                                         reg = <0x59 1>;
 427                                         bits = <4 2>;
 428                                 };
 429                                 usb_sel_t0: trim@54,0 {
 430                                         reg = <0x54 1>;
 431                                         bits = <0 4>;
 432                                 };
 433                                 usb_sel_t1: trim@55,0 {
 434                                         reg = <0x55 1>;
 435                                         bits = <0 4>;
 436                                 };
 437                                 usb_sel_t2: trim@58,0 {
 438                                         reg = <0x58 1>;
 439                                         bits = <0 4>;
 440                                 };
 441                                 usb_sel_t3: trim@59,0 {
 442                                         reg = <0x59 1>;
 443                                         bits = <0 4>;
 444                                 };
 445                                 usb_hs_i0: trim@56,0 {
 446                                         reg = <0x56 1>;
 447                                         bits = <0 4>;
 448                                 };
 449                                 usb_hs_i2: trim@5a,0 {
 450                                         reg = <0x5a 1>;
 451                                         bits = <0 4>;
 452                                 };
 453                         };
 454                 };
 455
 456                 aidet: aidet@5fc20000 {
 457                         compatible = "socionext,uniphier-pxs3-aidet";
 458                         reg = <0x5fc20000 0x200>;
 459                         interrupt-controller;
 460                         #interrupt-cells = <2>;
 461                 };
 462
 463                 gic: interrupt-controller@5fe00000 {
 464                         compatible = "arm,gic-v3";
 465                         reg = <0x5fe00000 0x10000>,     /* GICD */
 466                               <0x5fe80000 0x80000>;     /* GICR */
 467                         interrupt-controller;
 468                         #interrupt-cells = <3>;
 469                         interrupts = <1 9 4>;
 470                 };
 471
 472                 sysctrl@61840000 {
 473                         compatible = "socionext,uniphier-pxs3-sysctrl",
 474                                      "simple-mfd", "syscon";
 475                         reg = <0x61840000 0x10000>;
 476
 477                         sys_clk: clock {
 478                                 compatible = "socionext,uniphier-pxs3-clock";
 479                                 #clock-cells = <1>;
 480                         };
 481
 482                         sys_rst: reset {
 483                                 compatible = "socionext,uniphier-pxs3-reset";
 484                                 #reset-cells = <1>;
 485                         };
 486
 487                         watchdog {
 488                                 compatible = "socionext,uniphier-wdt";
 489                         };
 490                 };
 491
 492                 eth0: ethernet@65000000 {
 493                         compatible = "socionext,uniphier-pxs3-ave4";
 494                         status = "disabled";
 495                         reg = <0x65000000 0x8500>;
 496                         interrupts = <0 66 4>;
 497                         pinctrl-names = "default";
 498                         pinctrl-0 = <&pinctrl_ether_rgmii>;
 499                         clock-names = "ether";
 500                         clocks = <&sys_clk 6>;
 501                         reset-names = "ether";
 502                         resets = <&sys_rst 6>;
 503                         phy-mode = "rgmii";
 504                         local-mac-address = [00 00 00 00 00 00];
 505                         socionext,syscon-phy-mode = <&soc_glue 0>;
 506
 507                         mdio0: mdio {
 508                                 #address-cells = <1>;
 509                                 #size-cells = <0>;
 510                         };
 511                 };
 512
 513                 eth1: ethernet@65200000 {
 514                         compatible = "socionext,uniphier-pxs3-ave4";
 515                         status = "disabled";
 516                         reg = <0x65200000 0x8500>;
 517                         interrupts = <0 67 4>;
 518                         pinctrl-names = "default";
 519                         pinctrl-0 = <&pinctrl_ether1_rgmii>;
 520                         clock-names = "ether";
 521                         clocks = <&sys_clk 7>;
 522                         reset-names = "ether";
 523                         resets = <&sys_rst 7>;
 524                         phy-mode = "rgmii";
 525                         local-mac-address = [00 00 00 00 00 00];
 526                         socionext,syscon-phy-mode = <&soc_glue 1>;
 527
 528                         mdio1: mdio {
 529                                 #address-cells = <1>;
 530                                 #size-cells = <0>;
 531                         };
 532                 };
 533
 534                 usb0: usb@65a00000 {
 535                         compatible = "socionext,uniphier-dwc3", "snps,dwc3";
 536                         status = "disabled";
 537                         reg = <0x65a00000 0xcd00>;
 538                         interrupt-names = "host", "peripheral";
 539                         interrupts = <0 134 4>, <0 135 4>;
 540                         pinctrl-names = "default";
 541                         pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
 542                         clock-names = "ref", "bus_early", "suspend";
 543                         clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
 544                         resets = <&usb0_rst 15>;
 545                         phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
 546                                <&usb0_ssphy0>, <&usb0_ssphy1>;
 547                         dr_mode = "host";
 548                 };
 549
 550                 usb-glue@65b00000 {
 551                         compatible = "socionext,uniphier-pxs3-dwc3-glue",
 552                                      "simple-mfd";
 553                         #address-cells = <1>;
 554                         #size-cells = <1>;
 555                         ranges = <0 0x65b00000 0x400>;
 556
 557                         usb0_rst: reset@0 {
 558                                 compatible = "socionext,uniphier-pxs3-usb3-reset";
 559                                 reg = <0x0 0x4>;
 560                                 #reset-cells = <1>;
 561                                 clock-names = "link";
 562                                 clocks = <&sys_clk 12>;
 563                                 reset-names = "link";
 564                                 resets = <&sys_rst 12>;
 565                         };
 566
 567                         usb0_vbus0: regulator@100 {
 568                                 compatible = "socionext,uniphier-pxs3-usb3-regulator";
 569                                 reg = <0x100 0x10>;
 570                                 clock-names = "link";
 571                                 clocks = <&sys_clk 12>;
 572                                 reset-names = "link";
 573                                 resets = <&sys_rst 12>;
 574                         };
 575
 576                         usb0_vbus1: regulator@110 {
 577                                 compatible = "socionext,uniphier-pxs3-usb3-regulator";
 578                                 reg = <0x110 0x10>;
 579                                 clock-names = "link";
 580                                 clocks = <&sys_clk 12>;
 581                                 reset-names = "link";
 582                                 resets = <&sys_rst 12>;
 583                         };
 584
 585                         usb0_hsphy0: hs-phy@200 {
 586                                 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
 587                                 reg = <0x200 0x10>;
 588                                 #phy-cells = <0>;
 589                                 clock-names = "link", "phy";
 590                                 clocks = <&sys_clk 12>, <&sys_clk 16>;
 591                                 reset-names = "link", "phy";
 592                                 resets = <&sys_rst 12>, <&sys_rst 16>;
 593                                 vbus-supply = <&usb0_vbus0>;
 594                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 595                                 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
 596                                               <&usb_hs_i0>;
 597                         };
 598
 599                         usb0_hsphy1: hs-phy@210 {
 600                                 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
 601                                 reg = <0x210 0x10>;
 602                                 #phy-cells = <0>;
 603                                 clock-names = "link", "phy";
 604                                 clocks = <&sys_clk 12>, <&sys_clk 16>;
 605                                 reset-names = "link", "phy";
 606                                 resets = <&sys_rst 12>, <&sys_rst 16>;
 607                                 vbus-supply = <&usb0_vbus1>;
 608                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 609                                 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
 610                                               <&usb_hs_i0>;
 611                         };
 612
 613                         usb0_ssphy0: ss-phy@300 {
 614                                 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
 615                                 reg = <0x300 0x10>;
 616                                 #phy-cells = <0>;
 617                                 clock-names = "link", "phy";
 618                                 clocks = <&sys_clk 12>, <&sys_clk 17>;
 619                                 reset-names = "link", "phy";
 620                                 resets = <&sys_rst 12>, <&sys_rst 17>;
 621                                 vbus-supply = <&usb0_vbus0>;
 622                         };
 623
 624                         usb0_ssphy1: ss-phy@310 {
 625                                 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
 626                                 reg = <0x310 0x10>;
 627                                 #phy-cells = <0>;
 628                                 clock-names = "link", "phy";
 629                                 clocks = <&sys_clk 12>, <&sys_clk 18>;
 630                                 reset-names = "link", "phy";
 631                                 resets = <&sys_rst 12>, <&sys_rst 18>;
 632                                 vbus-supply = <&usb0_vbus1>;
 633                         };
 634                 };
 635
 636                 usb1: usb@65c00000 {
 637                         compatible = "socionext,uniphier-dwc3", "snps,dwc3";
 638                         status = "disabled";
 639                         reg = <0x65c00000 0xcd00>;
 640                         interrupt-names = "host", "peripheral";
 641                         interrupts = <0 137 4>, <0 138 4>;
 642                         pinctrl-names = "default";
 643                         pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
 644                         clock-names = "ref", "bus_early", "suspend";
 645                         clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
 646                         resets = <&usb1_rst 15>;
 647                         phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
 648                                <&usb1_ssphy0>;
 649                         dr_mode = "host";
 650                 };
 651
 652                 usb-glue@65d00000 {
 653                         compatible = "socionext,uniphier-pxs3-dwc3-glue",
 654                                      "simple-mfd";
 655                         #address-cells = <1>;
 656                         #size-cells = <1>;
 657                         ranges = <0 0x65d00000 0x400>;
 658
 659                         usb1_rst: reset@0 {
 660                                 compatible = "socionext,uniphier-pxs3-usb3-reset";
 661                                 reg = <0x0 0x4>;
 662                                 #reset-cells = <1>;
 663                                 clock-names = "link";
 664                                 clocks = <&sys_clk 13>;
 665                                 reset-names = "link";
 666                                 resets = <&sys_rst 13>;
 667                         };
 668
 669                         usb1_vbus0: regulator@100 {
 670                                 compatible = "socionext,uniphier-pxs3-usb3-regulator";
 671                                 reg = <0x100 0x10>;
 672                                 clock-names = "link";
 673                                 clocks = <&sys_clk 13>;
 674                                 reset-names = "link";
 675                                 resets = <&sys_rst 13>;
 676                         };
 677
 678                         usb1_vbus1: regulator@110 {
 679                                 compatible = "socionext,uniphier-pxs3-usb3-regulator";
 680                                 reg = <0x110 0x10>;
 681                                 clock-names = "link";
 682                                 clocks = <&sys_clk 13>;
 683                                 reset-names = "link";
 684                                 resets = <&sys_rst 13>;
 685                         };
 686
 687                         usb1_hsphy0: hs-phy@200 {
 688                                 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
 689                                 reg = <0x200 0x10>;
 690                                 #phy-cells = <0>;
 691                                 clock-names = "link", "phy", "phy-ext";
 692                                 clocks = <&sys_clk 13>, <&sys_clk 20>,
 693                                          <&sys_clk 14>;
 694                                 reset-names = "link", "phy";
 695                                 resets = <&sys_rst 13>, <&sys_rst 20>;
 696                                 vbus-supply = <&usb1_vbus0>;
 697                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 698                                 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
 699                                               <&usb_hs_i2>;
 700                         };
 701
 702                         usb1_hsphy1: hs-phy@210 {
 703                                 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
 704                                 reg = <0x210 0x10>;
 705                                 #phy-cells = <0>;
 706                                 clock-names = "link", "phy", "phy-ext";
 707                                 clocks = <&sys_clk 13>, <&sys_clk 20>,
 708                                          <&sys_clk 14>;
 709                                 reset-names = "link", "phy";
 710                                 resets = <&sys_rst 13>, <&sys_rst 20>;
 711                                 vbus-supply = <&usb1_vbus1>;
 712                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 713                                 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
 714                                               <&usb_hs_i2>;
 715                         };
 716
 717                         usb1_ssphy0: ss-phy@300 {
 718                                 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
 719                                 reg = <0x300 0x10>;
 720                                 #phy-cells = <0>;
 721                                 clock-names = "link", "phy", "phy-ext";
 722                                 clocks = <&sys_clk 13>, <&sys_clk 21>,
 723                                          <&sys_clk 14>;
 724                                 reset-names = "link", "phy";
 725                                 resets = <&sys_rst 13>, <&sys_rst 21>;
 726                                 vbus-supply = <&usb1_vbus0>;
 727                         };
 728                 };
 729
 730                 pcie: pcie@66000000 {
 731                         compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
 732                         status = "disabled";
 733                         reg-names = "dbi", "link", "config";
 734                         reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
 735                               <0x2fff0000 0x10000>;
 736                         #address-cells = <3>;
 737                         #size-cells = <2>;
 738                         clocks = <&sys_clk 24>;
 739                         resets = <&sys_rst 24>;
 740                         num-lanes = <1>;
 741                         num-viewport = <1>;
 742                         bus-range = <0x0 0xff>;
 743                         device_type = "pci";
 744                         ranges =
 745                         /* downstream I/O */
 746                                 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
 747                         /* non-prefetchable memory */
 748                                 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
 749                         #interrupt-cells = <1>;
 750                         interrupt-names = "dma", "msi";
 751                         interrupts = <0 224 4>, <0 225 4>;
 752                         interrupt-map-mask = <0 0 0 7>;
 753                         interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
 754                                         <0 0 0 2 &pcie_intc 1>, /* INTB */
 755                                         <0 0 0 3 &pcie_intc 2>, /* INTC */
 756                                         <0 0 0 4 &pcie_intc 3>; /* INTD */
 757                         phy-names = "pcie-phy";
 758                         phys = <&pcie_phy>;
 759
 760                         pcie_intc: legacy-interrupt-controller {
 761                                 interrupt-controller;
 762                                 #interrupt-cells = <1>;
 763                                 interrupt-parent = <&gic>;
 764                                 interrupts = <0 226 4>;
 765                         };
 766                 };
 767
 768                 pcie_phy: phy@66038000 {
 769                         compatible = "socionext,uniphier-pxs3-pcie-phy";
 770                         reg = <0x66038000 0x4000>;
 771                         #phy-cells = <0>;
 772                         clocks = <&sys_clk 24>;
 773                         resets = <&sys_rst 24>;
 774                         socionext,syscon = <&soc_glue>;
 775                 };
 776
 777                 nand: nand@68000000 {
 778                         compatible = "socionext,uniphier-denali-nand-v5b";
 779                         status = "disabled";
 780                         reg-names = "nand_data", "denali_reg";
 781                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 782                         interrupts = <0 65 4>;
 783                         pinctrl-names = "default";
 784                         pinctrl-0 = <&pinctrl_nand>;
 785                         clock-names = "nand", "nand_x", "ecc";
 786                         clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 787                         resets = <&sys_rst 2>;
 788                 };
 789         };
 790 };
 791
 792 #include "uniphier-pinctrl.dtsi"