arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier LD20 SoC
   4 //
   5 // Copyright (C) 2015-2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/gpio/uniphier-gpio.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 /memreserve/ 0x80000000 0x02000000;
  13
  14 / {
  15         compatible = "socionext,uniphier-ld20";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18         interrupt-parent = <&gic>;
  19
  20         cpus {
  21                 #address-cells = <2>;
  22                 #size-cells = <0>;
  23
  24                 cpu-map {
  25                         cluster0 {
  26                                 core0 {
  27                                         cpu = <&cpu0>;
  28                                 };
  29                                 core1 {
  30                                         cpu = <&cpu1>;
  31                                 };
  32                         };
  33
  34                         cluster1 {
  35                                 core0 {
  36                                         cpu = <&cpu2>;
  37                                 };
  38                                 core1 {
  39                                         cpu = <&cpu3>;
  40                                 };
  41                         };
  42                 };
  43
  44                 cpu0: cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a72";
  47                         reg = <0 0x000>;
  48                         clocks = <&sys_clk 32>;
  49                         enable-method = "psci";
  50                         operating-points-v2 = <&cluster0_opp>;
  51                         #cooling-cells = <2>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a72";
  57                         reg = <0 0x001>;
  58                         clocks = <&sys_clk 32>;
  59                         enable-method = "psci";
  60                         operating-points-v2 = <&cluster0_opp>;
  61                         #cooling-cells = <2>;
  62                 };
  63
  64                 cpu2: cpu@100 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a53";
  67                         reg = <0 0x100>;
  68                         clocks = <&sys_clk 33>;
  69                         enable-method = "psci";
  70                         operating-points-v2 = <&cluster1_opp>;
  71                         #cooling-cells = <2>;
  72                 };
  73
  74                 cpu3: cpu@101 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53";
  77                         reg = <0 0x101>;
  78                         clocks = <&sys_clk 33>;
  79                         enable-method = "psci";
  80                         operating-points-v2 = <&cluster1_opp>;
  81                         #cooling-cells = <2>;
  82                 };
  83         };
  84
  85         cluster0_opp: opp-table0 {
  86                 compatible = "operating-points-v2";
  87                 opp-shared;
  88
  89                 opp-250000000 {
  90                         opp-hz = /bits/ 64 <250000000>;
  91                         clock-latency-ns = <300>;
  92                 };
  93                 opp-275000000 {
  94                         opp-hz = /bits/ 64 <275000000>;
  95                         clock-latency-ns = <300>;
  96                 };
  97                 opp-500000000 {
  98                         opp-hz = /bits/ 64 <500000000>;
  99                         clock-latency-ns = <300>;
 100                 };
 101                 opp-550000000 {
 102                         opp-hz = /bits/ 64 <550000000>;
 103                         clock-latency-ns = <300>;
 104                 };
 105                 opp-666667000 {
 106                         opp-hz = /bits/ 64 <666667000>;
 107                         clock-latency-ns = <300>;
 108                 };
 109                 opp-733334000 {
 110                         opp-hz = /bits/ 64 <733334000>;
 111                         clock-latency-ns = <300>;
 112                 };
 113                 opp-1000000000 {
 114                         opp-hz = /bits/ 64 <1000000000>;
 115                         clock-latency-ns = <300>;
 116                 };
 117                 opp-1100000000 {
 118                         opp-hz = /bits/ 64 <1100000000>;
 119                         clock-latency-ns = <300>;
 120                 };
 121         };
 122
 123         cluster1_opp: opp-table1 {
 124                 compatible = "operating-points-v2";
 125                 opp-shared;
 126
 127                 opp-250000000 {
 128                         opp-hz = /bits/ 64 <250000000>;
 129                         clock-latency-ns = <300>;
 130                 };
 131                 opp-275000000 {
 132                         opp-hz = /bits/ 64 <275000000>;
 133                         clock-latency-ns = <300>;
 134                 };
 135                 opp-500000000 {
 136                         opp-hz = /bits/ 64 <500000000>;
 137                         clock-latency-ns = <300>;
 138                 };
 139                 opp-550000000 {
 140                         opp-hz = /bits/ 64 <550000000>;
 141                         clock-latency-ns = <300>;
 142                 };
 143                 opp-666667000 {
 144                         opp-hz = /bits/ 64 <666667000>;
 145                         clock-latency-ns = <300>;
 146                 };
 147                 opp-733334000 {
 148                         opp-hz = /bits/ 64 <733334000>;
 149                         clock-latency-ns = <300>;
 150                 };
 151                 opp-1000000000 {
 152                         opp-hz = /bits/ 64 <1000000000>;
 153                         clock-latency-ns = <300>;
 154                 };
 155                 opp-1100000000 {
 156                         opp-hz = /bits/ 64 <1100000000>;
 157                         clock-latency-ns = <300>;
 158                 };
 159         };
 160
 161         psci {
 162                 compatible = "arm,psci-1.0";
 163                 method = "smc";
 164         };
 165
 166         clocks {
 167                 refclk: ref {
 168                         compatible = "fixed-clock";
 169                         #clock-cells = <0>;
 170                         clock-frequency = <25000000>;
 171                 };
 172         };
 173
 174         emmc_pwrseq: emmc-pwrseq {
 175                 compatible = "mmc-pwrseq-emmc";
 176                 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
 177         };
 178
 179         timer {
 180                 compatible = "arm,armv8-timer";
 181                 interrupts = <1 13 4>,
 182                              <1 14 4>,
 183                              <1 11 4>,
 184                              <1 10 4>;
 185         };
 186
 187         thermal-zones {
 188                 cpu-thermal {
 189                         polling-delay-passive = <250>;  /* 250ms */
 190                         polling-delay = <1000>;         /* 1000ms */
 191                         thermal-sensors = <&pvtctl>;
 192
 193                         trips {
 194                                 cpu_crit: cpu-crit {
 195                                         temperature = <110000>; /* 110C */
 196                                         hysteresis = <2000>;
 197                                         type = "critical";
 198                                 };
 199                                 cpu_alert: cpu-alert {
 200                                         temperature = <100000>; /* 100C */
 201                                         hysteresis = <2000>;
 202                                         type = "passive";
 203                                 };
 204                         };
 205
 206                         cooling-maps {
 207                                 map0 {
 208                                         trip = <&cpu_alert>;
 209                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 210                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 211                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 212                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 213                                 };
 214                         };
 215                 };
 216         };
 217
 218         soc@0 {
 219                 compatible = "simple-bus";
 220                 #address-cells = <1>;
 221                 #size-cells = <1>;
 222                 ranges = <0 0 0 0xffffffff>;
 223
 224                 spi0: spi@54006000 {
 225                         compatible = "socionext,uniphier-scssi";
 226                         status = "disabled";
 227                         reg = <0x54006000 0x100>;
 228                         interrupts = <0 39 4>;
 229                         pinctrl-names = "default";
 230                         pinctrl-0 = <&pinctrl_spi0>;
 231                         clocks = <&peri_clk 11>;
 232                         resets = <&peri_rst 11>;
 233                 };
 234
 235                 spi1: spi@54006100 {
 236                         compatible = "socionext,uniphier-scssi";
 237                         status = "disabled";
 238                         reg = <0x54006100 0x100>;
 239                         interrupts = <0 216 4>;
 240                         pinctrl-names = "default";
 241                         pinctrl-0 = <&pinctrl_spi1>;
 242                         clocks = <&peri_clk 11>;
 243                         resets = <&peri_rst 11>;
 244                 };
 245
 246                 spi2: spi@54006200 {
 247                         compatible = "socionext,uniphier-scssi";
 248                         status = "disabled";
 249                         reg = <0x54006200 0x100>;
 250                         interrupts = <0 229 4>;
 251                         pinctrl-names = "default";
 252                         pinctrl-0 = <&pinctrl_spi2>;
 253                         clocks = <&peri_clk 11>;
 254                         resets = <&peri_rst 11>;
 255                 };
 256
 257                 spi3: spi@54006300 {
 258                         compatible = "socionext,uniphier-scssi";
 259                         status = "disabled";
 260                         reg = <0x54006300 0x100>;
 261                         interrupts = <0 230 4>;
 262                         pinctrl-names = "default";
 263                         pinctrl-0 = <&pinctrl_spi3>;
 264                         clocks = <&peri_clk 11>;
 265                         resets = <&peri_rst 11>;
 266                 };
 267
 268                 serial0: serial@54006800 {
 269                         compatible = "socionext,uniphier-uart";
 270                         status = "disabled";
 271                         reg = <0x54006800 0x40>;
 272                         interrupts = <0 33 4>;
 273                         pinctrl-names = "default";
 274                         pinctrl-0 = <&pinctrl_uart0>;
 275                         clocks = <&peri_clk 0>;
 276                         resets = <&peri_rst 0>;
 277                 };
 278
 279                 serial1: serial@54006900 {
 280                         compatible = "socionext,uniphier-uart";
 281                         status = "disabled";
 282                         reg = <0x54006900 0x40>;
 283                         interrupts = <0 35 4>;
 284                         pinctrl-names = "default";
 285                         pinctrl-0 = <&pinctrl_uart1>;
 286                         clocks = <&peri_clk 1>;
 287                         resets = <&peri_rst 1>;
 288                 };
 289
 290                 serial2: serial@54006a00 {
 291                         compatible = "socionext,uniphier-uart";
 292                         status = "disabled";
 293                         reg = <0x54006a00 0x40>;
 294                         interrupts = <0 37 4>;
 295                         pinctrl-names = "default";
 296                         pinctrl-0 = <&pinctrl_uart2>;
 297                         clocks = <&peri_clk 2>;
 298                         resets = <&peri_rst 2>;
 299                 };
 300
 301                 serial3: serial@54006b00 {
 302                         compatible = "socionext,uniphier-uart";
 303                         status = "disabled";
 304                         reg = <0x54006b00 0x40>;
 305                         interrupts = <0 177 4>;
 306                         pinctrl-names = "default";
 307                         pinctrl-0 = <&pinctrl_uart3>;
 308                         clocks = <&peri_clk 3>;
 309                         resets = <&peri_rst 3>;
 310                 };
 311
 312                 gpio: gpio@55000000 {
 313                         compatible = "socionext,uniphier-gpio";
 314                         reg = <0x55000000 0x200>;
 315                         interrupt-parent = <&aidet>;
 316                         interrupt-controller;
 317                         #interrupt-cells = <2>;
 318                         gpio-controller;
 319                         #gpio-cells = <2>;
 320                         gpio-ranges = <&pinctrl 0 0 0>,
 321                                       <&pinctrl 96 0 0>,
 322                                       <&pinctrl 160 0 0>;
 323                         gpio-ranges-group-names = "gpio_range0",
 324                                                   "gpio_range1",
 325                                                   "gpio_range2";
 326                         ngpios = <205>;
 327                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 328                                                      <21 217 3>;
 329                 };
 330
 331                 audio@56000000 {
 332                         compatible = "socionext,uniphier-ld20-aio";
 333                         reg = <0x56000000 0x80000>;
 334                         interrupts = <0 144 4>;
 335                         pinctrl-names = "default";
 336                         pinctrl-0 = <&pinctrl_aout1>,
 337                                     <&pinctrl_aoutiec1>;
 338                         clock-names = "aio";
 339                         clocks = <&sys_clk 40>;
 340                         reset-names = "aio";
 341                         resets = <&sys_rst 40>;
 342                         #sound-dai-cells = <1>;
 343                         socionext,syscon = <&soc_glue>;
 344
 345                         i2s_port0: port@0 {
 346                                 i2s_hdmi: endpoint {
 347                                 };
 348                         };
 349
 350                         i2s_port1: port@1 {
 351                                 i2s_pcmin2: endpoint {
 352                                 };
 353                         };
 354
 355                         i2s_port2: port@2 {
 356                                 i2s_line: endpoint {
 357                                         dai-format = "i2s";
 358                                         remote-endpoint = <&evea_line>;
 359                                 };
 360                         };
 361
 362                         i2s_port3: port@3 {
 363                                 i2s_hpcmout1: endpoint {
 364                                 };
 365                         };
 366
 367                         i2s_port4: port@4 {
 368                                 i2s_hp: endpoint {
 369                                         dai-format = "i2s";
 370                                         remote-endpoint = <&evea_hp>;
 371                                 };
 372                         };
 373
 374                         spdif_port0: port@5 {
 375                                 spdif_hiecout1: endpoint {
 376                                 };
 377                         };
 378
 379                         src_port0: port@6 {
 380                                 i2s_epcmout2: endpoint {
 381                                 };
 382                         };
 383
 384                         src_port1: port@7 {
 385                                 i2s_epcmout3: endpoint {
 386                                 };
 387                         };
 388
 389                         comp_spdif_port0: port@8 {
 390                                 comp_spdif_hiecout1: endpoint {
 391                                 };
 392                         };
 393                 };
 394
 395                 codec@57900000 {
 396                         compatible = "socionext,uniphier-evea";
 397                         reg = <0x57900000 0x1000>;
 398                         clock-names = "evea", "exiv";
 399                         clocks = <&sys_clk 41>, <&sys_clk 42>;
 400                         reset-names = "evea", "exiv", "adamv";
 401                         resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
 402                         #sound-dai-cells = <1>;
 403
 404                         port@0 {
 405                                 evea_line: endpoint {
 406                                         remote-endpoint = <&i2s_line>;
 407                                 };
 408                         };
 409
 410                         port@1 {
 411                                 evea_hp: endpoint {
 412                                         remote-endpoint = <&i2s_hp>;
 413                                 };
 414                         };
 415                 };
 416
 417                 adamv@57920000 {
 418                         compatible = "socionext,uniphier-ld20-adamv",
 419                                      "simple-mfd", "syscon";
 420                         reg = <0x57920000 0x1000>;
 421
 422                         adamv_rst: reset {
 423                                 compatible = "socionext,uniphier-ld20-adamv-reset";
 424                                 #reset-cells = <1>;
 425                         };
 426                 };
 427
 428                 i2c0: i2c@58780000 {
 429                         compatible = "socionext,uniphier-fi2c";
 430                         status = "disabled";
 431                         reg = <0x58780000 0x80>;
 432                         #address-cells = <1>;
 433                         #size-cells = <0>;
 434                         interrupts = <0 41 4>;
 435                         pinctrl-names = "default";
 436                         pinctrl-0 = <&pinctrl_i2c0>;
 437                         clocks = <&peri_clk 4>;
 438                         resets = <&peri_rst 4>;
 439                         clock-frequency = <100000>;
 440                 };
 441
 442                 i2c1: i2c@58781000 {
 443                         compatible = "socionext,uniphier-fi2c";
 444                         status = "disabled";
 445                         reg = <0x58781000 0x80>;
 446                         #address-cells = <1>;
 447                         #size-cells = <0>;
 448                         interrupts = <0 42 4>;
 449                         pinctrl-names = "default";
 450                         pinctrl-0 = <&pinctrl_i2c1>;
 451                         clocks = <&peri_clk 5>;
 452                         resets = <&peri_rst 5>;
 453                         clock-frequency = <100000>;
 454                 };
 455
 456                 i2c2: i2c@58782000 {
 457                         compatible = "socionext,uniphier-fi2c";
 458                         reg = <0x58782000 0x80>;
 459                         #address-cells = <1>;
 460                         #size-cells = <0>;
 461                         interrupts = <0 43 4>;
 462                         clocks = <&peri_clk 6>;
 463                         resets = <&peri_rst 6>;
 464                         clock-frequency = <400000>;
 465                 };
 466
 467                 i2c3: i2c@58783000 {
 468                         compatible = "socionext,uniphier-fi2c";
 469                         status = "disabled";
 470                         reg = <0x58783000 0x80>;
 471                         #address-cells = <1>;
 472                         #size-cells = <0>;
 473                         interrupts = <0 44 4>;
 474                         pinctrl-names = "default";
 475                         pinctrl-0 = <&pinctrl_i2c3>;
 476                         clocks = <&peri_clk 7>;
 477                         resets = <&peri_rst 7>;
 478                         clock-frequency = <100000>;
 479                 };
 480
 481                 i2c4: i2c@58784000 {
 482                         compatible = "socionext,uniphier-fi2c";
 483                         status = "disabled";
 484                         reg = <0x58784000 0x80>;
 485                         #address-cells = <1>;
 486                         #size-cells = <0>;
 487                         interrupts = <0 45 4>;
 488                         pinctrl-names = "default";
 489                         pinctrl-0 = <&pinctrl_i2c4>;
 490                         clocks = <&peri_clk 8>;
 491                         resets = <&peri_rst 8>;
 492                         clock-frequency = <100000>;
 493                 };
 494
 495                 i2c5: i2c@58785000 {
 496                         compatible = "socionext,uniphier-fi2c";
 497                         reg = <0x58785000 0x80>;
 498                         #address-cells = <1>;
 499                         #size-cells = <0>;
 500                         interrupts = <0 25 4>;
 501                         clocks = <&peri_clk 9>;
 502                         resets = <&peri_rst 9>;
 503                         clock-frequency = <400000>;
 504                 };
 505
 506                 system_bus: system-bus@58c00000 {
 507                         compatible = "socionext,uniphier-system-bus";
 508                         status = "disabled";
 509                         reg = <0x58c00000 0x400>;
 510                         #address-cells = <2>;
 511                         #size-cells = <1>;
 512                         pinctrl-names = "default";
 513                         pinctrl-0 = <&pinctrl_system_bus>;
 514                 };
 515
 516                 smpctrl@59801000 {
 517                         compatible = "socionext,uniphier-smpctrl";
 518                         reg = <0x59801000 0x400>;
 519                 };
 520
 521                 sdctrl@59810000 {
 522                         compatible = "socionext,uniphier-ld20-sdctrl",
 523                                      "simple-mfd", "syscon";
 524                         reg = <0x59810000 0x400>;
 525
 526                         sd_clk: clock {
 527                                 compatible = "socionext,uniphier-ld20-sd-clock";
 528                                 #clock-cells = <1>;
 529                         };
 530
 531                         sd_rst: reset {
 532                                 compatible = "socionext,uniphier-ld20-sd-reset";
 533                                 #reset-cells = <1>;
 534                         };
 535                 };
 536
 537                 perictrl@59820000 {
 538                         compatible = "socionext,uniphier-ld20-perictrl",
 539                                      "simple-mfd", "syscon";
 540                         reg = <0x59820000 0x200>;
 541
 542                         peri_clk: clock {
 543                                 compatible = "socionext,uniphier-ld20-peri-clock";
 544                                 #clock-cells = <1>;
 545                         };
 546
 547                         peri_rst: reset {
 548                                 compatible = "socionext,uniphier-ld20-peri-reset";
 549                                 #reset-cells = <1>;
 550                         };
 551                 };
 552
 553                 emmc: sdhc@5a000000 {
 554                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 555                         reg = <0x5a000000 0x400>;
 556                         interrupts = <0 78 4>;
 557                         pinctrl-names = "default";
 558                         pinctrl-0 = <&pinctrl_emmc>;
 559                         clocks = <&sys_clk 4>;
 560                         resets = <&sys_rst 4>;
 561                         bus-width = <8>;
 562                         mmc-ddr-1_8v;
 563                         mmc-hs200-1_8v;
 564                         mmc-pwrseq = <&emmc_pwrseq>;
 565                         cdns,phy-input-delay-legacy = <9>;
 566                         cdns,phy-input-delay-mmc-highspeed = <2>;
 567                         cdns,phy-input-delay-mmc-ddr = <3>;
 568                         cdns,phy-dll-delay-sdclk = <21>;
 569                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 570                 };
 571
 572                 sd: sdhc@5a400000 {
 573                         compatible = "socionext,uniphier-sd-v3.1.1";
 574                         status = "disabled";
 575                         reg = <0x5a400000 0x800>;
 576                         interrupts = <0 76 4>;
 577                         pinctrl-names = "default";
 578                         pinctrl-0 = <&pinctrl_sd>;
 579                         clocks = <&sd_clk 0>;
 580                         reset-names = "host";
 581                         resets = <&sd_rst 0>;
 582                         bus-width = <4>;
 583                         cap-sd-highspeed;
 584                 };
 585
 586                 soc_glue: soc-glue@5f800000 {
 587                         compatible = "socionext,uniphier-ld20-soc-glue",
 588                                      "simple-mfd", "syscon";
 589                         reg = <0x5f800000 0x2000>;
 590
 591                         pinctrl: pinctrl {
 592                                 compatible = "socionext,uniphier-ld20-pinctrl";
 593                         };
 594                 };
 595
 596                 soc-glue@5f900000 {
 597                         compatible = "socionext,uniphier-ld20-soc-glue-debug",
 598                                      "simple-mfd";
 599                         #address-cells = <1>;
 600                         #size-cells = <1>;
 601                         ranges = <0 0x5f900000 0x2000>;
 602
 603                         efuse@100 {
 604                                 compatible = "socionext,uniphier-efuse";
 605                                 reg = <0x100 0x28>;
 606                         };
 607
 608                         efuse@200 {
 609                                 compatible = "socionext,uniphier-efuse";
 610                                 reg = <0x200 0x68>;
 611                                 #address-cells = <1>;
 612                                 #size-cells = <1>;
 613
 614                                 /* USB cells */
 615                                 usb_rterm0: trim@54,4 {
 616                                         reg = <0x54 1>;
 617                                         bits = <4 2>;
 618                                 };
 619                                 usb_rterm1: trim@55,4 {
 620                                         reg = <0x55 1>;
 621                                         bits = <4 2>;
 622                                 };
 623                                 usb_rterm2: trim@58,4 {
 624                                         reg = <0x58 1>;
 625                                         bits = <4 2>;
 626                                 };
 627                                 usb_rterm3: trim@59,4 {
 628                                         reg = <0x59 1>;
 629                                         bits = <4 2>;
 630                                 };
 631                                 usb_sel_t0: trim@54,0 {
 632                                         reg = <0x54 1>;
 633                                         bits = <0 4>;
 634                                 };
 635                                 usb_sel_t1: trim@55,0 {
 636                                         reg = <0x55 1>;
 637                                         bits = <0 4>;
 638                                 };
 639                                 usb_sel_t2: trim@58,0 {
 640                                         reg = <0x58 1>;
 641                                         bits = <0 4>;
 642                                 };
 643                                 usb_sel_t3: trim@59,0 {
 644                                         reg = <0x59 1>;
 645                                         bits = <0 4>;
 646                                 };
 647                                 usb_hs_i0: trim@56,0 {
 648                                         reg = <0x56 1>;
 649                                         bits = <0 4>;
 650                                 };
 651                                 usb_hs_i2: trim@5a,0 {
 652                                         reg = <0x5a 1>;
 653                                         bits = <0 4>;
 654                                 };
 655                         };
 656                 };
 657
 658                 aidet: aidet@5fc20000 {
 659                         compatible = "socionext,uniphier-ld20-aidet";
 660                         reg = <0x5fc20000 0x200>;
 661                         interrupt-controller;
 662                         #interrupt-cells = <2>;
 663                 };
 664
 665                 gic: interrupt-controller@5fe00000 {
 666                         compatible = "arm,gic-v3";
 667                         reg = <0x5fe00000 0x10000>,     /* GICD */
 668                               <0x5fe80000 0x80000>;     /* GICR */
 669                         interrupt-controller;
 670                         #interrupt-cells = <3>;
 671                         interrupts = <1 9 4>;
 672                 };
 673
 674                 sysctrl@61840000 {
 675                         compatible = "socionext,uniphier-ld20-sysctrl",
 676                                      "simple-mfd", "syscon";
 677                         reg = <0x61840000 0x10000>;
 678
 679                         sys_clk: clock {
 680                                 compatible = "socionext,uniphier-ld20-clock";
 681                                 #clock-cells = <1>;
 682                         };
 683
 684                         sys_rst: reset {
 685                                 compatible = "socionext,uniphier-ld20-reset";
 686                                 #reset-cells = <1>;
 687                         };
 688
 689                         watchdog {
 690                                 compatible = "socionext,uniphier-wdt";
 691                         };
 692
 693                         pvtctl: pvtctl {
 694                                 compatible = "socionext,uniphier-ld20-thermal";
 695                                 interrupts = <0 3 4>;
 696                                 #thermal-sensor-cells = <0>;
 697                                 socionext,tmod-calibration = <0x0f22 0x68ee>;
 698                         };
 699                 };
 700
 701                 eth: ethernet@65000000 {
 702                         compatible = "socionext,uniphier-ld20-ave4";
 703                         status = "disabled";
 704                         reg = <0x65000000 0x8500>;
 705                         interrupts = <0 66 4>;
 706                         pinctrl-names = "default";
 707                         pinctrl-0 = <&pinctrl_ether_rgmii>;
 708                         clock-names = "ether";
 709                         clocks = <&sys_clk 6>;
 710                         reset-names = "ether";
 711                         resets = <&sys_rst 6>;
 712                         phy-mode = "rgmii";
 713                         local-mac-address = [00 00 00 00 00 00];
 714                         socionext,syscon-phy-mode = <&soc_glue 0>;
 715
 716                         mdio: mdio {
 717                                 #address-cells = <1>;
 718                                 #size-cells = <0>;
 719                         };
 720                 };
 721
 722                 usb: usb@65a00000 {
 723                         compatible = "socionext,uniphier-dwc3", "snps,dwc3";
 724                         status = "disabled";
 725                         reg = <0x65a00000 0xcd00>;
 726                         interrupt-names = "host";
 727                         interrupts = <0 134 4>;
 728                         pinctrl-names = "default";
 729                         pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
 730                                     <&pinctrl_usb2>, <&pinctrl_usb3>;
 731                         clock-names = "ref", "bus_early", "suspend";
 732                         clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
 733                         resets = <&usb_rst 15>;
 734                         phys = <&usb_hsphy0>, <&usb_hsphy1>,
 735                                <&usb_hsphy2>, <&usb_hsphy3>,
 736                                <&usb_ssphy0>, <&usb_ssphy1>;
 737                         dr_mode = "host";
 738                 };
 739
 740                 usb-glue@65b00000 {
 741                         compatible = "socionext,uniphier-ld20-dwc3-glue",
 742                                      "simple-mfd";
 743                         #address-cells = <1>;
 744                         #size-cells = <1>;
 745                         ranges = <0 0x65b00000 0x400>;
 746
 747                         usb_rst: reset@0 {
 748                                 compatible = "socionext,uniphier-ld20-usb3-reset";
 749                                 reg = <0x0 0x4>;
 750                                 #reset-cells = <1>;
 751                                 clock-names = "link";
 752                                 clocks = <&sys_clk 14>;
 753                                 reset-names = "link";
 754                                 resets = <&sys_rst 14>;
 755                         };
 756
 757                         usb_vbus0: regulator@100 {
 758                                 compatible = "socionext,uniphier-ld20-usb3-regulator";
 759                                 reg = <0x100 0x10>;
 760                                 clock-names = "link";
 761                                 clocks = <&sys_clk 14>;
 762                                 reset-names = "link";
 763                                 resets = <&sys_rst 14>;
 764                         };
 765
 766                         usb_vbus1: regulator@110 {
 767                                 compatible = "socionext,uniphier-ld20-usb3-regulator";
 768                                 reg = <0x110 0x10>;
 769                                 clock-names = "link";
 770                                 clocks = <&sys_clk 14>;
 771                                 reset-names = "link";
 772                                 resets = <&sys_rst 14>;
 773                         };
 774
 775                         usb_vbus2: regulator@120 {
 776                                 compatible = "socionext,uniphier-ld20-usb3-regulator";
 777                                 reg = <0x120 0x10>;
 778                                 clock-names = "link";
 779                                 clocks = <&sys_clk 14>;
 780                                 reset-names = "link";
 781                                 resets = <&sys_rst 14>;
 782                         };
 783
 784                         usb_vbus3: regulator@130 {
 785                                 compatible = "socionext,uniphier-ld20-usb3-regulator";
 786                                 reg = <0x130 0x10>;
 787                                 clock-names = "link";
 788                                 clocks = <&sys_clk 14>;
 789                                 reset-names = "link";
 790                                 resets = <&sys_rst 14>;
 791                         };
 792
 793                         usb_hsphy0: hs-phy@200 {
 794                                 compatible = "socionext,uniphier-ld20-usb3-hsphy";
 795                                 reg = <0x200 0x10>;
 796                                 #phy-cells = <0>;
 797                                 clock-names = "link", "phy";
 798                                 clocks = <&sys_clk 14>, <&sys_clk 16>;
 799                                 reset-names = "link", "phy";
 800                                 resets = <&sys_rst 14>, <&sys_rst 16>;
 801                                 vbus-supply = <&usb_vbus0>;
 802                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 803                                 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
 804                                               <&usb_hs_i0>;
 805                         };
 806
 807                         usb_hsphy1: hs-phy@210 {
 808                                 compatible = "socionext,uniphier-ld20-usb3-hsphy";
 809                                 reg = <0x210 0x10>;
 810                                 #phy-cells = <0>;
 811                                 clock-names = "link", "phy";
 812                                 clocks = <&sys_clk 14>, <&sys_clk 16>;
 813                                 reset-names = "link", "phy";
 814                                 resets = <&sys_rst 14>, <&sys_rst 16>;
 815                                 vbus-supply = <&usb_vbus1>;
 816                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 817                                 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
 818                                               <&usb_hs_i0>;
 819                         };
 820
 821                         usb_hsphy2: hs-phy@220 {
 822                                 compatible = "socionext,uniphier-ld20-usb3-hsphy";
 823                                 reg = <0x220 0x10>;
 824                                 #phy-cells = <0>;
 825                                 clock-names = "link", "phy";
 826                                 clocks = <&sys_clk 14>, <&sys_clk 17>;
 827                                 reset-names = "link", "phy";
 828                                 resets = <&sys_rst 14>, <&sys_rst 17>;
 829                                 vbus-supply = <&usb_vbus2>;
 830                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 831                                 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
 832                                               <&usb_hs_i2>;
 833                         };
 834
 835                         usb_hsphy3: hs-phy@230 {
 836                                 compatible = "socionext,uniphier-ld20-usb3-hsphy";
 837                                 reg = <0x230 0x10>;
 838                                 #phy-cells = <0>;
 839                                 clock-names = "link", "phy";
 840                                 clocks = <&sys_clk 14>, <&sys_clk 17>;
 841                                 reset-names = "link", "phy";
 842                                 resets = <&sys_rst 14>, <&sys_rst 17>;
 843                                 vbus-supply = <&usb_vbus3>;
 844                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 845                                 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
 846                                               <&usb_hs_i2>;
 847                         };
 848
 849                         usb_ssphy0: ss-phy@300 {
 850                                 compatible = "socionext,uniphier-ld20-usb3-ssphy";
 851                                 reg = <0x300 0x10>;
 852                                 #phy-cells = <0>;
 853                                 clock-names = "link", "phy";
 854                                 clocks = <&sys_clk 14>, <&sys_clk 18>;
 855                                 reset-names = "link", "phy";
 856                                 resets = <&sys_rst 14>, <&sys_rst 18>;
 857                                 vbus-supply = <&usb_vbus0>;
 858                         };
 859
 860                         usb_ssphy1: ss-phy@310 {
 861                                 compatible = "socionext,uniphier-ld20-usb3-ssphy";
 862                                 reg = <0x310 0x10>;
 863                                 #phy-cells = <0>;
 864                                 clock-names = "link", "phy";
 865                                 clocks = <&sys_clk 14>, <&sys_clk 19>;
 866                                 reset-names = "link", "phy";
 867                                 resets = <&sys_rst 14>, <&sys_rst 19>;
 868                                 vbus-supply = <&usb_vbus1>;
 869                         };
 870                 };
 871
 872                 pcie: pcie@66000000 {
 873                         compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
 874                         status = "disabled";
 875                         reg-names = "dbi", "link", "config";
 876                         reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
 877                               <0x2fff0000 0x10000>;
 878                         #address-cells = <3>;
 879                         #size-cells = <2>;
 880                         clocks = <&sys_clk 24>;
 881                         resets = <&sys_rst 24>;
 882                         num-lanes = <1>;
 883                         num-viewport = <1>;
 884                         bus-range = <0x0 0xff>;
 885                         device_type = "pci";
 886                         ranges =
 887                         /* downstream I/O */
 888                                 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
 889                         /* non-prefetchable memory */
 890                                 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
 891                         #interrupt-cells = <1>;
 892                         interrupt-names = "dma", "msi";
 893                         interrupts = <0 224 4>, <0 225 4>;
 894                         interrupt-map-mask = <0 0 0 7>;
 895                         interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
 896                                         <0 0 0 2 &pcie_intc 1>, /* INTB */
 897                                         <0 0 0 3 &pcie_intc 2>, /* INTC */
 898                                         <0 0 0 4 &pcie_intc 3>; /* INTD */
 899                         phy-names = "pcie-phy";
 900                         phys = <&pcie_phy>;
 901
 902                         pcie_intc: legacy-interrupt-controller {
 903                                 interrupt-controller;
 904                                 #interrupt-cells = <1>;
 905                                 interrupt-parent = <&gic>;
 906                                 interrupts = <0 226 4>;
 907                         };
 908                 };
 909
 910                 pcie_phy: phy@66038000 {
 911                         compatible = "socionext,uniphier-ld20-pcie-phy";
 912                         reg = <0x66038000 0x4000>;
 913                         #phy-cells = <0>;
 914                         clocks = <&sys_clk 24>;
 915                         resets = <&sys_rst 24>;
 916                         socionext,syscon = <&soc_glue>;
 917                 };
 918
 919                 nand: nand@68000000 {
 920                         compatible = "socionext,uniphier-denali-nand-v5b";
 921                         status = "disabled";
 922                         reg-names = "nand_data", "denali_reg";
 923                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 924                         interrupts = <0 65 4>;
 925                         pinctrl-names = "default";
 926                         pinctrl-0 = <&pinctrl_nand>;
 927                         clock-names = "nand", "nand_x", "ecc";
 928                         clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 929                         resets = <&sys_rst 2>;
 930                 };
 931         };
 932 };
 933
 934 #include "uniphier-pinctrl.dtsi"
 935
 936 &pinctrl_aout1 {
 937         drive-strength = <4>;   /* default: 3.5mA */
 938
 939         ao1dacck {
 940                 pins = "AO1DACCK";
 941                 drive-strength = <5>;   /* 5mA */
 942         };
 943 };
 944
 945 &pinctrl_aoutiec1 {
 946         drive-strength = <4>;   /* default: 3.5mA */
 947
 948         ao1arc {
 949                 pins = "AO1ARC";
 950                 drive-strength = <11>;  /* 11mA */
 951         };
 952 };