2 * Device Tree Source for UniPhier LD11 SoC
4 * Copyright (C) 2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /memreserve/ 0x80000000 0x02000000;
13 compatible = "socionext,uniphier-ld11";
16 interrupt-parent = <&gic>;
35 compatible = "arm,cortex-a53", "arm,armv8";
37 clocks = <&sys_clk 33>;
38 enable-method = "psci";
39 operating-points-v2 = <&cluster0_opp>;
44 compatible = "arm,cortex-a53", "arm,armv8";
46 clocks = <&sys_clk 33>;
47 enable-method = "psci";
48 operating-points-v2 = <&cluster0_opp>;
52 cluster0_opp: opp_table {
53 compatible = "operating-points-v2";
57 opp-hz = /bits/ 64 <245000000>;
58 clock-latency-ns = <300>;
61 opp-hz = /bits/ 64 <250000000>;
62 clock-latency-ns = <300>;
65 opp-hz = /bits/ 64 <490000000>;
66 clock-latency-ns = <300>;
69 opp-hz = /bits/ 64 <500000000>;
70 clock-latency-ns = <300>;
73 opp-hz = /bits/ 64 <653334000>;
74 clock-latency-ns = <300>;
77 opp-hz = /bits/ 64 <666667000>;
78 clock-latency-ns = <300>;
81 opp-hz = /bits/ 64 <980000000>;
82 clock-latency-ns = <300>;
87 compatible = "arm,psci-1.0";
93 compatible = "fixed-clock";
95 clock-frequency = <25000000>;
100 compatible = "arm,armv8-timer";
101 interrupts = <1 13 4>,
108 compatible = "simple-bus";
109 #address-cells = <1>;
111 ranges = <0 0 0 0xffffffff>;
113 serial0: serial@54006800 {
114 compatible = "socionext,uniphier-uart";
116 reg = <0x54006800 0x40>;
117 interrupts = <0 33 4>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_uart0>;
120 clocks = <&peri_clk 0>;
123 serial1: serial@54006900 {
124 compatible = "socionext,uniphier-uart";
126 reg = <0x54006900 0x40>;
127 interrupts = <0 35 4>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_uart1>;
130 clocks = <&peri_clk 1>;
133 serial2: serial@54006a00 {
134 compatible = "socionext,uniphier-uart";
136 reg = <0x54006a00 0x40>;
137 interrupts = <0 37 4>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_uart2>;
140 clocks = <&peri_clk 2>;
143 serial3: serial@54006b00 {
144 compatible = "socionext,uniphier-uart";
146 reg = <0x54006b00 0x40>;
147 interrupts = <0 177 4>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_uart3>;
150 clocks = <&peri_clk 3>;
154 compatible = "socionext,uniphier-fi2c";
156 reg = <0x58780000 0x80>;
157 #address-cells = <1>;
159 interrupts = <0 41 4>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_i2c0>;
162 clocks = <&peri_clk 4>;
163 clock-frequency = <100000>;
167 compatible = "socionext,uniphier-fi2c";
169 reg = <0x58781000 0x80>;
170 #address-cells = <1>;
172 interrupts = <0 42 4>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_i2c1>;
175 clocks = <&peri_clk 5>;
176 clock-frequency = <100000>;
180 compatible = "socionext,uniphier-fi2c";
181 reg = <0x58782000 0x80>;
182 #address-cells = <1>;
184 interrupts = <0 43 4>;
185 clocks = <&peri_clk 6>;
186 clock-frequency = <400000>;
190 compatible = "socionext,uniphier-fi2c";
192 reg = <0x58783000 0x80>;
193 #address-cells = <1>;
195 interrupts = <0 44 4>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_i2c3>;
198 clocks = <&peri_clk 7>;
199 clock-frequency = <100000>;
203 compatible = "socionext,uniphier-fi2c";
205 reg = <0x58784000 0x80>;
206 #address-cells = <1>;
208 interrupts = <0 45 4>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_i2c4>;
211 clocks = <&peri_clk 8>;
212 clock-frequency = <100000>;
216 compatible = "socionext,uniphier-fi2c";
217 reg = <0x58785000 0x80>;
218 #address-cells = <1>;
220 interrupts = <0 25 4>;
221 clocks = <&peri_clk 9>;
222 clock-frequency = <400000>;
225 system_bus: system-bus@58c00000 {
226 compatible = "socionext,uniphier-system-bus";
228 reg = <0x58c00000 0x400>;
229 #address-cells = <2>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_system_bus>;
236 compatible = "socionext,uniphier-smpctrl";
237 reg = <0x59801000 0x400>;
241 compatible = "socionext,uniphier-ld11-sdctrl",
242 "simple-mfd", "syscon";
243 reg = <0x59810000 0x400>;
246 compatible = "socionext,uniphier-ld11-sd-reset";
252 compatible = "socionext,uniphier-ld11-perictrl",
253 "simple-mfd", "syscon";
254 reg = <0x59820000 0x200>;
257 compatible = "socionext,uniphier-ld11-peri-clock";
262 compatible = "socionext,uniphier-ld11-peri-reset";
267 emmc: sdhc@5a000000 {
268 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
269 reg = <0x5a000000 0x400>;
270 interrupts = <0 78 4>;
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_emmc>;
273 clocks = <&sys_clk 4>;
277 cdns,phy-input-delay-legacy = <4>;
278 cdns,phy-input-delay-mmc-highspeed = <2>;
279 cdns,phy-input-delay-mmc-ddr = <3>;
280 cdns,phy-dll-delay-sdclk = <21>;
281 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
285 compatible = "socionext,uniphier-ehci", "generic-ehci";
287 reg = <0x5a800100 0x100>;
288 interrupts = <0 243 4>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_usb0>;
291 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
292 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
297 compatible = "socionext,uniphier-ehci", "generic-ehci";
299 reg = <0x5a810100 0x100>;
300 interrupts = <0 244 4>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_usb1>;
303 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
304 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
309 compatible = "socionext,uniphier-ehci", "generic-ehci";
311 reg = <0x5a820100 0x100>;
312 interrupts = <0 245 4>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_usb2>;
315 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
316 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
321 compatible = "socionext,uniphier-ld11-mioctrl",
322 "simple-mfd", "syscon";
323 reg = <0x5b3e0000 0x800>;
326 compatible = "socionext,uniphier-ld11-mio-clock";
331 compatible = "socionext,uniphier-ld11-mio-reset";
333 resets = <&sys_rst 7>;
338 compatible = "socionext,uniphier-ld11-soc-glue",
339 "simple-mfd", "syscon";
340 reg = <0x5f800000 0x2000>;
343 compatible = "socionext,uniphier-ld11-pinctrl";
347 gic: interrupt-controller@5fe00000 {
348 compatible = "arm,gic-v3";
349 reg = <0x5fe00000 0x10000>, /* GICD */
350 <0x5fe40000 0x80000>; /* GICR */
351 interrupt-controller;
352 #interrupt-cells = <3>;
353 interrupts = <1 9 4>;
357 compatible = "socionext,uniphier-ld11-sysctrl",
358 "simple-mfd", "syscon";
359 reg = <0x61840000 0x10000>;
362 compatible = "socionext,uniphier-ld11-clock";
367 compatible = "socionext,uniphier-ld11-reset";
374 /include/ "uniphier-pinctrl.dtsi"