2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
54 interrupt-parent = <&gic>;
108 compatible = "arm,cortex-a53", "arm,armv8";
110 enable-method = "psci";
111 #cooling-cells = <2>; /* min followed by max */
112 clocks = <&cru ARMCLKL>;
113 dynamic-power-coefficient = <100>;
118 compatible = "arm,cortex-a53", "arm,armv8";
120 enable-method = "psci";
121 clocks = <&cru ARMCLKL>;
122 dynamic-power-coefficient = <100>;
127 compatible = "arm,cortex-a53", "arm,armv8";
129 enable-method = "psci";
130 clocks = <&cru ARMCLKL>;
131 dynamic-power-coefficient = <100>;
136 compatible = "arm,cortex-a53", "arm,armv8";
138 enable-method = "psci";
139 clocks = <&cru ARMCLKL>;
140 dynamic-power-coefficient = <100>;
145 compatible = "arm,cortex-a72", "arm,armv8";
147 enable-method = "psci";
148 #cooling-cells = <2>; /* min followed by max */
149 clocks = <&cru ARMCLKB>;
150 dynamic-power-coefficient = <436>;
155 compatible = "arm,cortex-a72", "arm,armv8";
157 enable-method = "psci";
158 clocks = <&cru ARMCLKB>;
159 dynamic-power-coefficient = <436>;
164 compatible = "rockchip,display-subsystem";
165 ports = <&vopl_out>, <&vopb_out>;
169 compatible = "arm,cortex-a53-pmu";
170 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
174 compatible = "arm,cortex-a72-pmu";
175 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
179 compatible = "arm,psci-1.0";
184 compatible = "arm,armv8-timer";
185 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
186 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
187 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
188 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
189 arm,no-tick-in-suspend;
193 compatible = "fixed-clock";
194 clock-frequency = <24000000>;
195 clock-output-names = "xin24m";
200 compatible = "simple-bus";
201 #address-cells = <2>;
205 dmac_bus: dma-controller@ff6d0000 {
206 compatible = "arm,pl330", "arm,primecell";
207 reg = <0x0 0xff6d0000 0x0 0x4000>;
208 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
209 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
211 clocks = <&cru ACLK_DMAC0_PERILP>;
212 clock-names = "apb_pclk";
215 dmac_peri: dma-controller@ff6e0000 {
216 compatible = "arm,pl330", "arm,primecell";
217 reg = <0x0 0xff6e0000 0x0 0x4000>;
218 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
219 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
221 clocks = <&cru ACLK_DMAC1_PERILP>;
222 clock-names = "apb_pclk";
226 pcie0: pcie@f8000000 {
227 compatible = "rockchip,rk3399-pcie";
228 reg = <0x0 0xf8000000 0x0 0x2000000>,
229 <0x0 0xfd000000 0x0 0x1000000>;
230 reg-names = "axi-base", "apb-base";
231 #address-cells = <3>;
233 #interrupt-cells = <1>;
235 bus-range = <0x0 0x1f>;
236 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
237 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
238 clock-names = "aclk", "aclk-perf",
240 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
241 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
242 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
243 interrupt-names = "sys", "legacy", "client";
244 interrupt-map-mask = <0 0 0 7>;
245 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
246 <0 0 0 2 &pcie0_intc 1>,
247 <0 0 0 3 &pcie0_intc 2>,
248 <0 0 0 4 &pcie0_intc 3>;
249 linux,pci-domain = <0>;
250 max-link-speed = <1>;
251 msi-map = <0x0 &its 0x0 0x1000>;
252 phys = <&pcie_phy 0>, <&pcie_phy 1>,
253 <&pcie_phy 2>, <&pcie_phy 3>;
254 phy-names = "pcie-phy-0", "pcie-phy-1",
255 "pcie-phy-2", "pcie-phy-3";
256 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
257 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
258 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
259 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
260 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
262 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
263 "pm", "pclk", "aclk";
266 pcie0_intc: interrupt-controller {
267 interrupt-controller;
268 #address-cells = <0>;
269 #interrupt-cells = <1>;
273 gmac: ethernet@fe300000 {
274 compatible = "rockchip,rk3399-gmac";
275 reg = <0x0 0xfe300000 0x0 0x10000>;
276 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
277 interrupt-names = "macirq";
278 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
279 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
280 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
282 clock-names = "stmmaceth", "mac_clk_rx",
283 "mac_clk_tx", "clk_mac_ref",
284 "clk_mac_refout", "aclk_mac",
286 power-domains = <&power RK3399_PD_GMAC>;
287 resets = <&cru SRST_A_GMAC>;
288 reset-names = "stmmaceth";
289 rockchip,grf = <&grf>;
293 sdio0: dwmmc@fe310000 {
294 compatible = "rockchip,rk3399-dw-mshc",
295 "rockchip,rk3288-dw-mshc";
296 reg = <0x0 0xfe310000 0x0 0x4000>;
297 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
298 max-frequency = <150000000>;
299 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
300 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
301 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
302 fifo-depth = <0x100>;
303 power-domains = <&power RK3399_PD_SDIOAUDIO>;
304 resets = <&cru SRST_SDIO0>;
305 reset-names = "reset";
309 sdmmc: dwmmc@fe320000 {
310 compatible = "rockchip,rk3399-dw-mshc",
311 "rockchip,rk3288-dw-mshc";
312 reg = <0x0 0xfe320000 0x0 0x4000>;
313 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
314 max-frequency = <150000000>;
315 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
316 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
317 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
318 fifo-depth = <0x100>;
319 power-domains = <&power RK3399_PD_SD>;
320 resets = <&cru SRST_SDMMC>;
321 reset-names = "reset";
325 sdhci: sdhci@fe330000 {
326 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
327 reg = <0x0 0xfe330000 0x0 0x10000>;
328 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
329 arasan,soc-ctl-syscon = <&grf>;
330 assigned-clocks = <&cru SCLK_EMMC>;
331 assigned-clock-rates = <200000000>;
332 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
333 clock-names = "clk_xin", "clk_ahb";
334 clock-output-names = "emmc_cardclock";
337 phy-names = "phy_arasan";
338 power-domains = <&power RK3399_PD_EMMC>;
342 usb_host0_ehci: usb@fe380000 {
343 compatible = "generic-ehci";
344 reg = <0x0 0xfe380000 0x0 0x20000>;
345 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
346 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
348 clock-names = "usbhost", "arbiter",
350 phys = <&u2phy0_host>;
355 usb_host0_ohci: usb@fe3a0000 {
356 compatible = "generic-ohci";
357 reg = <0x0 0xfe3a0000 0x0 0x20000>;
358 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
359 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
361 clock-names = "usbhost", "arbiter",
363 phys = <&u2phy0_host>;
368 usb_host1_ehci: usb@fe3c0000 {
369 compatible = "generic-ehci";
370 reg = <0x0 0xfe3c0000 0x0 0x20000>;
371 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
372 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
374 clock-names = "usbhost", "arbiter",
376 phys = <&u2phy1_host>;
381 usb_host1_ohci: usb@fe3e0000 {
382 compatible = "generic-ohci";
383 reg = <0x0 0xfe3e0000 0x0 0x20000>;
384 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
385 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
387 clock-names = "usbhost", "arbiter",
389 phys = <&u2phy1_host>;
394 usbdrd3_0: usb@fe800000 {
395 compatible = "rockchip,rk3399-dwc3";
396 #address-cells = <2>;
399 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
400 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
401 clock-names = "ref_clk", "suspend_clk",
402 "bus_clk", "grf_clk";
405 usbdrd_dwc3_0: dwc3 {
406 compatible = "snps,dwc3";
407 reg = <0x0 0xfe800000 0x0 0x100000>;
408 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
410 phys = <&u2phy0_otg>;
411 phy-names = "usb2-phy";
412 phy_type = "utmi_wide";
413 snps,dis_enblslpm_quirk;
414 snps,dis-u2-freeclk-exists-quirk;
415 snps,dis_u2_susphy_quirk;
416 snps,dis-del-phy-power-chg-quirk;
417 snps,dis-tx-ipgap-linecheck-quirk;
422 usbdrd3_1: usb@fe900000 {
423 compatible = "rockchip,rk3399-dwc3";
424 #address-cells = <2>;
427 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
428 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
429 clock-names = "ref_clk", "suspend_clk",
430 "bus_clk", "grf_clk";
433 usbdrd_dwc3_1: dwc3 {
434 compatible = "snps,dwc3";
435 reg = <0x0 0xfe900000 0x0 0x100000>;
436 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
438 phys = <&u2phy1_otg>;
439 phy-names = "usb2-phy";
440 phy_type = "utmi_wide";
441 snps,dis_enblslpm_quirk;
442 snps,dis-u2-freeclk-exists-quirk;
443 snps,dis_u2_susphy_quirk;
444 snps,dis-del-phy-power-chg-quirk;
445 snps,dis-tx-ipgap-linecheck-quirk;
450 gic: interrupt-controller@fee00000 {
451 compatible = "arm,gic-v3";
452 #interrupt-cells = <4>;
453 #address-cells = <2>;
456 interrupt-controller;
458 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
459 <0x0 0xfef00000 0 0xc0000>, /* GICR */
460 <0x0 0xfff00000 0 0x10000>, /* GICC */
461 <0x0 0xfff10000 0 0x10000>, /* GICH */
462 <0x0 0xfff20000 0 0x10000>; /* GICV */
463 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
464 its: interrupt-controller@fee20000 {
465 compatible = "arm,gic-v3-its";
467 reg = <0x0 0xfee20000 0x0 0x20000>;
471 ppi_cluster0: interrupt-partition-0 {
472 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
475 ppi_cluster1: interrupt-partition-1 {
476 affinity = <&cpu_b0 &cpu_b1>;
481 saradc: saradc@ff100000 {
482 compatible = "rockchip,rk3399-saradc";
483 reg = <0x0 0xff100000 0x0 0x100>;
484 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
485 #io-channel-cells = <1>;
486 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
487 clock-names = "saradc", "apb_pclk";
488 resets = <&cru SRST_P_SARADC>;
489 reset-names = "saradc-apb";
494 compatible = "rockchip,rk3399-i2c";
495 reg = <0x0 0xff110000 0x0 0x1000>;
496 assigned-clocks = <&cru SCLK_I2C1>;
497 assigned-clock-rates = <200000000>;
498 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
499 clock-names = "i2c", "pclk";
500 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2c1_xfer>;
503 #address-cells = <1>;
509 compatible = "rockchip,rk3399-i2c";
510 reg = <0x0 0xff120000 0x0 0x1000>;
511 assigned-clocks = <&cru SCLK_I2C2>;
512 assigned-clock-rates = <200000000>;
513 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
514 clock-names = "i2c", "pclk";
515 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
516 pinctrl-names = "default";
517 pinctrl-0 = <&i2c2_xfer>;
518 #address-cells = <1>;
524 compatible = "rockchip,rk3399-i2c";
525 reg = <0x0 0xff130000 0x0 0x1000>;
526 assigned-clocks = <&cru SCLK_I2C3>;
527 assigned-clock-rates = <200000000>;
528 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
529 clock-names = "i2c", "pclk";
530 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
531 pinctrl-names = "default";
532 pinctrl-0 = <&i2c3_xfer>;
533 #address-cells = <1>;
539 compatible = "rockchip,rk3399-i2c";
540 reg = <0x0 0xff140000 0x0 0x1000>;
541 assigned-clocks = <&cru SCLK_I2C5>;
542 assigned-clock-rates = <200000000>;
543 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
544 clock-names = "i2c", "pclk";
545 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2c5_xfer>;
548 #address-cells = <1>;
554 compatible = "rockchip,rk3399-i2c";
555 reg = <0x0 0xff150000 0x0 0x1000>;
556 assigned-clocks = <&cru SCLK_I2C6>;
557 assigned-clock-rates = <200000000>;
558 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
559 clock-names = "i2c", "pclk";
560 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&i2c6_xfer>;
563 #address-cells = <1>;
569 compatible = "rockchip,rk3399-i2c";
570 reg = <0x0 0xff160000 0x0 0x1000>;
571 assigned-clocks = <&cru SCLK_I2C7>;
572 assigned-clock-rates = <200000000>;
573 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
574 clock-names = "i2c", "pclk";
575 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&i2c7_xfer>;
578 #address-cells = <1>;
583 uart0: serial@ff180000 {
584 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
585 reg = <0x0 0xff180000 0x0 0x100>;
586 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
587 clock-names = "baudclk", "apb_pclk";
588 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
591 pinctrl-names = "default";
592 pinctrl-0 = <&uart0_xfer>;
596 uart1: serial@ff190000 {
597 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
598 reg = <0x0 0xff190000 0x0 0x100>;
599 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
600 clock-names = "baudclk", "apb_pclk";
601 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&uart1_xfer>;
609 uart2: serial@ff1a0000 {
610 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
611 reg = <0x0 0xff1a0000 0x0 0x100>;
612 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
613 clock-names = "baudclk", "apb_pclk";
614 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
617 pinctrl-names = "default";
618 pinctrl-0 = <&uart2c_xfer>;
622 uart3: serial@ff1b0000 {
623 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
624 reg = <0x0 0xff1b0000 0x0 0x100>;
625 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
626 clock-names = "baudclk", "apb_pclk";
627 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&uart3_xfer>;
636 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
637 reg = <0x0 0xff1c0000 0x0 0x1000>;
638 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
639 clock-names = "spiclk", "apb_pclk";
640 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
641 pinctrl-names = "default";
642 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
643 #address-cells = <1>;
649 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
650 reg = <0x0 0xff1d0000 0x0 0x1000>;
651 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
652 clock-names = "spiclk", "apb_pclk";
653 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
656 #address-cells = <1>;
662 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
663 reg = <0x0 0xff1e0000 0x0 0x1000>;
664 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
665 clock-names = "spiclk", "apb_pclk";
666 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
667 pinctrl-names = "default";
668 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
669 #address-cells = <1>;
675 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
676 reg = <0x0 0xff1f0000 0x0 0x1000>;
677 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
678 clock-names = "spiclk", "apb_pclk";
679 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
680 pinctrl-names = "default";
681 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
682 #address-cells = <1>;
688 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
689 reg = <0x0 0xff200000 0x0 0x1000>;
690 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
691 clock-names = "spiclk", "apb_pclk";
692 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
693 pinctrl-names = "default";
694 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
695 power-domains = <&power RK3399_PD_SDIOAUDIO>;
696 #address-cells = <1>;
701 thermal_zones: thermal-zones {
703 polling-delay-passive = <100>;
704 polling-delay = <1000>;
706 thermal-sensors = <&tsadc 0>;
709 cpu_alert0: cpu_alert0 {
710 temperature = <70000>;
714 cpu_alert1: cpu_alert1 {
715 temperature = <75000>;
720 temperature = <95000>;
728 trip = <&cpu_alert0>;
730 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
733 trip = <&cpu_alert1>;
735 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
736 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
742 polling-delay-passive = <100>;
743 polling-delay = <1000>;
745 thermal-sensors = <&tsadc 1>;
748 gpu_alert0: gpu_alert0 {
749 temperature = <75000>;
754 temperature = <95000>;
762 trip = <&gpu_alert0>;
764 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
770 tsadc: tsadc@ff260000 {
771 compatible = "rockchip,rk3399-tsadc";
772 reg = <0x0 0xff260000 0x0 0x100>;
773 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
774 assigned-clocks = <&cru SCLK_TSADC>;
775 assigned-clock-rates = <750000>;
776 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
777 clock-names = "tsadc", "apb_pclk";
778 resets = <&cru SRST_TSADC>;
779 reset-names = "tsadc-apb";
780 rockchip,grf = <&grf>;
781 rockchip,hw-tshut-temp = <95000>;
782 pinctrl-names = "init", "default", "sleep";
783 pinctrl-0 = <&otp_gpio>;
784 pinctrl-1 = <&otp_out>;
785 pinctrl-2 = <&otp_gpio>;
786 #thermal-sensor-cells = <1>;
790 qos_emmc: qos@ffa58000 {
791 compatible = "syscon";
792 reg = <0x0 0xffa58000 0x0 0x20>;
795 qos_gmac: qos@ffa5c000 {
796 compatible = "syscon";
797 reg = <0x0 0xffa5c000 0x0 0x20>;
800 qos_pcie: qos@ffa60080 {
801 compatible = "syscon";
802 reg = <0x0 0xffa60080 0x0 0x20>;
805 qos_usb_host0: qos@ffa60100 {
806 compatible = "syscon";
807 reg = <0x0 0xffa60100 0x0 0x20>;
810 qos_usb_host1: qos@ffa60180 {
811 compatible = "syscon";
812 reg = <0x0 0xffa60180 0x0 0x20>;
815 qos_usb_otg0: qos@ffa70000 {
816 compatible = "syscon";
817 reg = <0x0 0xffa70000 0x0 0x20>;
820 qos_usb_otg1: qos@ffa70080 {
821 compatible = "syscon";
822 reg = <0x0 0xffa70080 0x0 0x20>;
825 qos_sd: qos@ffa74000 {
826 compatible = "syscon";
827 reg = <0x0 0xffa74000 0x0 0x20>;
830 qos_sdioaudio: qos@ffa76000 {
831 compatible = "syscon";
832 reg = <0x0 0xffa76000 0x0 0x20>;
835 qos_hdcp: qos@ffa90000 {
836 compatible = "syscon";
837 reg = <0x0 0xffa90000 0x0 0x20>;
840 qos_iep: qos@ffa98000 {
841 compatible = "syscon";
842 reg = <0x0 0xffa98000 0x0 0x20>;
845 qos_isp0_m0: qos@ffaa0000 {
846 compatible = "syscon";
847 reg = <0x0 0xffaa0000 0x0 0x20>;
850 qos_isp0_m1: qos@ffaa0080 {
851 compatible = "syscon";
852 reg = <0x0 0xffaa0080 0x0 0x20>;
855 qos_isp1_m0: qos@ffaa8000 {
856 compatible = "syscon";
857 reg = <0x0 0xffaa8000 0x0 0x20>;
860 qos_isp1_m1: qos@ffaa8080 {
861 compatible = "syscon";
862 reg = <0x0 0xffaa8080 0x0 0x20>;
865 qos_rga_r: qos@ffab0000 {
866 compatible = "syscon";
867 reg = <0x0 0xffab0000 0x0 0x20>;
870 qos_rga_w: qos@ffab0080 {
871 compatible = "syscon";
872 reg = <0x0 0xffab0080 0x0 0x20>;
875 qos_video_m0: qos@ffab8000 {
876 compatible = "syscon";
877 reg = <0x0 0xffab8000 0x0 0x20>;
880 qos_video_m1_r: qos@ffac0000 {
881 compatible = "syscon";
882 reg = <0x0 0xffac0000 0x0 0x20>;
885 qos_video_m1_w: qos@ffac0080 {
886 compatible = "syscon";
887 reg = <0x0 0xffac0080 0x0 0x20>;
890 qos_vop_big_r: qos@ffac8000 {
891 compatible = "syscon";
892 reg = <0x0 0xffac8000 0x0 0x20>;
895 qos_vop_big_w: qos@ffac8080 {
896 compatible = "syscon";
897 reg = <0x0 0xffac8080 0x0 0x20>;
900 qos_vop_little: qos@ffad0000 {
901 compatible = "syscon";
902 reg = <0x0 0xffad0000 0x0 0x20>;
905 qos_perihp: qos@ffad8080 {
906 compatible = "syscon";
907 reg = <0x0 0xffad8080 0x0 0x20>;
910 qos_gpu: qos@ffae0000 {
911 compatible = "syscon";
912 reg = <0x0 0xffae0000 0x0 0x20>;
915 pmu: power-management@ff310000 {
916 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
917 reg = <0x0 0xff310000 0x0 0x1000>;
920 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
921 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
922 * Some of the power domains are grouped together for every
924 * The detail contents as below.
926 power: power-controller {
927 compatible = "rockchip,rk3399-power-controller";
928 #power-domain-cells = <1>;
929 #address-cells = <1>;
932 /* These power domains are grouped by VD_CENTER */
933 pd_iep@RK3399_PD_IEP {
934 reg = <RK3399_PD_IEP>;
935 clocks = <&cru ACLK_IEP>,
939 pd_rga@RK3399_PD_RGA {
940 reg = <RK3399_PD_RGA>;
941 clocks = <&cru ACLK_RGA>,
943 pm_qos = <&qos_rga_r>,
946 pd_vcodec@RK3399_PD_VCODEC {
947 reg = <RK3399_PD_VCODEC>;
948 clocks = <&cru ACLK_VCODEC>,
950 pm_qos = <&qos_video_m0>;
952 pd_vdu@RK3399_PD_VDU {
953 reg = <RK3399_PD_VDU>;
954 clocks = <&cru ACLK_VDU>,
956 pm_qos = <&qos_video_m1_r>,
960 /* These power domains are grouped by VD_GPU */
961 pd_gpu@RK3399_PD_GPU {
962 reg = <RK3399_PD_GPU>;
963 clocks = <&cru ACLK_GPU>;
967 /* These power domains are grouped by VD_LOGIC */
968 pd_edp@RK3399_PD_EDP {
969 reg = <RK3399_PD_EDP>;
970 clocks = <&cru PCLK_EDP_CTRL>;
972 pd_emmc@RK3399_PD_EMMC {
973 reg = <RK3399_PD_EMMC>;
974 clocks = <&cru ACLK_EMMC>;
975 pm_qos = <&qos_emmc>;
977 pd_gmac@RK3399_PD_GMAC {
978 reg = <RK3399_PD_GMAC>;
979 clocks = <&cru ACLK_GMAC>,
981 pm_qos = <&qos_gmac>;
984 reg = <RK3399_PD_SD>;
985 clocks = <&cru HCLK_SDMMC>,
989 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
990 reg = <RK3399_PD_SDIOAUDIO>;
991 clocks = <&cru HCLK_SDIO>;
992 pm_qos = <&qos_sdioaudio>;
994 pd_vio@RK3399_PD_VIO {
995 reg = <RK3399_PD_VIO>;
996 #address-cells = <1>;
999 pd_hdcp@RK3399_PD_HDCP {
1000 reg = <RK3399_PD_HDCP>;
1001 clocks = <&cru ACLK_HDCP>,
1004 pm_qos = <&qos_hdcp>;
1006 pd_isp0@RK3399_PD_ISP0 {
1007 reg = <RK3399_PD_ISP0>;
1008 clocks = <&cru ACLK_ISP0>,
1010 pm_qos = <&qos_isp0_m0>,
1013 pd_isp1@RK3399_PD_ISP1 {
1014 reg = <RK3399_PD_ISP1>;
1015 clocks = <&cru ACLK_ISP1>,
1017 pm_qos = <&qos_isp1_m0>,
1020 pd_tcpc0@RK3399_PD_TCPC0 {
1021 reg = <RK3399_PD_TCPD0>;
1022 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1023 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1025 pd_tcpc1@RK3399_PD_TCPC1 {
1026 reg = <RK3399_PD_TCPD1>;
1027 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1028 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1030 pd_vo@RK3399_PD_VO {
1031 reg = <RK3399_PD_VO>;
1032 #address-cells = <1>;
1035 pd_vopb@RK3399_PD_VOPB {
1036 reg = <RK3399_PD_VOPB>;
1037 clocks = <&cru ACLK_VOP0>,
1039 pm_qos = <&qos_vop_big_r>,
1042 pd_vopl@RK3399_PD_VOPL {
1043 reg = <RK3399_PD_VOPL>;
1044 clocks = <&cru ACLK_VOP1>,
1046 pm_qos = <&qos_vop_little>;
1053 pmugrf: syscon@ff320000 {
1054 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1055 reg = <0x0 0xff320000 0x0 0x1000>;
1056 #address-cells = <1>;
1059 pmu_io_domains: io-domains {
1060 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1061 status = "disabled";
1065 spi3: spi@ff350000 {
1066 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1067 reg = <0x0 0xff350000 0x0 0x1000>;
1068 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1069 clock-names = "spiclk", "apb_pclk";
1070 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1071 pinctrl-names = "default";
1072 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1073 #address-cells = <1>;
1075 status = "disabled";
1078 uart4: serial@ff370000 {
1079 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1080 reg = <0x0 0xff370000 0x0 0x100>;
1081 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1082 clock-names = "baudclk", "apb_pclk";
1083 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1086 pinctrl-names = "default";
1087 pinctrl-0 = <&uart4_xfer>;
1088 status = "disabled";
1091 i2c0: i2c@ff3c0000 {
1092 compatible = "rockchip,rk3399-i2c";
1093 reg = <0x0 0xff3c0000 0x0 0x1000>;
1094 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1095 assigned-clock-rates = <200000000>;
1096 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1097 clock-names = "i2c", "pclk";
1098 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1099 pinctrl-names = "default";
1100 pinctrl-0 = <&i2c0_xfer>;
1101 #address-cells = <1>;
1103 status = "disabled";
1106 i2c4: i2c@ff3d0000 {
1107 compatible = "rockchip,rk3399-i2c";
1108 reg = <0x0 0xff3d0000 0x0 0x1000>;
1109 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1110 assigned-clock-rates = <200000000>;
1111 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1112 clock-names = "i2c", "pclk";
1113 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1114 pinctrl-names = "default";
1115 pinctrl-0 = <&i2c4_xfer>;
1116 #address-cells = <1>;
1118 status = "disabled";
1121 i2c8: i2c@ff3e0000 {
1122 compatible = "rockchip,rk3399-i2c";
1123 reg = <0x0 0xff3e0000 0x0 0x1000>;
1124 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1125 assigned-clock-rates = <200000000>;
1126 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1127 clock-names = "i2c", "pclk";
1128 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1129 pinctrl-names = "default";
1130 pinctrl-0 = <&i2c8_xfer>;
1131 #address-cells = <1>;
1133 status = "disabled";
1136 pwm0: pwm@ff420000 {
1137 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1138 reg = <0x0 0xff420000 0x0 0x10>;
1140 pinctrl-names = "default";
1141 pinctrl-0 = <&pwm0_pin>;
1142 clocks = <&pmucru PCLK_RKPWM_PMU>;
1143 clock-names = "pwm";
1144 status = "disabled";
1147 pwm1: pwm@ff420010 {
1148 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1149 reg = <0x0 0xff420010 0x0 0x10>;
1151 pinctrl-names = "default";
1152 pinctrl-0 = <&pwm1_pin>;
1153 clocks = <&pmucru PCLK_RKPWM_PMU>;
1154 clock-names = "pwm";
1155 status = "disabled";
1158 pwm2: pwm@ff420020 {
1159 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1160 reg = <0x0 0xff420020 0x0 0x10>;
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&pwm2_pin>;
1164 clocks = <&pmucru PCLK_RKPWM_PMU>;
1165 clock-names = "pwm";
1166 status = "disabled";
1169 pwm3: pwm@ff420030 {
1170 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1171 reg = <0x0 0xff420030 0x0 0x10>;
1173 pinctrl-names = "default";
1174 pinctrl-0 = <&pwm3a_pin>;
1175 clocks = <&pmucru PCLK_RKPWM_PMU>;
1176 clock-names = "pwm";
1177 status = "disabled";
1180 vpu_mmu: iommu@ff650800 {
1181 compatible = "rockchip,iommu";
1182 reg = <0x0 0xff650800 0x0 0x40>;
1183 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1184 interrupt-names = "vpu_mmu";
1186 status = "disabled";
1189 vdec_mmu: iommu@ff660480 {
1190 compatible = "rockchip,iommu";
1191 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1192 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1193 interrupt-names = "vdec_mmu";
1195 status = "disabled";
1198 iep_mmu: iommu@ff670800 {
1199 compatible = "rockchip,iommu";
1200 reg = <0x0 0xff670800 0x0 0x40>;
1201 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1202 interrupt-names = "iep_mmu";
1204 status = "disabled";
1208 compatible = "rockchip,rk3399-rga";
1209 reg = <0x0 0xff680000 0x0 0x10000>;
1210 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1211 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1212 clock-names = "aclk", "hclk", "sclk";
1213 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1214 reset-names = "core", "axi", "ahb";
1215 power-domains = <&power RK3399_PD_RGA>;
1218 efuse0: efuse@ff690000 {
1219 compatible = "rockchip,rk3399-efuse";
1220 reg = <0x0 0xff690000 0x0 0x80>;
1221 #address-cells = <1>;
1223 clocks = <&cru PCLK_EFUSE1024NS>;
1224 clock-names = "pclk_efuse";
1230 cpub_leakage: cpu-leakage@17 {
1233 gpu_leakage: gpu-leakage@18 {
1236 center_leakage: center-leakage@19 {
1239 cpul_leakage: cpu-leakage@1a {
1242 logic_leakage: logic-leakage@1b {
1245 wafer_info: wafer-info@1c {
1250 pmucru: pmu-clock-controller@ff750000 {
1251 compatible = "rockchip,rk3399-pmucru";
1252 reg = <0x0 0xff750000 0x0 0x1000>;
1253 rockchip,grf = <&pmugrf>;
1256 assigned-clocks = <&pmucru PLL_PPLL>;
1257 assigned-clock-rates = <676000000>;
1260 cru: clock-controller@ff760000 {
1261 compatible = "rockchip,rk3399-cru";
1262 reg = <0x0 0xff760000 0x0 0x1000>;
1263 rockchip,grf = <&grf>;
1267 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1269 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1271 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1272 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1273 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1274 assigned-clock-rates =
1275 <594000000>, <800000000>,
1277 <150000000>, <75000000>,
1279 <100000000>, <100000000>,
1280 <50000000>, <600000000>,
1281 <100000000>, <50000000>;
1284 grf: syscon@ff770000 {
1285 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1286 reg = <0x0 0xff770000 0x0 0x10000>;
1287 #address-cells = <1>;
1290 io_domains: io-domains {
1291 compatible = "rockchip,rk3399-io-voltage-domain";
1292 status = "disabled";
1295 u2phy0: usb2-phy@e450 {
1296 compatible = "rockchip,rk3399-usb2phy";
1297 reg = <0xe450 0x10>;
1298 clocks = <&cru SCLK_USB2PHY0_REF>;
1299 clock-names = "phyclk";
1301 clock-output-names = "clk_usbphy0_480m";
1302 status = "disabled";
1304 u2phy0_host: host-port {
1306 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1307 interrupt-names = "linestate";
1308 status = "disabled";
1311 u2phy0_otg: otg-port {
1313 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1314 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1315 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1316 interrupt-names = "otg-bvalid", "otg-id",
1318 status = "disabled";
1322 u2phy1: usb2-phy@e460 {
1323 compatible = "rockchip,rk3399-usb2phy";
1324 reg = <0xe460 0x10>;
1325 clocks = <&cru SCLK_USB2PHY1_REF>;
1326 clock-names = "phyclk";
1328 clock-output-names = "clk_usbphy1_480m";
1329 status = "disabled";
1331 u2phy1_host: host-port {
1333 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1334 interrupt-names = "linestate";
1335 status = "disabled";
1338 u2phy1_otg: otg-port {
1340 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1341 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1342 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1343 interrupt-names = "otg-bvalid", "otg-id",
1345 status = "disabled";
1349 emmc_phy: phy@f780 {
1350 compatible = "rockchip,rk3399-emmc-phy";
1351 reg = <0xf780 0x24>;
1353 clock-names = "emmcclk";
1355 status = "disabled";
1358 pcie_phy: pcie-phy {
1359 compatible = "rockchip,rk3399-pcie-phy";
1360 clocks = <&cru SCLK_PCIEPHY_REF>;
1361 clock-names = "refclk";
1363 resets = <&cru SRST_PCIEPHY>;
1364 reset-names = "phy";
1365 status = "disabled";
1369 tcphy0: phy@ff7c0000 {
1370 compatible = "rockchip,rk3399-typec-phy";
1371 reg = <0x0 0xff7c0000 0x0 0x40000>;
1372 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1373 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1374 clock-names = "tcpdcore", "tcpdphy-ref";
1375 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1376 assigned-clock-rates = <50000000>;
1377 power-domains = <&power RK3399_PD_TCPD0>;
1378 resets = <&cru SRST_UPHY0>,
1379 <&cru SRST_UPHY0_PIPE_L00>,
1380 <&cru SRST_P_UPHY0_TCPHY>;
1381 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1382 rockchip,grf = <&grf>;
1383 rockchip,typec-conn-dir = <0xe580 0 16>;
1384 rockchip,usb3tousb2-en = <0xe580 3 19>;
1385 rockchip,external-psm = <0xe588 14 30>;
1386 rockchip,pipe-status = <0xe5c0 0 0>;
1387 status = "disabled";
1389 tcphy0_dp: dp-port {
1393 tcphy0_usb3: usb3-port {
1398 tcphy1: phy@ff800000 {
1399 compatible = "rockchip,rk3399-typec-phy";
1400 reg = <0x0 0xff800000 0x0 0x40000>;
1401 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1402 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1403 clock-names = "tcpdcore", "tcpdphy-ref";
1404 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1405 assigned-clock-rates = <50000000>;
1406 power-domains = <&power RK3399_PD_TCPD1>;
1407 resets = <&cru SRST_UPHY1>,
1408 <&cru SRST_UPHY1_PIPE_L00>,
1409 <&cru SRST_P_UPHY1_TCPHY>;
1410 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1411 rockchip,grf = <&grf>;
1412 rockchip,typec-conn-dir = <0xe58c 0 16>;
1413 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1414 rockchip,external-psm = <0xe594 14 30>;
1415 rockchip,pipe-status = <0xe5c0 16 16>;
1416 status = "disabled";
1418 tcphy1_dp: dp-port {
1422 tcphy1_usb3: usb3-port {
1428 compatible = "snps,dw-wdt";
1429 reg = <0x0 0xff848000 0x0 0x100>;
1430 clocks = <&cru PCLK_WDT>;
1431 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1434 rktimer: rktimer@ff850000 {
1435 compatible = "rockchip,rk3399-timer";
1436 reg = <0x0 0xff850000 0x0 0x1000>;
1437 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1438 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1439 clock-names = "pclk", "timer";
1442 spdif: spdif@ff870000 {
1443 compatible = "rockchip,rk3399-spdif";
1444 reg = <0x0 0xff870000 0x0 0x1000>;
1445 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1446 dmas = <&dmac_bus 7>;
1448 clock-names = "mclk", "hclk";
1449 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1450 pinctrl-names = "default";
1451 pinctrl-0 = <&spdif_bus>;
1452 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1453 status = "disabled";
1456 i2s0: i2s@ff880000 {
1457 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1458 reg = <0x0 0xff880000 0x0 0x1000>;
1459 rockchip,grf = <&grf>;
1460 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1461 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1462 dma-names = "tx", "rx";
1463 clock-names = "i2s_clk", "i2s_hclk";
1464 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1465 pinctrl-names = "default";
1466 pinctrl-0 = <&i2s0_8ch_bus>;
1467 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1468 status = "disabled";
1471 i2s1: i2s@ff890000 {
1472 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1473 reg = <0x0 0xff890000 0x0 0x1000>;
1474 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1475 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1476 dma-names = "tx", "rx";
1477 clock-names = "i2s_clk", "i2s_hclk";
1478 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1479 pinctrl-names = "default";
1480 pinctrl-0 = <&i2s1_2ch_bus>;
1481 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1482 status = "disabled";
1485 i2s2: i2s@ff8a0000 {
1486 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1487 reg = <0x0 0xff8a0000 0x0 0x1000>;
1488 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1489 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1490 dma-names = "tx", "rx";
1491 clock-names = "i2s_clk", "i2s_hclk";
1492 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1493 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1494 status = "disabled";
1497 vopl: vop@ff8f0000 {
1498 compatible = "rockchip,rk3399-vop-lit";
1499 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1500 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1501 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1502 assigned-clock-rates = <400000000>, <100000000>;
1503 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1504 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1505 iommus = <&vopl_mmu>;
1506 power-domains = <&power RK3399_PD_VOPL>;
1507 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1508 reset-names = "axi", "ahb", "dclk";
1509 status = "disabled";
1512 #address-cells = <1>;
1515 vopl_out_mipi: endpoint@0 {
1517 remote-endpoint = <&mipi_in_vopl>;
1520 vopl_out_edp: endpoint@1 {
1522 remote-endpoint = <&edp_in_vopl>;
1525 vopl_out_hdmi: endpoint@2 {
1527 remote-endpoint = <&hdmi_in_vopl>;
1532 vopl_mmu: iommu@ff8f3f00 {
1533 compatible = "rockchip,iommu";
1534 reg = <0x0 0xff8f3f00 0x0 0x100>;
1535 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1536 interrupt-names = "vopl_mmu";
1537 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1538 clock-names = "aclk", "hclk";
1539 power-domains = <&power RK3399_PD_VOPL>;
1541 status = "disabled";
1544 vopb: vop@ff900000 {
1545 compatible = "rockchip,rk3399-vop-big";
1546 reg = <0x0 0xff900000 0x0 0x3efc>;
1547 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1548 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1549 assigned-clock-rates = <400000000>, <100000000>;
1550 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1551 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1552 iommus = <&vopb_mmu>;
1553 power-domains = <&power RK3399_PD_VOPB>;
1554 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1555 reset-names = "axi", "ahb", "dclk";
1556 status = "disabled";
1559 #address-cells = <1>;
1562 vopb_out_edp: endpoint@0 {
1564 remote-endpoint = <&edp_in_vopb>;
1567 vopb_out_mipi: endpoint@1 {
1569 remote-endpoint = <&mipi_in_vopb>;
1572 vopb_out_hdmi: endpoint@2 {
1574 remote-endpoint = <&hdmi_in_vopb>;
1579 vopb_mmu: iommu@ff903f00 {
1580 compatible = "rockchip,iommu";
1581 reg = <0x0 0xff903f00 0x0 0x100>;
1582 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1583 interrupt-names = "vopb_mmu";
1584 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1585 clock-names = "aclk", "hclk";
1586 power-domains = <&power RK3399_PD_VOPB>;
1588 status = "disabled";
1591 isp0_mmu: iommu@ff914000 {
1592 compatible = "rockchip,iommu";
1593 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1594 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1595 interrupt-names = "isp0_mmu";
1597 rockchip,disable-mmu-reset;
1598 status = "disabled";
1601 isp1_mmu: iommu@ff924000 {
1602 compatible = "rockchip,iommu";
1603 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1604 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1605 interrupt-names = "isp1_mmu";
1607 rockchip,disable-mmu-reset;
1608 status = "disabled";
1611 hdmi: hdmi@ff940000 {
1612 compatible = "rockchip,rk3399-dw-hdmi";
1613 reg = <0x0 0xff940000 0x0 0x20000>;
1614 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1615 clocks = <&cru PCLK_HDMI_CTRL>,
1616 <&cru SCLK_HDMI_SFR>,
1618 <&cru PCLK_VIO_GRF>,
1619 <&cru SCLK_HDMI_CEC>;
1620 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1621 power-domains = <&power RK3399_PD_HDCP>;
1623 rockchip,grf = <&grf>;
1624 status = "disabled";
1628 #address-cells = <1>;
1631 hdmi_in_vopb: endpoint@0 {
1633 remote-endpoint = <&vopb_out_hdmi>;
1635 hdmi_in_vopl: endpoint@1 {
1637 remote-endpoint = <&vopl_out_hdmi>;
1643 mipi_dsi: mipi@ff960000 {
1644 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1645 reg = <0x0 0xff960000 0x0 0x8000>;
1646 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1647 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1648 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1649 clock-names = "ref", "pclk", "phy_cfg", "grf";
1650 power-domains = <&power RK3399_PD_VIO>;
1651 rockchip,grf = <&grf>;
1652 status = "disabled";
1656 #address-cells = <1>;
1659 mipi_in_vopb: endpoint@0 {
1661 remote-endpoint = <&vopb_out_mipi>;
1663 mipi_in_vopl: endpoint@1 {
1665 remote-endpoint = <&vopl_out_mipi>;
1672 compatible = "rockchip,rk3399-edp";
1673 reg = <0x0 0xff970000 0x0 0x8000>;
1674 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1675 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1676 clock-names = "dp", "pclk";
1677 pinctrl-names = "default";
1678 pinctrl-0 = <&edp_hpd>;
1679 power-domains = <&power RK3399_PD_EDP>;
1680 resets = <&cru SRST_P_EDP_CTRL>;
1682 rockchip,grf = <&grf>;
1683 status = "disabled";
1686 #address-cells = <1>;
1690 #address-cells = <1>;
1693 edp_in_vopb: endpoint@0 {
1695 remote-endpoint = <&vopb_out_edp>;
1698 edp_in_vopl: endpoint@1 {
1700 remote-endpoint = <&vopl_out_edp>;
1707 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1708 reg = <0x0 0xff9a0000 0x0 0x10000>;
1709 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1710 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1711 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1712 interrupt-names = "gpu", "job", "mmu";
1713 clocks = <&cru ACLK_GPU>;
1714 power-domains = <&power RK3399_PD_GPU>;
1715 status = "disabled";
1719 compatible = "rockchip,rk3399-pinctrl";
1720 rockchip,grf = <&grf>;
1721 rockchip,pmu = <&pmugrf>;
1722 #address-cells = <2>;
1726 gpio0: gpio0@ff720000 {
1727 compatible = "rockchip,gpio-bank";
1728 reg = <0x0 0xff720000 0x0 0x100>;
1729 clocks = <&pmucru PCLK_GPIO0_PMU>;
1730 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1733 #gpio-cells = <0x2>;
1735 interrupt-controller;
1736 #interrupt-cells = <0x2>;
1739 gpio1: gpio1@ff730000 {
1740 compatible = "rockchip,gpio-bank";
1741 reg = <0x0 0xff730000 0x0 0x100>;
1742 clocks = <&pmucru PCLK_GPIO1_PMU>;
1743 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1746 #gpio-cells = <0x2>;
1748 interrupt-controller;
1749 #interrupt-cells = <0x2>;
1752 gpio2: gpio2@ff780000 {
1753 compatible = "rockchip,gpio-bank";
1754 reg = <0x0 0xff780000 0x0 0x100>;
1755 clocks = <&cru PCLK_GPIO2>;
1756 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1759 #gpio-cells = <0x2>;
1761 interrupt-controller;
1762 #interrupt-cells = <0x2>;
1765 gpio3: gpio3@ff788000 {
1766 compatible = "rockchip,gpio-bank";
1767 reg = <0x0 0xff788000 0x0 0x100>;
1768 clocks = <&cru PCLK_GPIO3>;
1769 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1772 #gpio-cells = <0x2>;
1774 interrupt-controller;
1775 #interrupt-cells = <0x2>;
1778 gpio4: gpio4@ff790000 {
1779 compatible = "rockchip,gpio-bank";
1780 reg = <0x0 0xff790000 0x0 0x100>;
1781 clocks = <&cru PCLK_GPIO4>;
1782 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1785 #gpio-cells = <0x2>;
1787 interrupt-controller;
1788 #interrupt-cells = <0x2>;
1791 pcfg_pull_up: pcfg-pull-up {
1795 pcfg_pull_down: pcfg-pull-down {
1799 pcfg_pull_none: pcfg-pull-none {
1803 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1805 drive-strength = <12>;
1808 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1810 drive-strength = <8>;
1813 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1815 drive-strength = <4>;
1818 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1820 drive-strength = <2>;
1823 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1825 drive-strength = <12>;
1828 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1830 drive-strength = <13>;
1835 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1842 <4 23 RK_FUNC_2 &pcfg_pull_none>;
1847 rgmii_pins: rgmii-pins {
1850 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1852 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1854 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1856 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1858 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1860 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1862 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1864 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1866 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1868 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1870 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1872 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1874 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1876 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1878 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1881 rmii_pins: rmii-pins {
1884 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1886 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1888 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1890 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1892 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1894 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1896 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1898 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1900 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1902 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1907 i2c0_xfer: i2c0-xfer {
1909 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1910 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1915 i2c1_xfer: i2c1-xfer {
1917 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1918 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1923 i2c2_xfer: i2c2-xfer {
1925 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1926 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1931 i2c3_xfer: i2c3-xfer {
1933 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1934 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1939 i2c4_xfer: i2c4-xfer {
1941 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1942 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1947 i2c5_xfer: i2c5-xfer {
1949 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1950 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1955 i2c6_xfer: i2c6-xfer {
1957 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1958 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1963 i2c7_xfer: i2c7-xfer {
1965 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1966 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1971 i2c8_xfer: i2c8-xfer {
1973 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1974 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1979 i2s0_8ch_bus: i2s0-8ch-bus {
1981 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1982 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1983 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1984 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1985 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1986 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1987 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1988 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1989 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1994 i2s1_2ch_bus: i2s1-2ch-bus {
1996 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1997 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1998 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1999 <4 6 RK_FUNC_1 &pcfg_pull_none>,
2000 <4 7 RK_FUNC_1 &pcfg_pull_none>;
2005 sdio0_bus1: sdio0-bus1 {
2007 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
2010 sdio0_bus4: sdio0-bus4 {
2012 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
2013 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
2014 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
2015 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
2018 sdio0_cmd: sdio0-cmd {
2020 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
2023 sdio0_clk: sdio0-clk {
2025 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
2028 sdio0_cd: sdio0-cd {
2030 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
2033 sdio0_pwr: sdio0-pwr {
2035 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
2038 sdio0_bkpwr: sdio0-bkpwr {
2040 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
2043 sdio0_wp: sdio0-wp {
2045 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
2048 sdio0_int: sdio0-int {
2050 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
2055 sdmmc_bus1: sdmmc-bus1 {
2057 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2060 sdmmc_bus4: sdmmc-bus4 {
2062 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
2063 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
2064 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
2065 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
2068 sdmmc_clk: sdmmc-clk {
2070 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
2073 sdmmc_cmd: sdmmc-cmd {
2075 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
2078 sdmmc_cd: sdmmc-cd {
2080 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
2083 sdmmc_wp: sdmmc-wp {
2085 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2090 ap_pwroff: ap-pwroff {
2091 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
2094 ddrio_pwroff: ddrio-pwroff {
2095 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
2100 spdif_bus: spdif-bus {
2102 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2105 spdif_bus_1: spdif-bus-1 {
2107 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2112 spi0_clk: spi0-clk {
2114 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2116 spi0_cs0: spi0-cs0 {
2118 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2120 spi0_cs1: spi0-cs1 {
2122 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2126 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2130 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2135 spi1_clk: spi1-clk {
2137 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2139 spi1_cs0: spi1-cs0 {
2141 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2145 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2149 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2154 spi2_clk: spi2-clk {
2156 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2158 spi2_cs0: spi2-cs0 {
2160 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2164 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2168 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2173 spi3_clk: spi3-clk {
2175 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2177 spi3_cs0: spi3-cs0 {
2179 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2183 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2187 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2192 spi4_clk: spi4-clk {
2194 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2196 spi4_cs0: spi4-cs0 {
2198 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2202 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2206 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2211 spi5_clk: spi5-clk {
2213 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2215 spi5_cs0: spi5-cs0 {
2217 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2221 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2225 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2230 otp_gpio: otp-gpio {
2231 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2235 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2240 uart0_xfer: uart0-xfer {
2242 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2243 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2246 uart0_cts: uart0-cts {
2248 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2251 uart0_rts: uart0-rts {
2253 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2258 uart1_xfer: uart1-xfer {
2260 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2261 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2266 uart2a_xfer: uart2a-xfer {
2268 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2269 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2274 uart2b_xfer: uart2b-xfer {
2276 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2277 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2282 uart2c_xfer: uart2c-xfer {
2284 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2285 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2290 uart3_xfer: uart3-xfer {
2292 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2293 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2296 uart3_cts: uart3-cts {
2298 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2301 uart3_rts: uart3-rts {
2303 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2308 uart4_xfer: uart4-xfer {
2310 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2311 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2316 uarthdcp_xfer: uarthdcp-xfer {
2318 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2319 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2324 pwm0_pin: pwm0-pin {
2326 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2329 vop0_pwm_pin: vop0-pwm-pin {
2331 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2336 pwm1_pin: pwm1-pin {
2338 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2341 vop1_pwm_pin: vop1-pwm-pin {
2343 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2348 pwm2_pin: pwm2-pin {
2350 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2355 pwm3a_pin: pwm3a-pin {
2357 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2362 pwm3b_pin: pwm3b-pin {
2364 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2369 hdmi_i2c_xfer: hdmi-i2c-xfer {
2371 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
2372 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2375 hdmi_cec: hdmi-cec {
2377 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
2382 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2384 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2387 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2389 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;