arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 ethernet0 = &gmac;
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         cpus {
  77                 #address-cells = <2>;
  78                 #size-cells = <0>;
  79
  80                 cpu-map {
  81                         cluster0 {
  82                                 core0 {
  83                                         cpu = <&cpu_l0>;
  84                                 };
  85                                 core1 {
  86                                         cpu = <&cpu_l1>;
  87                                 };
  88                                 core2 {
  89                                         cpu = <&cpu_l2>;
  90                                 };
  91                                 core3 {
  92                                         cpu = <&cpu_l3>;
  93                                 };
  94                         };
  95
  96                         cluster1 {
  97                                 core0 {
  98                                         cpu = <&cpu_b0>;
  99                                 };
 100                                 core1 {
 101                                         cpu = <&cpu_b1>;
 102                                 };
 103                         };
 104                 };
 105
 106                 cpu_l0: cpu@0 {
 107                         device_type = "cpu";
 108                         compatible = "arm,cortex-a53", "arm,armv8";
 109                         reg = <0x0 0x0>;
 110                         enable-method = "psci";
 111                         #cooling-cells = <2>; /* min followed by max */
 112                         clocks = <&cru ARMCLKL>;
 113                         dynamic-power-coefficient = <100>;
 114                 };
 115
 116                 cpu_l1: cpu@1 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a53", "arm,armv8";
 119                         reg = <0x0 0x1>;
 120                         enable-method = "psci";
 121                         clocks = <&cru ARMCLKL>;
 122                         dynamic-power-coefficient = <100>;
 123                 };
 124
 125                 cpu_l2: cpu@2 {
 126                         device_type = "cpu";
 127                         compatible = "arm,cortex-a53", "arm,armv8";
 128                         reg = <0x0 0x2>;
 129                         enable-method = "psci";
 130                         clocks = <&cru ARMCLKL>;
 131                         dynamic-power-coefficient = <100>;
 132                 };
 133
 134                 cpu_l3: cpu@3 {
 135                         device_type = "cpu";
 136                         compatible = "arm,cortex-a53", "arm,armv8";
 137                         reg = <0x0 0x3>;
 138                         enable-method = "psci";
 139                         clocks = <&cru ARMCLKL>;
 140                         dynamic-power-coefficient = <100>;
 141                 };
 142
 143                 cpu_b0: cpu@100 {
 144                         device_type = "cpu";
 145                         compatible = "arm,cortex-a72", "arm,armv8";
 146                         reg = <0x0 0x100>;
 147                         enable-method = "psci";
 148                         #cooling-cells = <2>; /* min followed by max */
 149                         clocks = <&cru ARMCLKB>;
 150                         dynamic-power-coefficient = <436>;
 151                 };
 152
 153                 cpu_b1: cpu@101 {
 154                         device_type = "cpu";
 155                         compatible = "arm,cortex-a72", "arm,armv8";
 156                         reg = <0x0 0x101>;
 157                         enable-method = "psci";
 158                         clocks = <&cru ARMCLKB>;
 159                         dynamic-power-coefficient = <436>;
 160                 };
 161         };
 162
 163         display-subsystem {
 164                 compatible = "rockchip,display-subsystem";
 165                 ports = <&vopl_out>, <&vopb_out>;
 166         };
 167
 168         pmu_a53 {
 169                 compatible = "arm,cortex-a53-pmu";
 170                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 171         };
 172
 173         pmu_a72 {
 174                 compatible = "arm,cortex-a72-pmu";
 175                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 176         };
 177
 178         psci {
 179                 compatible = "arm,psci-1.0";
 180                 method = "smc";
 181         };
 182
 183         timer {
 184                 compatible = "arm,armv8-timer";
 185                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 186                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 187                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 188                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 189                 arm,no-tick-in-suspend;
 190         };
 191
 192         xin24m: xin24m {
 193                 compatible = "fixed-clock";
 194                 clock-frequency = <24000000>;
 195                 clock-output-names = "xin24m";
 196                 #clock-cells = <0>;
 197         };
 198
 199         amba {
 200                 compatible = "simple-bus";
 201                 #address-cells = <2>;
 202                 #size-cells = <2>;
 203                 ranges;
 204
 205                 dmac_bus: dma-controller@ff6d0000 {
 206                         compatible = "arm,pl330", "arm,primecell";
 207                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 208                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 209                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 210                         #dma-cells = <1>;
 211                         clocks = <&cru ACLK_DMAC0_PERILP>;
 212                         clock-names = "apb_pclk";
 213                 };
 214
 215                 dmac_peri: dma-controller@ff6e0000 {
 216                         compatible = "arm,pl330", "arm,primecell";
 217                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 218                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 219                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 220                         #dma-cells = <1>;
 221                         clocks = <&cru ACLK_DMAC1_PERILP>;
 222                         clock-names = "apb_pclk";
 223                 };
 224         };
 225
 226         pcie0: pcie@f8000000 {
 227                 compatible = "rockchip,rk3399-pcie";
 228                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 229                       <0x0 0xfd000000 0x0 0x1000000>;
 230                 reg-names = "axi-base", "apb-base";
 231                 #address-cells = <3>;
 232                 #size-cells = <2>;
 233                 #interrupt-cells = <1>;
 234                 aspm-no-l0s;
 235                 bus-range = <0x0 0x1f>;
 236                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 237                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 238                 clock-names = "aclk", "aclk-perf",
 239                               "hclk", "pm";
 240                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 241                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 242                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 243                 interrupt-names = "sys", "legacy", "client";
 244                 interrupt-map-mask = <0 0 0 7>;
 245                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 246                                 <0 0 0 2 &pcie0_intc 1>,
 247                                 <0 0 0 3 &pcie0_intc 2>,
 248                                 <0 0 0 4 &pcie0_intc 3>;
 249                 linux,pci-domain = <0>;
 250                 max-link-speed = <1>;
 251                 msi-map = <0x0 &its 0x0 0x1000>;
 252                 phys = <&pcie_phy 0>, <&pcie_phy 1>,
 253                        <&pcie_phy 2>, <&pcie_phy 3>;
 254                 phy-names = "pcie-phy-0", "pcie-phy-1",
 255                             "pcie-phy-2", "pcie-phy-3";
 256                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
 257                           0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
 258                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 259                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
 260                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
 261                          <&cru SRST_A_PCIE>;
 262                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
 263                               "pm", "pclk", "aclk";
 264                 status = "disabled";
 265
 266                 pcie0_intc: interrupt-controller {
 267                         interrupt-controller;
 268                         #address-cells = <0>;
 269                         #interrupt-cells = <1>;
 270                 };
 271         };
 272
 273         gmac: ethernet@fe300000 {
 274                 compatible = "rockchip,rk3399-gmac";
 275                 reg = <0x0 0xfe300000 0x0 0x10000>;
 276                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 277                 interrupt-names = "macirq";
 278                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 279                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 280                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 281                          <&cru PCLK_GMAC>;
 282                 clock-names = "stmmaceth", "mac_clk_rx",
 283                               "mac_clk_tx", "clk_mac_ref",
 284                               "clk_mac_refout", "aclk_mac",
 285                               "pclk_mac";
 286                 power-domains = <&power RK3399_PD_GMAC>;
 287                 resets = <&cru SRST_A_GMAC>;
 288                 reset-names = "stmmaceth";
 289                 rockchip,grf = <&grf>;
 290                 status = "disabled";
 291         };
 292
 293         sdio0: dwmmc@fe310000 {
 294                 compatible = "rockchip,rk3399-dw-mshc",
 295                              "rockchip,rk3288-dw-mshc";
 296                 reg = <0x0 0xfe310000 0x0 0x4000>;
 297                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 298                 max-frequency = <150000000>;
 299                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 300                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 301                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 302                 fifo-depth = <0x100>;
 303                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 304                 resets = <&cru SRST_SDIO0>;
 305                 reset-names = "reset";
 306                 status = "disabled";
 307         };
 308
 309         sdmmc: dwmmc@fe320000 {
 310                 compatible = "rockchip,rk3399-dw-mshc",
 311                              "rockchip,rk3288-dw-mshc";
 312                 reg = <0x0 0xfe320000 0x0 0x4000>;
 313                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 314                 max-frequency = <150000000>;
 315                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 316                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 317                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 318                 fifo-depth = <0x100>;
 319                 power-domains = <&power RK3399_PD_SD>;
 320                 resets = <&cru SRST_SDMMC>;
 321                 reset-names = "reset";
 322                 status = "disabled";
 323         };
 324
 325         sdhci: sdhci@fe330000 {
 326                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 327                 reg = <0x0 0xfe330000 0x0 0x10000>;
 328                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 329                 arasan,soc-ctl-syscon = <&grf>;
 330                 assigned-clocks = <&cru SCLK_EMMC>;
 331                 assigned-clock-rates = <200000000>;
 332                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 333                 clock-names = "clk_xin", "clk_ahb";
 334                 clock-output-names = "emmc_cardclock";
 335                 #clock-cells = <0>;
 336                 phys = <&emmc_phy>;
 337                 phy-names = "phy_arasan";
 338                 power-domains = <&power RK3399_PD_EMMC>;
 339                 status = "disabled";
 340         };
 341
 342         usb_host0_ehci: usb@fe380000 {
 343                 compatible = "generic-ehci";
 344                 reg = <0x0 0xfe380000 0x0 0x20000>;
 345                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 346                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 347                          <&u2phy0>;
 348                 clock-names = "usbhost", "arbiter",
 349                               "utmi";
 350                 phys = <&u2phy0_host>;
 351                 phy-names = "usb";
 352                 status = "disabled";
 353         };
 354
 355         usb_host0_ohci: usb@fe3a0000 {
 356                 compatible = "generic-ohci";
 357                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 358                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 359                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 360                          <&u2phy0>;
 361                 clock-names = "usbhost", "arbiter",
 362                               "utmi";
 363                 phys = <&u2phy0_host>;
 364                 phy-names = "usb";
 365                 status = "disabled";
 366         };
 367
 368         usb_host1_ehci: usb@fe3c0000 {
 369                 compatible = "generic-ehci";
 370                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 371                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 372                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 373                          <&u2phy1>;
 374                 clock-names = "usbhost", "arbiter",
 375                               "utmi";
 376                 phys = <&u2phy1_host>;
 377                 phy-names = "usb";
 378                 status = "disabled";
 379         };
 380
 381         usb_host1_ohci: usb@fe3e0000 {
 382                 compatible = "generic-ohci";
 383                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 384                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 385                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 386                          <&u2phy1>;
 387                 clock-names = "usbhost", "arbiter",
 388                               "utmi";
 389                 phys = <&u2phy1_host>;
 390                 phy-names = "usb";
 391                 status = "disabled";
 392         };
 393
 394         usbdrd3_0: usb@fe800000 {
 395                 compatible = "rockchip,rk3399-dwc3";
 396                 #address-cells = <2>;
 397                 #size-cells = <2>;
 398                 ranges;
 399                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 400                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 401                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 402                 clock-names = "ref_clk", "suspend_clk",
 403                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 404                               "aclk_usb3", "grf_clk";
 405                 resets = <&cru SRST_A_USB3_OTG0>;
 406                 reset-names = "usb3-otg";
 407                 status = "disabled";
 408
 409                 usbdrd_dwc3_0: dwc3 {
 410                         compatible = "snps,dwc3";
 411                         reg = <0x0 0xfe800000 0x0 0x100000>;
 412                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 413                         dr_mode = "otg";
 414                         phys = <&u2phy0_otg>;
 415                         phy-names = "usb2-phy";
 416                         phy_type = "utmi_wide";
 417                         snps,dis_enblslpm_quirk;
 418                         snps,dis-u2-freeclk-exists-quirk;
 419                         snps,dis_u2_susphy_quirk;
 420                         snps,dis-del-phy-power-chg-quirk;
 421                         snps,dis-tx-ipgap-linecheck-quirk;
 422                         power-domains = <&power RK3399_PD_USB3>;
 423                         status = "disabled";
 424                 };
 425         };
 426
 427         usbdrd3_1: usb@fe900000 {
 428                 compatible = "rockchip,rk3399-dwc3";
 429                 #address-cells = <2>;
 430                 #size-cells = <2>;
 431                 ranges;
 432                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 433                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 434                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 435                 clock-names = "ref_clk", "suspend_clk",
 436                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 437                               "aclk_usb3", "grf_clk";
 438                 resets = <&cru SRST_A_USB3_OTG1>;
 439                 reset-names = "usb3-otg";
 440                 status = "disabled";
 441
 442                 usbdrd_dwc3_1: dwc3 {
 443                         compatible = "snps,dwc3";
 444                         reg = <0x0 0xfe900000 0x0 0x100000>;
 445                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 446                         dr_mode = "otg";
 447                         phys = <&u2phy1_otg>;
 448                         phy-names = "usb2-phy";
 449                         phy_type = "utmi_wide";
 450                         snps,dis_enblslpm_quirk;
 451                         snps,dis-u2-freeclk-exists-quirk;
 452                         snps,dis_u2_susphy_quirk;
 453                         snps,dis-del-phy-power-chg-quirk;
 454                         snps,dis-tx-ipgap-linecheck-quirk;
 455                         power-domains = <&power RK3399_PD_USB3>;
 456                         status = "disabled";
 457                 };
 458         };
 459
 460         cdn_dp: dp@fec00000 {
 461                 compatible = "rockchip,rk3399-cdn-dp";
 462                 reg = <0x0 0xfec00000 0x0 0x100000>;
 463                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 464                 assigned-clocks = <&cru SCLK_DP_CORE>;
 465                 assigned-clock-rates = <100000000>;
 466                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 467                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 468                 clock-names = "core-clk", "pclk", "spdif", "grf";
 469                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 470                 power-domains = <&power RK3399_PD_HDCP>;
 471                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 472                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 473                 reset-names = "spdif", "dptx", "apb", "core";
 474                 rockchip,grf = <&grf>;
 475                 #sound-dai-cells = <1>;
 476                 status = "disabled";
 477
 478                 ports {
 479                         dp_in: port {
 480                                 #address-cells = <1>;
 481                                 #size-cells = <0>;
 482
 483                                 dp_in_vopb: endpoint@0 {
 484                                         reg = <0>;
 485                                         remote-endpoint = <&vopb_out_dp>;
 486                                 };
 487
 488                                 dp_in_vopl: endpoint@1 {
 489                                         reg = <1>;
 490                                         remote-endpoint = <&vopl_out_dp>;
 491                                 };
 492                         };
 493                 };
 494         };
 495
 496         gic: interrupt-controller@fee00000 {
 497                 compatible = "arm,gic-v3";
 498                 #interrupt-cells = <4>;
 499                 #address-cells = <2>;
 500                 #size-cells = <2>;
 501                 ranges;
 502                 interrupt-controller;
 503
 504                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 505                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 506                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 507                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 508                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 509                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 510                 its: interrupt-controller@fee20000 {
 511                         compatible = "arm,gic-v3-its";
 512                         msi-controller;
 513                         reg = <0x0 0xfee20000 0x0 0x20000>;
 514                 };
 515
 516                 ppi-partitions {
 517                         ppi_cluster0: interrupt-partition-0 {
 518                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 519                         };
 520
 521                         ppi_cluster1: interrupt-partition-1 {
 522                                 affinity = <&cpu_b0 &cpu_b1>;
 523                         };
 524                 };
 525         };
 526
 527         saradc: saradc@ff100000 {
 528                 compatible = "rockchip,rk3399-saradc";
 529                 reg = <0x0 0xff100000 0x0 0x100>;
 530                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 531                 #io-channel-cells = <1>;
 532                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 533                 clock-names = "saradc", "apb_pclk";
 534                 resets = <&cru SRST_P_SARADC>;
 535                 reset-names = "saradc-apb";
 536                 status = "disabled";
 537         };
 538
 539         i2c1: i2c@ff110000 {
 540                 compatible = "rockchip,rk3399-i2c";
 541                 reg = <0x0 0xff110000 0x0 0x1000>;
 542                 assigned-clocks = <&cru SCLK_I2C1>;
 543                 assigned-clock-rates = <200000000>;
 544                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 545                 clock-names = "i2c", "pclk";
 546                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 547                 pinctrl-names = "default";
 548                 pinctrl-0 = <&i2c1_xfer>;
 549                 #address-cells = <1>;
 550                 #size-cells = <0>;
 551                 status = "disabled";
 552         };
 553
 554         i2c2: i2c@ff120000 {
 555                 compatible = "rockchip,rk3399-i2c";
 556                 reg = <0x0 0xff120000 0x0 0x1000>;
 557                 assigned-clocks = <&cru SCLK_I2C2>;
 558                 assigned-clock-rates = <200000000>;
 559                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 560                 clock-names = "i2c", "pclk";
 561                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 562                 pinctrl-names = "default";
 563                 pinctrl-0 = <&i2c2_xfer>;
 564                 #address-cells = <1>;
 565                 #size-cells = <0>;
 566                 status = "disabled";
 567         };
 568
 569         i2c3: i2c@ff130000 {
 570                 compatible = "rockchip,rk3399-i2c";
 571                 reg = <0x0 0xff130000 0x0 0x1000>;
 572                 assigned-clocks = <&cru SCLK_I2C3>;
 573                 assigned-clock-rates = <200000000>;
 574                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 575                 clock-names = "i2c", "pclk";
 576                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 577                 pinctrl-names = "default";
 578                 pinctrl-0 = <&i2c3_xfer>;
 579                 #address-cells = <1>;
 580                 #size-cells = <0>;
 581                 status = "disabled";
 582         };
 583
 584         i2c5: i2c@ff140000 {
 585                 compatible = "rockchip,rk3399-i2c";
 586                 reg = <0x0 0xff140000 0x0 0x1000>;
 587                 assigned-clocks = <&cru SCLK_I2C5>;
 588                 assigned-clock-rates = <200000000>;
 589                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 590                 clock-names = "i2c", "pclk";
 591                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 592                 pinctrl-names = "default";
 593                 pinctrl-0 = <&i2c5_xfer>;
 594                 #address-cells = <1>;
 595                 #size-cells = <0>;
 596                 status = "disabled";
 597         };
 598
 599         i2c6: i2c@ff150000 {
 600                 compatible = "rockchip,rk3399-i2c";
 601                 reg = <0x0 0xff150000 0x0 0x1000>;
 602                 assigned-clocks = <&cru SCLK_I2C6>;
 603                 assigned-clock-rates = <200000000>;
 604                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 605                 clock-names = "i2c", "pclk";
 606                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 607                 pinctrl-names = "default";
 608                 pinctrl-0 = <&i2c6_xfer>;
 609                 #address-cells = <1>;
 610                 #size-cells = <0>;
 611                 status = "disabled";
 612         };
 613
 614         i2c7: i2c@ff160000 {
 615                 compatible = "rockchip,rk3399-i2c";
 616                 reg = <0x0 0xff160000 0x0 0x1000>;
 617                 assigned-clocks = <&cru SCLK_I2C7>;
 618                 assigned-clock-rates = <200000000>;
 619                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 620                 clock-names = "i2c", "pclk";
 621                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 622                 pinctrl-names = "default";
 623                 pinctrl-0 = <&i2c7_xfer>;
 624                 #address-cells = <1>;
 625                 #size-cells = <0>;
 626                 status = "disabled";
 627         };
 628
 629         uart0: serial@ff180000 {
 630                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 631                 reg = <0x0 0xff180000 0x0 0x100>;
 632                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 633                 clock-names = "baudclk", "apb_pclk";
 634                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 635                 reg-shift = <2>;
 636                 reg-io-width = <4>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&uart0_xfer>;
 639                 status = "disabled";
 640         };
 641
 642         uart1: serial@ff190000 {
 643                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 644                 reg = <0x0 0xff190000 0x0 0x100>;
 645                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 646                 clock-names = "baudclk", "apb_pclk";
 647                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 648                 reg-shift = <2>;
 649                 reg-io-width = <4>;
 650                 pinctrl-names = "default";
 651                 pinctrl-0 = <&uart1_xfer>;
 652                 status = "disabled";
 653         };
 654
 655         uart2: serial@ff1a0000 {
 656                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 657                 reg = <0x0 0xff1a0000 0x0 0x100>;
 658                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 659                 clock-names = "baudclk", "apb_pclk";
 660                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 661                 reg-shift = <2>;
 662                 reg-io-width = <4>;
 663                 pinctrl-names = "default";
 664                 pinctrl-0 = <&uart2c_xfer>;
 665                 status = "disabled";
 666         };
 667
 668         uart3: serial@ff1b0000 {
 669                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 670                 reg = <0x0 0xff1b0000 0x0 0x100>;
 671                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 672                 clock-names = "baudclk", "apb_pclk";
 673                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 674                 reg-shift = <2>;
 675                 reg-io-width = <4>;
 676                 pinctrl-names = "default";
 677                 pinctrl-0 = <&uart3_xfer>;
 678                 status = "disabled";
 679         };
 680
 681         spi0: spi@ff1c0000 {
 682                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 683                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 684                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 685                 clock-names = "spiclk", "apb_pclk";
 686                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 687                 pinctrl-names = "default";
 688                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 689                 #address-cells = <1>;
 690                 #size-cells = <0>;
 691                 status = "disabled";
 692         };
 693
 694         spi1: spi@ff1d0000 {
 695                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 696                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 697                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 698                 clock-names = "spiclk", "apb_pclk";
 699                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 700                 pinctrl-names = "default";
 701                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 702                 #address-cells = <1>;
 703                 #size-cells = <0>;
 704                 status = "disabled";
 705         };
 706
 707         spi2: spi@ff1e0000 {
 708                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 709                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 710                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 711                 clock-names = "spiclk", "apb_pclk";
 712                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 713                 pinctrl-names = "default";
 714                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 715                 #address-cells = <1>;
 716                 #size-cells = <0>;
 717                 status = "disabled";
 718         };
 719
 720         spi4: spi@ff1f0000 {
 721                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 722                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 723                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 724                 clock-names = "spiclk", "apb_pclk";
 725                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 726                 pinctrl-names = "default";
 727                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 728                 #address-cells = <1>;
 729                 #size-cells = <0>;
 730                 status = "disabled";
 731         };
 732
 733         spi5: spi@ff200000 {
 734                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 735                 reg = <0x0 0xff200000 0x0 0x1000>;
 736                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 737                 clock-names = "spiclk", "apb_pclk";
 738                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 739                 pinctrl-names = "default";
 740                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 741                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 742                 #address-cells = <1>;
 743                 #size-cells = <0>;
 744                 status = "disabled";
 745         };
 746
 747         thermal_zones: thermal-zones {
 748                 cpu_thermal: cpu {
 749                         polling-delay-passive = <100>;
 750                         polling-delay = <1000>;
 751
 752                         thermal-sensors = <&tsadc 0>;
 753
 754                         trips {
 755                                 cpu_alert0: cpu_alert0 {
 756                                         temperature = <70000>;
 757                                         hysteresis = <2000>;
 758                                         type = "passive";
 759                                 };
 760                                 cpu_alert1: cpu_alert1 {
 761                                         temperature = <75000>;
 762                                         hysteresis = <2000>;
 763                                         type = "passive";
 764                                 };
 765                                 cpu_crit: cpu_crit {
 766                                         temperature = <95000>;
 767                                         hysteresis = <2000>;
 768                                         type = "critical";
 769                                 };
 770                         };
 771
 772                         cooling-maps {
 773                                 map0 {
 774                                         trip = <&cpu_alert0>;
 775                                         cooling-device =
 776                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 777                                 };
 778                                 map1 {
 779                                         trip = <&cpu_alert1>;
 780                                         cooling-device =
 781                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 782                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 783                                 };
 784                         };
 785                 };
 786
 787                 gpu_thermal: gpu {
 788                         polling-delay-passive = <100>;
 789                         polling-delay = <1000>;
 790
 791                         thermal-sensors = <&tsadc 1>;
 792
 793                         trips {
 794                                 gpu_alert0: gpu_alert0 {
 795                                         temperature = <75000>;
 796                                         hysteresis = <2000>;
 797                                         type = "passive";
 798                                 };
 799                                 gpu_crit: gpu_crit {
 800                                         temperature = <95000>;
 801                                         hysteresis = <2000>;
 802                                         type = "critical";
 803                                 };
 804                         };
 805
 806                         cooling-maps {
 807                                 map0 {
 808                                         trip = <&gpu_alert0>;
 809                                         cooling-device =
 810                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 811                                 };
 812                         };
 813                 };
 814         };
 815
 816         tsadc: tsadc@ff260000 {
 817                 compatible = "rockchip,rk3399-tsadc";
 818                 reg = <0x0 0xff260000 0x0 0x100>;
 819                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 820                 assigned-clocks = <&cru SCLK_TSADC>;
 821                 assigned-clock-rates = <750000>;
 822                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 823                 clock-names = "tsadc", "apb_pclk";
 824                 resets = <&cru SRST_TSADC>;
 825                 reset-names = "tsadc-apb";
 826                 rockchip,grf = <&grf>;
 827                 rockchip,hw-tshut-temp = <95000>;
 828                 pinctrl-names = "init", "default", "sleep";
 829                 pinctrl-0 = <&otp_gpio>;
 830                 pinctrl-1 = <&otp_out>;
 831                 pinctrl-2 = <&otp_gpio>;
 832                 #thermal-sensor-cells = <1>;
 833                 status = "disabled";
 834         };
 835
 836         qos_emmc: qos@ffa58000 {
 837                 compatible = "syscon";
 838                 reg = <0x0 0xffa58000 0x0 0x20>;
 839         };
 840
 841         qos_gmac: qos@ffa5c000 {
 842                 compatible = "syscon";
 843                 reg = <0x0 0xffa5c000 0x0 0x20>;
 844         };
 845
 846         qos_pcie: qos@ffa60080 {
 847                 compatible = "syscon";
 848                 reg = <0x0 0xffa60080 0x0 0x20>;
 849         };
 850
 851         qos_usb_host0: qos@ffa60100 {
 852                 compatible = "syscon";
 853                 reg = <0x0 0xffa60100 0x0 0x20>;
 854         };
 855
 856         qos_usb_host1: qos@ffa60180 {
 857                 compatible = "syscon";
 858                 reg = <0x0 0xffa60180 0x0 0x20>;
 859         };
 860
 861         qos_usb_otg0: qos@ffa70000 {
 862                 compatible = "syscon";
 863                 reg = <0x0 0xffa70000 0x0 0x20>;
 864         };
 865
 866         qos_usb_otg1: qos@ffa70080 {
 867                 compatible = "syscon";
 868                 reg = <0x0 0xffa70080 0x0 0x20>;
 869         };
 870
 871         qos_sd: qos@ffa74000 {
 872                 compatible = "syscon";
 873                 reg = <0x0 0xffa74000 0x0 0x20>;
 874         };
 875
 876         qos_sdioaudio: qos@ffa76000 {
 877                 compatible = "syscon";
 878                 reg = <0x0 0xffa76000 0x0 0x20>;
 879         };
 880
 881         qos_hdcp: qos@ffa90000 {
 882                 compatible = "syscon";
 883                 reg = <0x0 0xffa90000 0x0 0x20>;
 884         };
 885
 886         qos_iep: qos@ffa98000 {
 887                 compatible = "syscon";
 888                 reg = <0x0 0xffa98000 0x0 0x20>;
 889         };
 890
 891         qos_isp0_m0: qos@ffaa0000 {
 892                 compatible = "syscon";
 893                 reg = <0x0 0xffaa0000 0x0 0x20>;
 894         };
 895
 896         qos_isp0_m1: qos@ffaa0080 {
 897                 compatible = "syscon";
 898                 reg = <0x0 0xffaa0080 0x0 0x20>;
 899         };
 900
 901         qos_isp1_m0: qos@ffaa8000 {
 902                 compatible = "syscon";
 903                 reg = <0x0 0xffaa8000 0x0 0x20>;
 904         };
 905
 906         qos_isp1_m1: qos@ffaa8080 {
 907                 compatible = "syscon";
 908                 reg = <0x0 0xffaa8080 0x0 0x20>;
 909         };
 910
 911         qos_rga_r: qos@ffab0000 {
 912                 compatible = "syscon";
 913                 reg = <0x0 0xffab0000 0x0 0x20>;
 914         };
 915
 916         qos_rga_w: qos@ffab0080 {
 917                 compatible = "syscon";
 918                 reg = <0x0 0xffab0080 0x0 0x20>;
 919         };
 920
 921         qos_video_m0: qos@ffab8000 {
 922                 compatible = "syscon";
 923                 reg = <0x0 0xffab8000 0x0 0x20>;
 924         };
 925
 926         qos_video_m1_r: qos@ffac0000 {
 927                 compatible = "syscon";
 928                 reg = <0x0 0xffac0000 0x0 0x20>;
 929         };
 930
 931         qos_video_m1_w: qos@ffac0080 {
 932                 compatible = "syscon";
 933                 reg = <0x0 0xffac0080 0x0 0x20>;
 934         };
 935
 936         qos_vop_big_r: qos@ffac8000 {
 937                 compatible = "syscon";
 938                 reg = <0x0 0xffac8000 0x0 0x20>;
 939         };
 940
 941         qos_vop_big_w: qos@ffac8080 {
 942                 compatible = "syscon";
 943                 reg = <0x0 0xffac8080 0x0 0x20>;
 944         };
 945
 946         qos_vop_little: qos@ffad0000 {
 947                 compatible = "syscon";
 948                 reg = <0x0 0xffad0000 0x0 0x20>;
 949         };
 950
 951         qos_perihp: qos@ffad8080 {
 952                 compatible = "syscon";
 953                 reg = <0x0 0xffad8080 0x0 0x20>;
 954         };
 955
 956         qos_gpu: qos@ffae0000 {
 957                 compatible = "syscon";
 958                 reg = <0x0 0xffae0000 0x0 0x20>;
 959         };
 960
 961         pmu: power-management@ff310000 {
 962                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 963                 reg = <0x0 0xff310000 0x0 0x1000>;
 964
 965                 /*
 966                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 967                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 968                  * Some of the power domains are grouped together for every
 969                  * voltage domain.
 970                  * The detail contents as below.
 971                  */
 972                 power: power-controller {
 973                         compatible = "rockchip,rk3399-power-controller";
 974                         #power-domain-cells = <1>;
 975                         #address-cells = <1>;
 976                         #size-cells = <0>;
 977
 978                         /* These power domains are grouped by VD_CENTER */
 979                         pd_iep@RK3399_PD_IEP {
 980                                 reg = <RK3399_PD_IEP>;
 981                                 clocks = <&cru ACLK_IEP>,
 982                                          <&cru HCLK_IEP>;
 983                                 pm_qos = <&qos_iep>;
 984                         };
 985                         pd_rga@RK3399_PD_RGA {
 986                                 reg = <RK3399_PD_RGA>;
 987                                 clocks = <&cru ACLK_RGA>,
 988                                          <&cru HCLK_RGA>;
 989                                 pm_qos = <&qos_rga_r>,
 990                                          <&qos_rga_w>;
 991                         };
 992                         pd_vcodec@RK3399_PD_VCODEC {
 993                                 reg = <RK3399_PD_VCODEC>;
 994                                 clocks = <&cru ACLK_VCODEC>,
 995                                          <&cru HCLK_VCODEC>;
 996                                 pm_qos = <&qos_video_m0>;
 997                         };
 998                         pd_vdu@RK3399_PD_VDU {
 999                                 reg = <RK3399_PD_VDU>;
1000                                 clocks = <&cru ACLK_VDU>,
1001                                          <&cru HCLK_VDU>;
1002                                 pm_qos = <&qos_video_m1_r>,
1003                                          <&qos_video_m1_w>;
1004                         };
1005
1006                         /* These power domains are grouped by VD_GPU */
1007                         pd_gpu@RK3399_PD_GPU {
1008                                 reg = <RK3399_PD_GPU>;
1009                                 clocks = <&cru ACLK_GPU>;
1010                                 pm_qos = <&qos_gpu>;
1011                         };
1012
1013                         /* These power domains are grouped by VD_LOGIC */
1014                         pd_edp@RK3399_PD_EDP {
1015                                 reg = <RK3399_PD_EDP>;
1016                                 clocks = <&cru PCLK_EDP_CTRL>;
1017                         };
1018                         pd_emmc@RK3399_PD_EMMC {
1019                                 reg = <RK3399_PD_EMMC>;
1020                                 clocks = <&cru ACLK_EMMC>;
1021                                 pm_qos = <&qos_emmc>;
1022                         };
1023                         pd_gmac@RK3399_PD_GMAC {
1024                                 reg = <RK3399_PD_GMAC>;
1025                                 clocks = <&cru ACLK_GMAC>,
1026                                          <&cru PCLK_GMAC>;
1027                                 pm_qos = <&qos_gmac>;
1028                         };
1029                         pd_sd@RK3399_PD_SD {
1030                                 reg = <RK3399_PD_SD>;
1031                                 clocks = <&cru HCLK_SDMMC>,
1032                                          <&cru SCLK_SDMMC>;
1033                                 pm_qos = <&qos_sd>;
1034                         };
1035                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1036                                 reg = <RK3399_PD_SDIOAUDIO>;
1037                                 clocks = <&cru HCLK_SDIO>;
1038                                 pm_qos = <&qos_sdioaudio>;
1039                         };
1040                         pd_usb3@RK3399_PD_USB3 {
1041                                 reg = <RK3399_PD_USB3>;
1042                                 clocks = <&cru ACLK_USB3>;
1043                                 pm_qos = <&qos_usb_otg0>,
1044                                          <&qos_usb_otg1>;
1045                         };
1046                         pd_vio@RK3399_PD_VIO {
1047                                 reg = <RK3399_PD_VIO>;
1048                                 #address-cells = <1>;
1049                                 #size-cells = <0>;
1050
1051                                 pd_hdcp@RK3399_PD_HDCP {
1052                                         reg = <RK3399_PD_HDCP>;
1053                                         clocks = <&cru ACLK_HDCP>,
1054                                                  <&cru HCLK_HDCP>,
1055                                                  <&cru PCLK_HDCP>;
1056                                         pm_qos = <&qos_hdcp>;
1057                                 };
1058                                 pd_isp0@RK3399_PD_ISP0 {
1059                                         reg = <RK3399_PD_ISP0>;
1060                                         clocks = <&cru ACLK_ISP0>,
1061                                                  <&cru HCLK_ISP0>;
1062                                         pm_qos = <&qos_isp0_m0>,
1063                                                  <&qos_isp0_m1>;
1064                                 };
1065                                 pd_isp1@RK3399_PD_ISP1 {
1066                                         reg = <RK3399_PD_ISP1>;
1067                                         clocks = <&cru ACLK_ISP1>,
1068                                                  <&cru HCLK_ISP1>;
1069                                         pm_qos = <&qos_isp1_m0>,
1070                                                  <&qos_isp1_m1>;
1071                                 };
1072                                 pd_tcpc0@RK3399_PD_TCPC0 {
1073                                         reg = <RK3399_PD_TCPD0>;
1074                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1075                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1076                                 };
1077                                 pd_tcpc1@RK3399_PD_TCPC1 {
1078                                         reg = <RK3399_PD_TCPD1>;
1079                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1080                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1081                                 };
1082                                 pd_vo@RK3399_PD_VO {
1083                                         reg = <RK3399_PD_VO>;
1084                                         #address-cells = <1>;
1085                                         #size-cells = <0>;
1086
1087                                         pd_vopb@RK3399_PD_VOPB {
1088                                                 reg = <RK3399_PD_VOPB>;
1089                                                 clocks = <&cru ACLK_VOP0>,
1090                                                          <&cru HCLK_VOP0>;
1091                                                 pm_qos = <&qos_vop_big_r>,
1092                                                          <&qos_vop_big_w>;
1093                                         };
1094                                         pd_vopl@RK3399_PD_VOPL {
1095                                                 reg = <RK3399_PD_VOPL>;
1096                                                 clocks = <&cru ACLK_VOP1>,
1097                                                          <&cru HCLK_VOP1>;
1098                                                 pm_qos = <&qos_vop_little>;
1099                                         };
1100                                 };
1101                         };
1102                 };
1103         };
1104
1105         pmugrf: syscon@ff320000 {
1106                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1107                 reg = <0x0 0xff320000 0x0 0x1000>;
1108                 #address-cells = <1>;
1109                 #size-cells = <1>;
1110
1111                 pmu_io_domains: io-domains {
1112                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1113                         status = "disabled";
1114                 };
1115         };
1116
1117         spi3: spi@ff350000 {
1118                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1119                 reg = <0x0 0xff350000 0x0 0x1000>;
1120                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1121                 clock-names = "spiclk", "apb_pclk";
1122                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1123                 pinctrl-names = "default";
1124                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1125                 #address-cells = <1>;
1126                 #size-cells = <0>;
1127                 status = "disabled";
1128         };
1129
1130         uart4: serial@ff370000 {
1131                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1132                 reg = <0x0 0xff370000 0x0 0x100>;
1133                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1134                 clock-names = "baudclk", "apb_pclk";
1135                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1136                 reg-shift = <2>;
1137                 reg-io-width = <4>;
1138                 pinctrl-names = "default";
1139                 pinctrl-0 = <&uart4_xfer>;
1140                 status = "disabled";
1141         };
1142
1143         i2c0: i2c@ff3c0000 {
1144                 compatible = "rockchip,rk3399-i2c";
1145                 reg = <0x0 0xff3c0000 0x0 0x1000>;
1146                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1147                 assigned-clock-rates = <200000000>;
1148                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1149                 clock-names = "i2c", "pclk";
1150                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1151                 pinctrl-names = "default";
1152                 pinctrl-0 = <&i2c0_xfer>;
1153                 #address-cells = <1>;
1154                 #size-cells = <0>;
1155                 status = "disabled";
1156         };
1157
1158         i2c4: i2c@ff3d0000 {
1159                 compatible = "rockchip,rk3399-i2c";
1160                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1161                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1162                 assigned-clock-rates = <200000000>;
1163                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1164                 clock-names = "i2c", "pclk";
1165                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1166                 pinctrl-names = "default";
1167                 pinctrl-0 = <&i2c4_xfer>;
1168                 #address-cells = <1>;
1169                 #size-cells = <0>;
1170                 status = "disabled";
1171         };
1172
1173         i2c8: i2c@ff3e0000 {
1174                 compatible = "rockchip,rk3399-i2c";
1175                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1176                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1177                 assigned-clock-rates = <200000000>;
1178                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1179                 clock-names = "i2c", "pclk";
1180                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1181                 pinctrl-names = "default";
1182                 pinctrl-0 = <&i2c8_xfer>;
1183                 #address-cells = <1>;
1184                 #size-cells = <0>;
1185                 status = "disabled";
1186         };
1187
1188         pwm0: pwm@ff420000 {
1189                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1190                 reg = <0x0 0xff420000 0x0 0x10>;
1191                 #pwm-cells = <3>;
1192                 pinctrl-names = "default";
1193                 pinctrl-0 = <&pwm0_pin>;
1194                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1195                 clock-names = "pwm";
1196                 status = "disabled";
1197         };
1198
1199         pwm1: pwm@ff420010 {
1200                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1201                 reg = <0x0 0xff420010 0x0 0x10>;
1202                 #pwm-cells = <3>;
1203                 pinctrl-names = "default";
1204                 pinctrl-0 = <&pwm1_pin>;
1205                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1206                 clock-names = "pwm";
1207                 status = "disabled";
1208         };
1209
1210         pwm2: pwm@ff420020 {
1211                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1212                 reg = <0x0 0xff420020 0x0 0x10>;
1213                 #pwm-cells = <3>;
1214                 pinctrl-names = "default";
1215                 pinctrl-0 = <&pwm2_pin>;
1216                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1217                 clock-names = "pwm";
1218                 status = "disabled";
1219         };
1220
1221         pwm3: pwm@ff420030 {
1222                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1223                 reg = <0x0 0xff420030 0x0 0x10>;
1224                 #pwm-cells = <3>;
1225                 pinctrl-names = "default";
1226                 pinctrl-0 = <&pwm3a_pin>;
1227                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1228                 clock-names = "pwm";
1229                 status = "disabled";
1230         };
1231
1232         vpu_mmu: iommu@ff650800 {
1233                 compatible = "rockchip,iommu";
1234                 reg = <0x0 0xff650800 0x0 0x40>;
1235                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1236                 interrupt-names = "vpu_mmu";
1237                 #iommu-cells = <0>;
1238                 status = "disabled";
1239         };
1240
1241         vdec_mmu: iommu@ff660480 {
1242                 compatible = "rockchip,iommu";
1243                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1244                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1245                 interrupt-names = "vdec_mmu";
1246                 #iommu-cells = <0>;
1247                 status = "disabled";
1248         };
1249
1250         iep_mmu: iommu@ff670800 {
1251                 compatible = "rockchip,iommu";
1252                 reg = <0x0 0xff670800 0x0 0x40>;
1253                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1254                 interrupt-names = "iep_mmu";
1255                 #iommu-cells = <0>;
1256                 status = "disabled";
1257         };
1258
1259         rga: rga@ff680000 {
1260                 compatible = "rockchip,rk3399-rga";
1261                 reg = <0x0 0xff680000 0x0 0x10000>;
1262                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1263                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1264                 clock-names = "aclk", "hclk", "sclk";
1265                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1266                 reset-names = "core", "axi", "ahb";
1267                 power-domains = <&power RK3399_PD_RGA>;
1268         };
1269
1270         efuse0: efuse@ff690000 {
1271                 compatible = "rockchip,rk3399-efuse";
1272                 reg = <0x0 0xff690000 0x0 0x80>;
1273                 #address-cells = <1>;
1274                 #size-cells = <1>;
1275                 clocks = <&cru PCLK_EFUSE1024NS>;
1276                 clock-names = "pclk_efuse";
1277
1278                 /* Data cells */
1279                 cpu_id: cpu-id@7 {
1280                         reg = <0x07 0x10>;
1281                 };
1282                 cpub_leakage: cpu-leakage@17 {
1283                         reg = <0x17 0x1>;
1284                 };
1285                 gpu_leakage: gpu-leakage@18 {
1286                         reg = <0x18 0x1>;
1287                 };
1288                 center_leakage: center-leakage@19 {
1289                         reg = <0x19 0x1>;
1290                 };
1291                 cpul_leakage: cpu-leakage@1a {
1292                         reg = <0x1a 0x1>;
1293                 };
1294                 logic_leakage: logic-leakage@1b {
1295                         reg = <0x1b 0x1>;
1296                 };
1297                 wafer_info: wafer-info@1c {
1298                         reg = <0x1c 0x1>;
1299                 };
1300         };
1301
1302         pmucru: pmu-clock-controller@ff750000 {
1303                 compatible = "rockchip,rk3399-pmucru";
1304                 reg = <0x0 0xff750000 0x0 0x1000>;
1305                 rockchip,grf = <&pmugrf>;
1306                 #clock-cells = <1>;
1307                 #reset-cells = <1>;
1308                 assigned-clocks = <&pmucru PLL_PPLL>;
1309                 assigned-clock-rates = <676000000>;
1310         };
1311
1312         cru: clock-controller@ff760000 {
1313                 compatible = "rockchip,rk3399-cru";
1314                 reg = <0x0 0xff760000 0x0 0x1000>;
1315                 rockchip,grf = <&grf>;
1316                 #clock-cells = <1>;
1317                 #reset-cells = <1>;
1318                 assigned-clocks =
1319                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1320                         <&cru PLL_NPLL>,
1321                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1322                         <&cru PCLK_PERIHP>,
1323                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1324                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1325                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1326                         <&cru ACLK_VIO>;
1327                 assigned-clock-rates =
1328                          <594000000>,  <800000000>,
1329                         <1000000000>,
1330                          <150000000>,   <75000000>,
1331                           <37500000>,
1332                          <100000000>,  <100000000>,
1333                           <50000000>, <600000000>,
1334                          <100000000>,   <50000000>,
1335                          <400000000>;
1336         };
1337
1338         grf: syscon@ff770000 {
1339                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1340                 reg = <0x0 0xff770000 0x0 0x10000>;
1341                 #address-cells = <1>;
1342                 #size-cells = <1>;
1343
1344                 io_domains: io-domains {
1345                         compatible = "rockchip,rk3399-io-voltage-domain";
1346                         status = "disabled";
1347                 };
1348
1349                 u2phy0: usb2-phy@e450 {
1350                         compatible = "rockchip,rk3399-usb2phy";
1351                         reg = <0xe450 0x10>;
1352                         clocks = <&cru SCLK_USB2PHY0_REF>;
1353                         clock-names = "phyclk";
1354                         #clock-cells = <0>;
1355                         clock-output-names = "clk_usbphy0_480m";
1356                         status = "disabled";
1357
1358                         u2phy0_host: host-port {
1359                                 #phy-cells = <0>;
1360                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1361                                 interrupt-names = "linestate";
1362                                 status = "disabled";
1363                         };
1364
1365                         u2phy0_otg: otg-port {
1366                                 #phy-cells = <0>;
1367                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1368                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1369                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1370                                 interrupt-names = "otg-bvalid", "otg-id",
1371                                                   "linestate";
1372                                 status = "disabled";
1373                         };
1374                 };
1375
1376                 u2phy1: usb2-phy@e460 {
1377                         compatible = "rockchip,rk3399-usb2phy";
1378                         reg = <0xe460 0x10>;
1379                         clocks = <&cru SCLK_USB2PHY1_REF>;
1380                         clock-names = "phyclk";
1381                         #clock-cells = <0>;
1382                         clock-output-names = "clk_usbphy1_480m";
1383                         status = "disabled";
1384
1385                         u2phy1_host: host-port {
1386                                 #phy-cells = <0>;
1387                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1388                                 interrupt-names = "linestate";
1389                                 status = "disabled";
1390                         };
1391
1392                         u2phy1_otg: otg-port {
1393                                 #phy-cells = <0>;
1394                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1395                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1396                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1397                                 interrupt-names = "otg-bvalid", "otg-id",
1398                                                   "linestate";
1399                                 status = "disabled";
1400                         };
1401                 };
1402
1403                 emmc_phy: phy@f780 {
1404                         compatible = "rockchip,rk3399-emmc-phy";
1405                         reg = <0xf780 0x24>;
1406                         clocks = <&sdhci>;
1407                         clock-names = "emmcclk";
1408                         #phy-cells = <0>;
1409                         status = "disabled";
1410                 };
1411
1412                 pcie_phy: pcie-phy {
1413                         compatible = "rockchip,rk3399-pcie-phy";
1414                         clocks = <&cru SCLK_PCIEPHY_REF>;
1415                         clock-names = "refclk";
1416                         #phy-cells = <1>;
1417                         resets = <&cru SRST_PCIEPHY>;
1418                         reset-names = "phy";
1419                         status = "disabled";
1420                 };
1421         };
1422
1423         tcphy0: phy@ff7c0000 {
1424                 compatible = "rockchip,rk3399-typec-phy";
1425                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1426                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1427                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1428                 clock-names = "tcpdcore", "tcpdphy-ref";
1429                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1430                 assigned-clock-rates = <50000000>;
1431                 power-domains = <&power RK3399_PD_TCPD0>;
1432                 resets = <&cru SRST_UPHY0>,
1433                          <&cru SRST_UPHY0_PIPE_L00>,
1434                          <&cru SRST_P_UPHY0_TCPHY>;
1435                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1436                 rockchip,grf = <&grf>;
1437                 rockchip,typec-conn-dir = <0xe580 0 16>;
1438                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1439                 rockchip,external-psm = <0xe588 14 30>;
1440                 rockchip,pipe-status = <0xe5c0 0 0>;
1441                 status = "disabled";
1442
1443                 tcphy0_dp: dp-port {
1444                         #phy-cells = <0>;
1445                 };
1446
1447                 tcphy0_usb3: usb3-port {
1448                         #phy-cells = <0>;
1449                 };
1450         };
1451
1452         tcphy1: phy@ff800000 {
1453                 compatible = "rockchip,rk3399-typec-phy";
1454                 reg = <0x0 0xff800000 0x0 0x40000>;
1455                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1456                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1457                 clock-names = "tcpdcore", "tcpdphy-ref";
1458                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1459                 assigned-clock-rates = <50000000>;
1460                 power-domains = <&power RK3399_PD_TCPD1>;
1461                 resets = <&cru SRST_UPHY1>,
1462                          <&cru SRST_UPHY1_PIPE_L00>,
1463                          <&cru SRST_P_UPHY1_TCPHY>;
1464                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1465                 rockchip,grf = <&grf>;
1466                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1467                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1468                 rockchip,external-psm = <0xe594 14 30>;
1469                 rockchip,pipe-status = <0xe5c0 16 16>;
1470                 status = "disabled";
1471
1472                 tcphy1_dp: dp-port {
1473                         #phy-cells = <0>;
1474                 };
1475
1476                 tcphy1_usb3: usb3-port {
1477                         #phy-cells = <0>;
1478                 };
1479         };
1480
1481         watchdog@ff848000 {
1482                 compatible = "snps,dw-wdt";
1483                 reg = <0x0 0xff848000 0x0 0x100>;
1484                 clocks = <&cru PCLK_WDT>;
1485                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1486         };
1487
1488         rktimer: rktimer@ff850000 {
1489                 compatible = "rockchip,rk3399-timer";
1490                 reg = <0x0 0xff850000 0x0 0x1000>;
1491                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1492                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1493                 clock-names = "pclk", "timer";
1494         };
1495
1496         spdif: spdif@ff870000 {
1497                 compatible = "rockchip,rk3399-spdif";
1498                 reg = <0x0 0xff870000 0x0 0x1000>;
1499                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1500                 dmas = <&dmac_bus 7>;
1501                 dma-names = "tx";
1502                 clock-names = "mclk", "hclk";
1503                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1504                 pinctrl-names = "default";
1505                 pinctrl-0 = <&spdif_bus>;
1506                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1507                 status = "disabled";
1508         };
1509
1510         i2s0: i2s@ff880000 {
1511                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1512                 reg = <0x0 0xff880000 0x0 0x1000>;
1513                 rockchip,grf = <&grf>;
1514                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1515                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1516                 dma-names = "tx", "rx";
1517                 clock-names = "i2s_clk", "i2s_hclk";
1518                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1519                 pinctrl-names = "default";
1520                 pinctrl-0 = <&i2s0_8ch_bus>;
1521                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1522                 status = "disabled";
1523         };
1524
1525         i2s1: i2s@ff890000 {
1526                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1527                 reg = <0x0 0xff890000 0x0 0x1000>;
1528                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1529                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1530                 dma-names = "tx", "rx";
1531                 clock-names = "i2s_clk", "i2s_hclk";
1532                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1533                 pinctrl-names = "default";
1534                 pinctrl-0 = <&i2s1_2ch_bus>;
1535                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1536                 status = "disabled";
1537         };
1538
1539         i2s2: i2s@ff8a0000 {
1540                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1541                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1542                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1543                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1544                 dma-names = "tx", "rx";
1545                 clock-names = "i2s_clk", "i2s_hclk";
1546                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1547                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1548                 status = "disabled";
1549         };
1550
1551         vopl: vop@ff8f0000 {
1552                 compatible = "rockchip,rk3399-vop-lit";
1553                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1554                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1555                 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1556                 assigned-clock-rates = <400000000>, <100000000>;
1557                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1558                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1559                 iommus = <&vopl_mmu>;
1560                 power-domains = <&power RK3399_PD_VOPL>;
1561                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1562                 reset-names = "axi", "ahb", "dclk";
1563                 status = "disabled";
1564
1565                 vopl_out: port {
1566                         #address-cells = <1>;
1567                         #size-cells = <0>;
1568
1569                         vopl_out_mipi: endpoint@0 {
1570                                 reg = <0>;
1571                                 remote-endpoint = <&mipi_in_vopl>;
1572                         };
1573
1574                         vopl_out_edp: endpoint@1 {
1575                                 reg = <1>;
1576                                 remote-endpoint = <&edp_in_vopl>;
1577                         };
1578
1579                         vopl_out_hdmi: endpoint@2 {
1580                                 reg = <2>;
1581                                 remote-endpoint = <&hdmi_in_vopl>;
1582                         };
1583
1584                         vopl_out_mipi1: endpoint@3 {
1585                                 reg = <3>;
1586                                 remote-endpoint = <&mipi1_in_vopl>;
1587                         };
1588
1589                         vopl_out_dp: endpoint@4 {
1590                                 reg = <4>;
1591                                 remote-endpoint = <&dp_in_vopl>;
1592                         };
1593                 };
1594         };
1595
1596         vopl_mmu: iommu@ff8f3f00 {
1597                 compatible = "rockchip,iommu";
1598                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1599                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1600                 interrupt-names = "vopl_mmu";
1601                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1602                 clock-names = "aclk", "hclk";
1603                 power-domains = <&power RK3399_PD_VOPL>;
1604                 #iommu-cells = <0>;
1605                 status = "disabled";
1606         };
1607
1608         vopb: vop@ff900000 {
1609                 compatible = "rockchip,rk3399-vop-big";
1610                 reg = <0x0 0xff900000 0x0 0x3efc>;
1611                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1612                 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1613                 assigned-clock-rates = <400000000>, <100000000>;
1614                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1615                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1616                 iommus = <&vopb_mmu>;
1617                 power-domains = <&power RK3399_PD_VOPB>;
1618                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1619                 reset-names = "axi", "ahb", "dclk";
1620                 status = "disabled";
1621
1622                 vopb_out: port {
1623                         #address-cells = <1>;
1624                         #size-cells = <0>;
1625
1626                         vopb_out_edp: endpoint@0 {
1627                                 reg = <0>;
1628                                 remote-endpoint = <&edp_in_vopb>;
1629                         };
1630
1631                         vopb_out_mipi: endpoint@1 {
1632                                 reg = <1>;
1633                                 remote-endpoint = <&mipi_in_vopb>;
1634                         };
1635
1636                         vopb_out_hdmi: endpoint@2 {
1637                                 reg = <2>;
1638                                 remote-endpoint = <&hdmi_in_vopb>;
1639                         };
1640
1641                         vopb_out_mipi1: endpoint@3 {
1642                                 reg = <3>;
1643                                 remote-endpoint = <&mipi1_in_vopb>;
1644                         };
1645
1646                         vopb_out_dp: endpoint@4 {
1647                                 reg = <4>;
1648                                 remote-endpoint = <&dp_in_vopb>;
1649                         };
1650                 };
1651         };
1652
1653         vopb_mmu: iommu@ff903f00 {
1654                 compatible = "rockchip,iommu";
1655                 reg = <0x0 0xff903f00 0x0 0x100>;
1656                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1657                 interrupt-names = "vopb_mmu";
1658                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1659                 clock-names = "aclk", "hclk";
1660                 power-domains = <&power RK3399_PD_VOPB>;
1661                 #iommu-cells = <0>;
1662                 status = "disabled";
1663         };
1664
1665         isp0_mmu: iommu@ff914000 {
1666                 compatible = "rockchip,iommu";
1667                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1668                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1669                 interrupt-names = "isp0_mmu";
1670                 #iommu-cells = <0>;
1671                 rockchip,disable-mmu-reset;
1672                 status = "disabled";
1673         };
1674
1675         isp1_mmu: iommu@ff924000 {
1676                 compatible = "rockchip,iommu";
1677                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1678                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1679                 interrupt-names = "isp1_mmu";
1680                 #iommu-cells = <0>;
1681                 rockchip,disable-mmu-reset;
1682                 status = "disabled";
1683         };
1684
1685         hdmi: hdmi@ff940000 {
1686                 compatible = "rockchip,rk3399-dw-hdmi";
1687                 reg = <0x0 0xff940000 0x0 0x20000>;
1688                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1689                 clocks = <&cru PCLK_HDMI_CTRL>,
1690                          <&cru SCLK_HDMI_SFR>,
1691                          <&cru PLL_VPLL>,
1692                          <&cru PCLK_VIO_GRF>,
1693                          <&cru SCLK_HDMI_CEC>;
1694                 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1695                 power-domains = <&power RK3399_PD_HDCP>;
1696                 reg-io-width = <4>;
1697                 rockchip,grf = <&grf>;
1698                 status = "disabled";
1699
1700                 ports {
1701                         hdmi_in: port {
1702                                 #address-cells = <1>;
1703                                 #size-cells = <0>;
1704
1705                                 hdmi_in_vopb: endpoint@0 {
1706                                         reg = <0>;
1707                                         remote-endpoint = <&vopb_out_hdmi>;
1708                                 };
1709                                 hdmi_in_vopl: endpoint@1 {
1710                                         reg = <1>;
1711                                         remote-endpoint = <&vopl_out_hdmi>;
1712                                 };
1713                         };
1714                 };
1715         };
1716
1717         mipi_dsi: mipi@ff960000 {
1718                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1719                 reg = <0x0 0xff960000 0x0 0x8000>;
1720                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1721                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1722                          <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1723                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1724                 power-domains = <&power RK3399_PD_VIO>;
1725                 resets = <&cru SRST_P_MIPI_DSI0>;
1726                 reset-names = "apb";
1727                 rockchip,grf = <&grf>;
1728                 status = "disabled";
1729
1730                 ports {
1731                         #address-cells = <1>;
1732                         #size-cells = <0>;
1733
1734                         mipi_in: port@0 {
1735                                 reg = <0>;
1736                                 #address-cells = <1>;
1737                                 #size-cells = <0>;
1738
1739                                 mipi_in_vopb: endpoint@0 {
1740                                         reg = <0>;
1741                                         remote-endpoint = <&vopb_out_mipi>;
1742                                 };
1743                                 mipi_in_vopl: endpoint@1 {
1744                                         reg = <1>;
1745                                         remote-endpoint = <&vopl_out_mipi>;
1746                                 };
1747                         };
1748                 };
1749         };
1750
1751         mipi_dsi1: mipi@ff968000 {
1752                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1753                 reg = <0x0 0xff968000 0x0 0x8000>;
1754                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1755                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1756                          <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1757                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1758                 power-domains = <&power RK3399_PD_VIO>;
1759                 resets = <&cru SRST_P_MIPI_DSI1>;
1760                 reset-names = "apb";
1761                 rockchip,grf = <&grf>;
1762                 status = "disabled";
1763
1764                 ports {
1765                         #address-cells = <1>;
1766                         #size-cells = <0>;
1767
1768                         mipi1_in: port@0 {
1769                                 reg = <0>;
1770                                 #address-cells = <1>;
1771                                 #size-cells = <0>;
1772
1773                                 mipi1_in_vopb: endpoint@0 {
1774                                         reg = <0>;
1775                                         remote-endpoint = <&vopb_out_mipi1>;
1776                                 };
1777
1778                                 mipi1_in_vopl: endpoint@1 {
1779                                         reg = <1>;
1780                                         remote-endpoint = <&vopl_out_mipi1>;
1781                                 };
1782                         };
1783                 };
1784         };
1785
1786         edp: edp@ff970000 {
1787                 compatible = "rockchip,rk3399-edp";
1788                 reg = <0x0 0xff970000 0x0 0x8000>;
1789                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1790                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1791                 clock-names = "dp", "pclk", "grf";
1792                 pinctrl-names = "default";
1793                 pinctrl-0 = <&edp_hpd>;
1794                 power-domains = <&power RK3399_PD_EDP>;
1795                 resets = <&cru SRST_P_EDP_CTRL>;
1796                 reset-names = "dp";
1797                 rockchip,grf = <&grf>;
1798                 status = "disabled";
1799
1800                 ports {
1801                         #address-cells = <1>;
1802                         #size-cells = <0>;
1803                         edp_in: port@0 {
1804                                 reg = <0>;
1805                                 #address-cells = <1>;
1806                                 #size-cells = <0>;
1807
1808                                 edp_in_vopb: endpoint@0 {
1809                                         reg = <0>;
1810                                         remote-endpoint = <&vopb_out_edp>;
1811                                 };
1812
1813                                 edp_in_vopl: endpoint@1 {
1814                                         reg = <1>;
1815                                         remote-endpoint = <&vopl_out_edp>;
1816                                 };
1817                         };
1818                 };
1819         };
1820
1821         gpu: gpu@ff9a0000 {
1822                 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1823                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1824                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1825                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1826                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1827                 interrupt-names = "gpu", "job", "mmu";
1828                 clocks = <&cru ACLK_GPU>;
1829                 power-domains = <&power RK3399_PD_GPU>;
1830                 status = "disabled";
1831         };
1832
1833         pinctrl: pinctrl {
1834                 compatible = "rockchip,rk3399-pinctrl";
1835                 rockchip,grf = <&grf>;
1836                 rockchip,pmu = <&pmugrf>;
1837                 #address-cells = <2>;
1838                 #size-cells = <2>;
1839                 ranges;
1840
1841                 gpio0: gpio0@ff720000 {
1842                         compatible = "rockchip,gpio-bank";
1843                         reg = <0x0 0xff720000 0x0 0x100>;
1844                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1845                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1846
1847                         gpio-controller;
1848                         #gpio-cells = <0x2>;
1849
1850                         interrupt-controller;
1851                         #interrupt-cells = <0x2>;
1852                 };
1853
1854                 gpio1: gpio1@ff730000 {
1855                         compatible = "rockchip,gpio-bank";
1856                         reg = <0x0 0xff730000 0x0 0x100>;
1857                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1858                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1859
1860                         gpio-controller;
1861                         #gpio-cells = <0x2>;
1862
1863                         interrupt-controller;
1864                         #interrupt-cells = <0x2>;
1865                 };
1866
1867                 gpio2: gpio2@ff780000 {
1868                         compatible = "rockchip,gpio-bank";
1869                         reg = <0x0 0xff780000 0x0 0x100>;
1870                         clocks = <&cru PCLK_GPIO2>;
1871                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1872
1873                         gpio-controller;
1874                         #gpio-cells = <0x2>;
1875
1876                         interrupt-controller;
1877                         #interrupt-cells = <0x2>;
1878                 };
1879
1880                 gpio3: gpio3@ff788000 {
1881                         compatible = "rockchip,gpio-bank";
1882                         reg = <0x0 0xff788000 0x0 0x100>;
1883                         clocks = <&cru PCLK_GPIO3>;
1884                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1885
1886                         gpio-controller;
1887                         #gpio-cells = <0x2>;
1888
1889                         interrupt-controller;
1890                         #interrupt-cells = <0x2>;
1891                 };
1892
1893                 gpio4: gpio4@ff790000 {
1894                         compatible = "rockchip,gpio-bank";
1895                         reg = <0x0 0xff790000 0x0 0x100>;
1896                         clocks = <&cru PCLK_GPIO4>;
1897                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1898
1899                         gpio-controller;
1900                         #gpio-cells = <0x2>;
1901
1902                         interrupt-controller;
1903                         #interrupt-cells = <0x2>;
1904                 };
1905
1906                 pcfg_pull_up: pcfg-pull-up {
1907                         bias-pull-up;
1908                 };
1909
1910                 pcfg_pull_down: pcfg-pull-down {
1911                         bias-pull-down;
1912                 };
1913
1914                 pcfg_pull_none: pcfg-pull-none {
1915                         bias-disable;
1916                 };
1917
1918                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1919                         bias-disable;
1920                         drive-strength = <12>;
1921                 };
1922
1923                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1924                         bias-pull-up;
1925                         drive-strength = <8>;
1926                 };
1927
1928                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1929                         bias-pull-down;
1930                         drive-strength = <4>;
1931                 };
1932
1933                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1934                         bias-pull-up;
1935                         drive-strength = <2>;
1936                 };
1937
1938                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1939                         bias-pull-down;
1940                         drive-strength = <12>;
1941                 };
1942
1943                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1944                         bias-disable;
1945                         drive-strength = <13>;
1946                 };
1947
1948                 clock {
1949                         clk_32k: clk-32k {
1950                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1951                         };
1952                 };
1953
1954                 edp {
1955                         edp_hpd: edp-hpd {
1956                                 rockchip,pins =
1957                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
1958                         };
1959                 };
1960
1961                 gmac {
1962                         rgmii_pins: rgmii-pins {
1963                                 rockchip,pins =
1964                                         /* mac_txclk */
1965                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1966                                         /* mac_rxclk */
1967                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1968                                         /* mac_mdio */
1969                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1970                                         /* mac_txen */
1971                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1972                                         /* mac_clk */
1973                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1974                                         /* mac_rxdv */
1975                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1976                                         /* mac_mdc */
1977                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1978                                         /* mac_rxd1 */
1979                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1980                                         /* mac_rxd0 */
1981                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1982                                         /* mac_txd1 */
1983                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1984                                         /* mac_txd0 */
1985                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1986                                         /* mac_rxd3 */
1987                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1988                                         /* mac_rxd2 */
1989                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1990                                         /* mac_txd3 */
1991                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1992                                         /* mac_txd2 */
1993                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1994                         };
1995
1996                         rmii_pins: rmii-pins {
1997                                 rockchip,pins =
1998                                         /* mac_mdio */
1999                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2000                                         /* mac_txen */
2001                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2002                                         /* mac_clk */
2003                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2004                                         /* mac_rxer */
2005                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2006                                         /* mac_rxdv */
2007                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2008                                         /* mac_mdc */
2009                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2010                                         /* mac_rxd1 */
2011                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2012                                         /* mac_rxd0 */
2013                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2014                                         /* mac_txd1 */
2015                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2016                                         /* mac_txd0 */
2017                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2018                         };
2019                 };
2020
2021                 i2c0 {
2022                         i2c0_xfer: i2c0-xfer {
2023                                 rockchip,pins =
2024                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2025                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2026                         };
2027                 };
2028
2029                 i2c1 {
2030                         i2c1_xfer: i2c1-xfer {
2031                                 rockchip,pins =
2032                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2033                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2034                         };
2035                 };
2036
2037                 i2c2 {
2038                         i2c2_xfer: i2c2-xfer {
2039                                 rockchip,pins =
2040                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2041                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2042                         };
2043                 };
2044
2045                 i2c3 {
2046                         i2c3_xfer: i2c3-xfer {
2047                                 rockchip,pins =
2048                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2049                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2050                         };
2051                 };
2052
2053                 i2c4 {
2054                         i2c4_xfer: i2c4-xfer {
2055                                 rockchip,pins =
2056                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2057                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2058                         };
2059                 };
2060
2061                 i2c5 {
2062                         i2c5_xfer: i2c5-xfer {
2063                                 rockchip,pins =
2064                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2065                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2066                         };
2067                 };
2068
2069                 i2c6 {
2070                         i2c6_xfer: i2c6-xfer {
2071                                 rockchip,pins =
2072                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2073                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2074                         };
2075                 };
2076
2077                 i2c7 {
2078                         i2c7_xfer: i2c7-xfer {
2079                                 rockchip,pins =
2080                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2081                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2082                         };
2083                 };
2084
2085                 i2c8 {
2086                         i2c8_xfer: i2c8-xfer {
2087                                 rockchip,pins =
2088                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2089                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2090                         };
2091                 };
2092
2093                 i2s0 {
2094                         i2s0_2ch_bus: i2s0-2ch-bus {
2095                                 rockchip,pins =
2096                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2097                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2098                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2099                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2100                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2101                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2102                         };
2103
2104                         i2s0_8ch_bus: i2s0-8ch-bus {
2105                                 rockchip,pins =
2106                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2107                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2108                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2109                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2110                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2111                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2112                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2113                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2114                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2115                         };
2116                 };
2117
2118                 i2s1 {
2119                         i2s1_2ch_bus: i2s1-2ch-bus {
2120                                 rockchip,pins =
2121                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2122                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2123                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2124                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2125                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2126                         };
2127                 };
2128
2129                 sdio0 {
2130                         sdio0_bus1: sdio0-bus1 {
2131                                 rockchip,pins =
2132                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
2133                         };
2134
2135                         sdio0_bus4: sdio0-bus4 {
2136                                 rockchip,pins =
2137                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
2138                                         <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
2139                                         <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
2140                                         <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
2141                         };
2142
2143                         sdio0_cmd: sdio0-cmd {
2144                                 rockchip,pins =
2145                                         <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
2146                         };
2147
2148                         sdio0_clk: sdio0-clk {
2149                                 rockchip,pins =
2150                                         <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
2151                         };
2152
2153                         sdio0_cd: sdio0-cd {
2154                                 rockchip,pins =
2155                                         <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
2156                         };
2157
2158                         sdio0_pwr: sdio0-pwr {
2159                                 rockchip,pins =
2160                                         <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
2161                         };
2162
2163                         sdio0_bkpwr: sdio0-bkpwr {
2164                                 rockchip,pins =
2165                                         <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
2166                         };
2167
2168                         sdio0_wp: sdio0-wp {
2169                                 rockchip,pins =
2170                                         <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
2171                         };
2172
2173                         sdio0_int: sdio0-int {
2174                                 rockchip,pins =
2175                                         <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
2176                         };
2177                 };
2178
2179                 sdmmc {
2180                         sdmmc_bus1: sdmmc-bus1 {
2181                                 rockchip,pins =
2182                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2183                         };
2184
2185                         sdmmc_bus4: sdmmc-bus4 {
2186                                 rockchip,pins =
2187                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
2188                                         <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
2189                                         <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
2190                                         <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
2191                         };
2192
2193                         sdmmc_clk: sdmmc-clk {
2194                                 rockchip,pins =
2195                                         <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
2196                         };
2197
2198                         sdmmc_cmd: sdmmc-cmd {
2199                                 rockchip,pins =
2200                                         <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
2201                         };
2202
2203                         sdmmc_cd: sdmmc-cd {
2204                                 rockchip,pins =
2205                                         <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
2206                         };
2207
2208                         sdmmc_wp: sdmmc-wp {
2209                                 rockchip,pins =
2210                                         <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2211                         };
2212                 };
2213
2214                 sleep {
2215                         ap_pwroff: ap-pwroff {
2216                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
2217                         };
2218
2219                         ddrio_pwroff: ddrio-pwroff {
2220                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
2221                         };
2222                 };
2223
2224                 spdif {
2225                         spdif_bus: spdif-bus {
2226                                 rockchip,pins =
2227                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2228                         };
2229
2230                         spdif_bus_1: spdif-bus-1 {
2231                                 rockchip,pins =
2232                                         <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2233                         };
2234                 };
2235
2236                 spi0 {
2237                         spi0_clk: spi0-clk {
2238                                 rockchip,pins =
2239                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2240                         };
2241                         spi0_cs0: spi0-cs0 {
2242                                 rockchip,pins =
2243                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2244                         };
2245                         spi0_cs1: spi0-cs1 {
2246                                 rockchip,pins =
2247                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2248                         };
2249                         spi0_tx: spi0-tx {
2250                                 rockchip,pins =
2251                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2252                         };
2253                         spi0_rx: spi0-rx {
2254                                 rockchip,pins =
2255                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2256                         };
2257                 };
2258
2259                 spi1 {
2260                         spi1_clk: spi1-clk {
2261                                 rockchip,pins =
2262                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2263                         };
2264                         spi1_cs0: spi1-cs0 {
2265                                 rockchip,pins =
2266                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2267                         };
2268                         spi1_rx: spi1-rx {
2269                                 rockchip,pins =
2270                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2271                         };
2272                         spi1_tx: spi1-tx {
2273                                 rockchip,pins =
2274                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2275                         };
2276                 };
2277
2278                 spi2 {
2279                         spi2_clk: spi2-clk {
2280                                 rockchip,pins =
2281                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2282                         };
2283                         spi2_cs0: spi2-cs0 {
2284                                 rockchip,pins =
2285                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2286                         };
2287                         spi2_rx: spi2-rx {
2288                                 rockchip,pins =
2289                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2290                         };
2291                         spi2_tx: spi2-tx {
2292                                 rockchip,pins =
2293                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2294                         };
2295                 };
2296
2297                 spi3 {
2298                         spi3_clk: spi3-clk {
2299                                 rockchip,pins =
2300                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2301                         };
2302                         spi3_cs0: spi3-cs0 {
2303                                 rockchip,pins =
2304                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2305                         };
2306                         spi3_rx: spi3-rx {
2307                                 rockchip,pins =
2308                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2309                         };
2310                         spi3_tx: spi3-tx {
2311                                 rockchip,pins =
2312                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2313                         };
2314                 };
2315
2316                 spi4 {
2317                         spi4_clk: spi4-clk {
2318                                 rockchip,pins =
2319                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2320                         };
2321                         spi4_cs0: spi4-cs0 {
2322                                 rockchip,pins =
2323                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2324                         };
2325                         spi4_rx: spi4-rx {
2326                                 rockchip,pins =
2327                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2328                         };
2329                         spi4_tx: spi4-tx {
2330                                 rockchip,pins =
2331                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2332                         };
2333                 };
2334
2335                 spi5 {
2336                         spi5_clk: spi5-clk {
2337                                 rockchip,pins =
2338                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2339                         };
2340                         spi5_cs0: spi5-cs0 {
2341                                 rockchip,pins =
2342                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2343                         };
2344                         spi5_rx: spi5-rx {
2345                                 rockchip,pins =
2346                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2347                         };
2348                         spi5_tx: spi5-tx {
2349                                 rockchip,pins =
2350                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2351                         };
2352                 };
2353
2354                 testclk {
2355                         test_clkout0: test-clkout0 {
2356                                 rockchip,pins =
2357                                         <0 0 RK_FUNC_1 &pcfg_pull_none>;
2358                         };
2359
2360                         test_clkout1: test-clkout1 {
2361                                 rockchip,pins =
2362                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
2363                         };
2364
2365                         test_clkout2: test-clkout2 {
2366                                 rockchip,pins =
2367                                         <0 8 RK_FUNC_3 &pcfg_pull_none>;
2368                         };
2369                 };
2370
2371                 tsadc {
2372                         otp_gpio: otp-gpio {
2373                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2374                         };
2375
2376                         otp_out: otp-out {
2377                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2378                         };
2379                 };
2380
2381                 uart0 {
2382                         uart0_xfer: uart0-xfer {
2383                                 rockchip,pins =
2384                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2385                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2386                         };
2387
2388                         uart0_cts: uart0-cts {
2389                                 rockchip,pins =
2390                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2391                         };
2392
2393                         uart0_rts: uart0-rts {
2394                                 rockchip,pins =
2395                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2396                         };
2397                 };
2398
2399                 uart1 {
2400                         uart1_xfer: uart1-xfer {
2401                                 rockchip,pins =
2402                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2403                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2404                         };
2405                 };
2406
2407                 uart2a {
2408                         uart2a_xfer: uart2a-xfer {
2409                                 rockchip,pins =
2410                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2411                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2412                         };
2413                 };
2414
2415                 uart2b {
2416                         uart2b_xfer: uart2b-xfer {
2417                                 rockchip,pins =
2418                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2419                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2420                         };
2421                 };
2422
2423                 uart2c {
2424                         uart2c_xfer: uart2c-xfer {
2425                                 rockchip,pins =
2426                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2427                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2428                         };
2429                 };
2430
2431                 uart3 {
2432                         uart3_xfer: uart3-xfer {
2433                                 rockchip,pins =
2434                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2435                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2436                         };
2437
2438                         uart3_cts: uart3-cts {
2439                                 rockchip,pins =
2440                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2441                         };
2442
2443                         uart3_rts: uart3-rts {
2444                                 rockchip,pins =
2445                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2446                         };
2447                 };
2448
2449                 uart4 {
2450                         uart4_xfer: uart4-xfer {
2451                                 rockchip,pins =
2452                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2453                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2454                         };
2455                 };
2456
2457                 uarthdcp {
2458                         uarthdcp_xfer: uarthdcp-xfer {
2459                                 rockchip,pins =
2460                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2461                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2462                         };
2463                 };
2464
2465                 pwm0 {
2466                         pwm0_pin: pwm0-pin {
2467                                 rockchip,pins =
2468                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2469                         };
2470
2471                         vop0_pwm_pin: vop0-pwm-pin {
2472                                 rockchip,pins =
2473                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2474                         };
2475                 };
2476
2477                 pwm1 {
2478                         pwm1_pin: pwm1-pin {
2479                                 rockchip,pins =
2480                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2481                         };
2482
2483                         vop1_pwm_pin: vop1-pwm-pin {
2484                                 rockchip,pins =
2485                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2486                         };
2487                 };
2488
2489                 pwm2 {
2490                         pwm2_pin: pwm2-pin {
2491                                 rockchip,pins =
2492                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2493                         };
2494                 };
2495
2496                 pwm3a {
2497                         pwm3a_pin: pwm3a-pin {
2498                                 rockchip,pins =
2499                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2500                         };
2501                 };
2502
2503                 pwm3b {
2504                         pwm3b_pin: pwm3b-pin {
2505                                 rockchip,pins =
2506                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2507                         };
2508                 };
2509
2510                 hdmi {
2511                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2512                                 rockchip,pins =
2513                                         <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
2514                                         <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2515                         };
2516
2517                         hdmi_cec: hdmi-cec {
2518                                 rockchip,pins =
2519                                         <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
2520                         };
2521                 };
2522
2523                 pcie {
2524                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2525                                 rockchip,pins =
2526                                         <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2527                         };
2528
2529                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2530                                 rockchip,pins =
2531                                         <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2532                         };
2533                 };
2534
2535         };
2536 };