arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   4  */
   5
   6 #include <dt-bindings/clock/rk3368-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/soc/rockchip,boot-mode.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "rockchip,rk3368";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 ethernet0 = &gmac;
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 i2c4 = &i2c4;
  27                 i2c5 = &i2c5;
  28                 serial0 = &uart0;
  29                 serial1 = &uart1;
  30                 serial2 = &uart2;
  31                 serial3 = &uart3;
  32                 serial4 = &uart4;
  33                 spi0 = &spi0;
  34                 spi1 = &spi1;
  35                 spi2 = &spi2;
  36         };
  37
  38         cpus {
  39                 #address-cells = <0x2>;
  40                 #size-cells = <0x0>;
  41
  42                 cpu-map {
  43                         cluster0 {
  44                                 core0 {
  45                                         cpu = <&cpu_b0>;
  46                                 };
  47                                 core1 {
  48                                         cpu = <&cpu_b1>;
  49                                 };
  50                                 core2 {
  51                                         cpu = <&cpu_b2>;
  52                                 };
  53                                 core3 {
  54                                         cpu = <&cpu_b3>;
  55                                 };
  56                         };
  57
  58                         cluster1 {
  59                                 core0 {
  60                                         cpu = <&cpu_l0>;
  61                                 };
  62                                 core1 {
  63                                         cpu = <&cpu_l1>;
  64                                 };
  65                                 core2 {
  66                                         cpu = <&cpu_l2>;
  67                                 };
  68                                 core3 {
  69                                         cpu = <&cpu_l3>;
  70                                 };
  71                         };
  72                 };
  73
  74                 cpu_l0: cpu@0 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53";
  77                         reg = <0x0 0x0>;
  78                         enable-method = "psci";
  79                         #cooling-cells = <2>; /* min followed by max */
  80                 };
  81
  82                 cpu_l1: cpu@1 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53";
  85                         reg = <0x0 0x1>;
  86                         enable-method = "psci";
  87                         #cooling-cells = <2>; /* min followed by max */
  88                 };
  89
  90                 cpu_l2: cpu@2 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a53";
  93                         reg = <0x0 0x2>;
  94                         enable-method = "psci";
  95                         #cooling-cells = <2>; /* min followed by max */
  96                 };
  97
  98                 cpu_l3: cpu@3 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a53";
 101                         reg = <0x0 0x3>;
 102                         enable-method = "psci";
 103                         #cooling-cells = <2>; /* min followed by max */
 104                 };
 105
 106                 cpu_b0: cpu@100 {
 107                         device_type = "cpu";
 108                         compatible = "arm,cortex-a53";
 109                         reg = <0x0 0x100>;
 110                         enable-method = "psci";
 111                         #cooling-cells = <2>; /* min followed by max */
 112                 };
 113
 114                 cpu_b1: cpu@101 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a53";
 117                         reg = <0x0 0x101>;
 118                         enable-method = "psci";
 119                         #cooling-cells = <2>; /* min followed by max */
 120                 };
 121
 122                 cpu_b2: cpu@102 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a53";
 125                         reg = <0x0 0x102>;
 126                         enable-method = "psci";
 127                         #cooling-cells = <2>; /* min followed by max */
 128                 };
 129
 130                 cpu_b3: cpu@103 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a53";
 133                         reg = <0x0 0x103>;
 134                         enable-method = "psci";
 135                         #cooling-cells = <2>; /* min followed by max */
 136                 };
 137         };
 138
 139         amba {
 140                 compatible = "simple-bus";
 141                 #address-cells = <2>;
 142                 #size-cells = <2>;
 143                 ranges;
 144
 145                 dmac_peri: dma-controller@ff250000 {
 146                         compatible = "arm,pl330", "arm,primecell";
 147                         reg = <0x0 0xff250000 0x0 0x4000>;
 148                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 149                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 150                         #dma-cells = <1>;
 151                         arm,pl330-broken-no-flushp;
 152                         clocks = <&cru ACLK_DMAC_PERI>;
 153                         clock-names = "apb_pclk";
 154                 };
 155
 156                 dmac_bus: dma-controller@ff600000 {
 157                         compatible = "arm,pl330", "arm,primecell";
 158                         reg = <0x0 0xff600000 0x0 0x4000>;
 159                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 160                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 161                         #dma-cells = <1>;
 162                         arm,pl330-broken-no-flushp;
 163                         clocks = <&cru ACLK_DMAC_BUS>;
 164                         clock-names = "apb_pclk";
 165                 };
 166         };
 167
 168         arm-pmu {
 169                 compatible = "arm,armv8-pmuv3";
 170                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 178                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 179                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 180                                      <&cpu_b2>, <&cpu_b3>;
 181         };
 182
 183         psci {
 184                 compatible = "arm,psci-0.2";
 185                 method = "smc";
 186         };
 187
 188         timer {
 189                 compatible = "arm,armv8-timer";
 190                 interrupts = <GIC_PPI 13
 191                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 192                              <GIC_PPI 14
 193                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 194                              <GIC_PPI 11
 195                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 196                              <GIC_PPI 10
 197                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 198         };
 199
 200         xin24m: oscillator {
 201                 compatible = "fixed-clock";
 202                 clock-frequency = <24000000>;
 203                 clock-output-names = "xin24m";
 204                 #clock-cells = <0>;
 205         };
 206
 207         sdmmc: dwmmc@ff0c0000 {
 208                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 209                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 210                 max-frequency = <150000000>;
 211                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 212                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 213                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 214                 fifo-depth = <0x100>;
 215                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 216                 resets = <&cru SRST_MMC0>;
 217                 reset-names = "reset";
 218                 status = "disabled";
 219         };
 220
 221         sdio0: dwmmc@ff0d0000 {
 222                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 223                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 224                 max-frequency = <150000000>;
 225                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 226                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 227                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 228                 fifo-depth = <0x100>;
 229                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 230                 resets = <&cru SRST_SDIO0>;
 231                 reset-names = "reset";
 232                 status = "disabled";
 233         };
 234
 235         emmc: dwmmc@ff0f0000 {
 236                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 237                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 238                 max-frequency = <150000000>;
 239                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 240                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 241                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 242                 fifo-depth = <0x100>;
 243                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 244                 resets = <&cru SRST_EMMC>;
 245                 reset-names = "reset";
 246                 status = "disabled";
 247         };
 248
 249         saradc: saradc@ff100000 {
 250                 compatible = "rockchip,saradc";
 251                 reg = <0x0 0xff100000 0x0 0x100>;
 252                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 253                 #io-channel-cells = <1>;
 254                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 255                 clock-names = "saradc", "apb_pclk";
 256                 resets = <&cru SRST_SARADC>;
 257                 reset-names = "saradc-apb";
 258                 status = "disabled";
 259         };
 260
 261         spi0: spi@ff110000 {
 262                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 263                 reg = <0x0 0xff110000 0x0 0x1000>;
 264                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 265                 clock-names = "spiclk", "apb_pclk";
 266                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 267                 pinctrl-names = "default";
 268                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 269                 #address-cells = <1>;
 270                 #size-cells = <0>;
 271                 status = "disabled";
 272         };
 273
 274         spi1: spi@ff120000 {
 275                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 276                 reg = <0x0 0xff120000 0x0 0x1000>;
 277                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 278                 clock-names = "spiclk", "apb_pclk";
 279                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 280                 pinctrl-names = "default";
 281                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 282                 #address-cells = <1>;
 283                 #size-cells = <0>;
 284                 status = "disabled";
 285         };
 286
 287         spi2: spi@ff130000 {
 288                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 289                 reg = <0x0 0xff130000 0x0 0x1000>;
 290                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 291                 clock-names = "spiclk", "apb_pclk";
 292                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 293                 pinctrl-names = "default";
 294                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 295                 #address-cells = <1>;
 296                 #size-cells = <0>;
 297                 status = "disabled";
 298         };
 299
 300         i2c2: i2c@ff140000 {
 301                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 302                 reg = <0x0 0xff140000 0x0 0x1000>;
 303                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 304                 #address-cells = <1>;
 305                 #size-cells = <0>;
 306                 clock-names = "i2c";
 307                 clocks = <&cru PCLK_I2C2>;
 308                 pinctrl-names = "default";
 309                 pinctrl-0 = <&i2c2_xfer>;
 310                 status = "disabled";
 311         };
 312
 313         i2c3: i2c@ff150000 {
 314                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 315                 reg = <0x0 0xff150000 0x0 0x1000>;
 316                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 317                 #address-cells = <1>;
 318                 #size-cells = <0>;
 319                 clock-names = "i2c";
 320                 clocks = <&cru PCLK_I2C3>;
 321                 pinctrl-names = "default";
 322                 pinctrl-0 = <&i2c3_xfer>;
 323                 status = "disabled";
 324         };
 325
 326         i2c4: i2c@ff160000 {
 327                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 328                 reg = <0x0 0xff160000 0x0 0x1000>;
 329                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 330                 #address-cells = <1>;
 331                 #size-cells = <0>;
 332                 clock-names = "i2c";
 333                 clocks = <&cru PCLK_I2C4>;
 334                 pinctrl-names = "default";
 335                 pinctrl-0 = <&i2c4_xfer>;
 336                 status = "disabled";
 337         };
 338
 339         i2c5: i2c@ff170000 {
 340                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 341                 reg = <0x0 0xff170000 0x0 0x1000>;
 342                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345                 clock-names = "i2c";
 346                 clocks = <&cru PCLK_I2C5>;
 347                 pinctrl-names = "default";
 348                 pinctrl-0 = <&i2c5_xfer>;
 349                 status = "disabled";
 350         };
 351
 352         uart0: serial@ff180000 {
 353                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 354                 reg = <0x0 0xff180000 0x0 0x100>;
 355                 clock-frequency = <24000000>;
 356                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 357                 clock-names = "baudclk", "apb_pclk";
 358                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 359                 reg-shift = <2>;
 360                 reg-io-width = <4>;
 361                 status = "disabled";
 362         };
 363
 364         uart1: serial@ff190000 {
 365                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 366                 reg = <0x0 0xff190000 0x0 0x100>;
 367                 clock-frequency = <24000000>;
 368                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 369                 clock-names = "baudclk", "apb_pclk";
 370                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 371                 reg-shift = <2>;
 372                 reg-io-width = <4>;
 373                 status = "disabled";
 374         };
 375
 376         uart3: serial@ff1b0000 {
 377                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 378                 reg = <0x0 0xff1b0000 0x0 0x100>;
 379                 clock-frequency = <24000000>;
 380                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 381                 clock-names = "baudclk", "apb_pclk";
 382                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 383                 reg-shift = <2>;
 384                 reg-io-width = <4>;
 385                 status = "disabled";
 386         };
 387
 388         uart4: serial@ff1c0000 {
 389                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 390                 reg = <0x0 0xff1c0000 0x0 0x100>;
 391                 clock-frequency = <24000000>;
 392                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 393                 clock-names = "baudclk", "apb_pclk";
 394                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 395                 reg-shift = <2>;
 396                 reg-io-width = <4>;
 397                 status = "disabled";
 398         };
 399
 400         thermal-zones {
 401                 cpu {
 402                         polling-delay-passive = <100>; /* milliseconds */
 403                         polling-delay = <5000>; /* milliseconds */
 404
 405                         thermal-sensors = <&tsadc 0>;
 406
 407                         trips {
 408                                 cpu_alert0: cpu_alert0 {
 409                                         temperature = <75000>; /* millicelsius */
 410                                         hysteresis = <2000>; /* millicelsius */
 411                                         type = "passive";
 412                                 };
 413                                 cpu_alert1: cpu_alert1 {
 414                                         temperature = <80000>; /* millicelsius */
 415                                         hysteresis = <2000>; /* millicelsius */
 416                                         type = "passive";
 417                                 };
 418                                 cpu_crit: cpu_crit {
 419                                         temperature = <95000>; /* millicelsius */
 420                                         hysteresis = <2000>; /* millicelsius */
 421                                         type = "critical";
 422                                 };
 423                         };
 424
 425                         cooling-maps {
 426                                 map0 {
 427                                         trip = <&cpu_alert0>;
 428                                         cooling-device =
 429                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 430                                         <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 431                                         <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 432                                         <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 433                                 };
 434                                 map1 {
 435                                         trip = <&cpu_alert1>;
 436                                         cooling-device =
 437                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 438                                         <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 439                                         <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 440                                         <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 441                                 };
 442                         };
 443                 };
 444
 445                 gpu {
 446                         polling-delay-passive = <100>; /* milliseconds */
 447                         polling-delay = <5000>; /* milliseconds */
 448
 449                         thermal-sensors = <&tsadc 1>;
 450
 451                         trips {
 452                                 gpu_alert0: gpu_alert0 {
 453                                         temperature = <80000>; /* millicelsius */
 454                                         hysteresis = <2000>; /* millicelsius */
 455                                         type = "passive";
 456                                 };
 457                                 gpu_crit: gpu_crit {
 458                                         temperature = <115000>; /* millicelsius */
 459                                         hysteresis = <2000>; /* millicelsius */
 460                                         type = "critical";
 461                                 };
 462                         };
 463
 464                         cooling-maps {
 465                                 map0 {
 466                                         trip = <&gpu_alert0>;
 467                                         cooling-device =
 468                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 469                                         <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 470                                         <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 471                                         <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 472                                 };
 473                         };
 474                 };
 475         };
 476
 477         tsadc: tsadc@ff280000 {
 478                 compatible = "rockchip,rk3368-tsadc";
 479                 reg = <0x0 0xff280000 0x0 0x100>;
 480                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 481                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 482                 clock-names = "tsadc", "apb_pclk";
 483                 resets = <&cru SRST_TSADC>;
 484                 reset-names = "tsadc-apb";
 485                 pinctrl-names = "init", "default", "sleep";
 486                 pinctrl-0 = <&otp_gpio>;
 487                 pinctrl-1 = <&otp_out>;
 488                 pinctrl-2 = <&otp_gpio>;
 489                 #thermal-sensor-cells = <1>;
 490                 rockchip,hw-tshut-temp = <95000>;
 491                 status = "disabled";
 492         };
 493
 494         gmac: ethernet@ff290000 {
 495                 compatible = "rockchip,rk3368-gmac";
 496                 reg = <0x0 0xff290000 0x0 0x10000>;
 497                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 498                 interrupt-names = "macirq";
 499                 rockchip,grf = <&grf>;
 500                 clocks = <&cru SCLK_MAC>,
 501                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 502                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 503                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 504                 clock-names = "stmmaceth",
 505                         "mac_clk_rx", "mac_clk_tx",
 506                         "clk_mac_ref", "clk_mac_refout",
 507                         "aclk_mac", "pclk_mac";
 508                 status = "disabled";
 509         };
 510
 511         usb_host0_ehci: usb@ff500000 {
 512                 compatible = "generic-ehci";
 513                 reg = <0x0 0xff500000 0x0 0x100>;
 514                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 515                 clocks = <&cru HCLK_HOST0>;
 516                 clock-names = "usbhost";
 517                 status = "disabled";
 518         };
 519
 520         usb_otg: usb@ff580000 {
 521                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 522                                 "snps,dwc2";
 523                 reg = <0x0 0xff580000 0x0 0x40000>;
 524                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 525                 clocks = <&cru HCLK_OTG0>;
 526                 clock-names = "otg";
 527                 dr_mode = "otg";
 528                 g-np-tx-fifo-size = <16>;
 529                 g-rx-fifo-size = <275>;
 530                 g-tx-fifo-size = <256 128 128 64 64 32>;
 531                 status = "disabled";
 532         };
 533
 534         i2c0: i2c@ff650000 {
 535                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 536                 reg = <0x0 0xff650000 0x0 0x1000>;
 537                 clocks = <&cru PCLK_I2C0>;
 538                 clock-names = "i2c";
 539                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&i2c0_xfer>;
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 status = "disabled";
 545         };
 546
 547         i2c1: i2c@ff660000 {
 548                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 549                 reg = <0x0 0xff660000 0x0 0x1000>;
 550                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 551                 #address-cells = <1>;
 552                 #size-cells = <0>;
 553                 clock-names = "i2c";
 554                 clocks = <&cru PCLK_I2C1>;
 555                 pinctrl-names = "default";
 556                 pinctrl-0 = <&i2c1_xfer>;
 557                 status = "disabled";
 558         };
 559
 560         pwm0: pwm@ff680000 {
 561                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 562                 reg = <0x0 0xff680000 0x0 0x10>;
 563                 #pwm-cells = <3>;
 564                 pinctrl-names = "default";
 565                 pinctrl-0 = <&pwm0_pin>;
 566                 clocks = <&cru PCLK_PWM1>;
 567                 clock-names = "pwm";
 568                 status = "disabled";
 569         };
 570
 571         pwm1: pwm@ff680010 {
 572                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 573                 reg = <0x0 0xff680010 0x0 0x10>;
 574                 #pwm-cells = <3>;
 575                 pinctrl-names = "default";
 576                 pinctrl-0 = <&pwm1_pin>;
 577                 clocks = <&cru PCLK_PWM1>;
 578                 clock-names = "pwm";
 579                 status = "disabled";
 580         };
 581
 582         pwm2: pwm@ff680020 {
 583                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 584                 reg = <0x0 0xff680020 0x0 0x10>;
 585                 #pwm-cells = <3>;
 586                 clocks = <&cru PCLK_PWM1>;
 587                 clock-names = "pwm";
 588                 status = "disabled";
 589         };
 590
 591         pwm3: pwm@ff680030 {
 592                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 593                 reg = <0x0 0xff680030 0x0 0x10>;
 594                 #pwm-cells = <3>;
 595                 pinctrl-names = "default";
 596                 pinctrl-0 = <&pwm3_pin>;
 597                 clocks = <&cru PCLK_PWM1>;
 598                 clock-names = "pwm";
 599                 status = "disabled";
 600         };
 601
 602         uart2: serial@ff690000 {
 603                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 604                 reg = <0x0 0xff690000 0x0 0x100>;
 605                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 606                 clock-names = "baudclk", "apb_pclk";
 607                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 608                 pinctrl-names = "default";
 609                 pinctrl-0 = <&uart2_xfer>;
 610                 reg-shift = <2>;
 611                 reg-io-width = <4>;
 612                 status = "disabled";
 613         };
 614
 615         mbox: mbox@ff6b0000 {
 616                 compatible = "rockchip,rk3368-mailbox";
 617                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 618                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 619                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 620                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 621                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 622                 clocks = <&cru PCLK_MAILBOX>;
 623                 clock-names = "pclk_mailbox";
 624                 #mbox-cells = <1>;
 625                 status = "disabled";
 626         };
 627
 628         pmugrf: syscon@ff738000 {
 629                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
 630                 reg = <0x0 0xff738000 0x0 0x1000>;
 631
 632                 pmu_io_domains: io-domains {
 633                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
 634                         status = "disabled";
 635                 };
 636
 637                 reboot-mode {
 638                         compatible = "syscon-reboot-mode";
 639                         offset = <0x200>;
 640                         mode-normal = <BOOT_NORMAL>;
 641                         mode-recovery = <BOOT_RECOVERY>;
 642                         mode-bootloader = <BOOT_FASTBOOT>;
 643                         mode-loader = <BOOT_BL_DOWNLOAD>;
 644                 };
 645         };
 646
 647         cru: clock-controller@ff760000 {
 648                 compatible = "rockchip,rk3368-cru";
 649                 reg = <0x0 0xff760000 0x0 0x1000>;
 650                 rockchip,grf = <&grf>;
 651                 #clock-cells = <1>;
 652                 #reset-cells = <1>;
 653         };
 654
 655         grf: syscon@ff770000 {
 656                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
 657                 reg = <0x0 0xff770000 0x0 0x1000>;
 658
 659                 io_domains: io-domains {
 660                         compatible = "rockchip,rk3368-io-voltage-domain";
 661                         status = "disabled";
 662                 };
 663         };
 664
 665         wdt: watchdog@ff800000 {
 666                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 667                 reg = <0x0 0xff800000 0x0 0x100>;
 668                 clocks = <&cru PCLK_WDT>;
 669                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 670                 status = "disabled";
 671         };
 672
 673         timer@ff810000 {
 674                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
 675                 reg = <0x0 0xff810000 0x0 0x20>;
 676                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 677         };
 678
 679         spdif: spdif@ff880000 {
 680                 compatible = "rockchip,rk3368-spdif";
 681                 reg = <0x0 0xff880000 0x0 0x1000>;
 682                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 683                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 684                 clock-names = "mclk", "hclk";
 685                 dmas = <&dmac_bus 3>;
 686                 dma-names = "tx";
 687                 pinctrl-names = "default";
 688                 pinctrl-0 = <&spdif_tx>;
 689                 status = "disabled";
 690         };
 691
 692         i2s_2ch: i2s-2ch@ff890000 {
 693                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 694                 reg = <0x0 0xff890000 0x0 0x1000>;
 695                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 696                 clock-names = "i2s_clk", "i2s_hclk";
 697                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 698                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 699                 dma-names = "tx", "rx";
 700                 status = "disabled";
 701         };
 702
 703         i2s_8ch: i2s-8ch@ff898000 {
 704                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 705                 reg = <0x0 0xff898000 0x0 0x1000>;
 706                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 707                 clock-names = "i2s_clk", "i2s_hclk";
 708                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 709                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 710                 dma-names = "tx", "rx";
 711                 pinctrl-names = "default";
 712                 pinctrl-0 = <&i2s_8ch_bus>;
 713                 status = "disabled";
 714         };
 715
 716         iep_mmu: iommu@ff900800 {
 717                 compatible = "rockchip,iommu";
 718                 reg = <0x0 0xff900800 0x0 0x100>;
 719                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 720                 interrupt-names = "iep_mmu";
 721                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 722                 clock-names = "aclk", "iface";
 723                 #iommu-cells = <0>;
 724                 status = "disabled";
 725         };
 726
 727         isp_mmu: iommu@ff914000 {
 728                 compatible = "rockchip,iommu";
 729                 reg = <0x0 0xff914000 0x0 0x100>,
 730                       <0x0 0xff915000 0x0 0x100>;
 731                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 732                 interrupt-names = "isp_mmu";
 733                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
 734                 clock-names = "aclk", "iface";
 735                 #iommu-cells = <0>;
 736                 rockchip,disable-mmu-reset;
 737                 status = "disabled";
 738         };
 739
 740         vop_mmu: iommu@ff930300 {
 741                 compatible = "rockchip,iommu";
 742                 reg = <0x0 0xff930300 0x0 0x100>;
 743                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 744                 interrupt-names = "vop_mmu";
 745                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 746                 clock-names = "aclk", "iface";
 747                 #iommu-cells = <0>;
 748                 status = "disabled";
 749         };
 750
 751         hevc_mmu: iommu@ff9a0440 {
 752                 compatible = "rockchip,iommu";
 753                 reg = <0x0 0xff9a0440 0x0 0x40>,
 754                       <0x0 0xff9a0480 0x0 0x40>;
 755                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 756                 interrupt-names = "hevc_mmu";
 757                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
 758                 clock-names = "aclk", "iface";
 759                 #iommu-cells = <0>;
 760                 status = "disabled";
 761         };
 762
 763         vpu_mmu: iommu@ff9a0800 {
 764                 compatible = "rockchip,iommu";
 765                 reg = <0x0 0xff9a0800 0x0 0x100>;
 766                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 767                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 768                 interrupt-names = "vepu_mmu", "vdpu_mmu";
 769                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
 770                 clock-names = "aclk", "iface";
 771                 #iommu-cells = <0>;
 772                 status = "disabled";
 773         };
 774
 775         efuse256: efuse@ffb00000 {
 776                 compatible = "rockchip,rk3368-efuse";
 777                 reg = <0x0 0xffb00000 0x0 0x20>;
 778                 #address-cells = <1>;
 779                 #size-cells = <1>;
 780                 clocks = <&cru PCLK_EFUSE256>;
 781                 clock-names = "pclk_efuse";
 782
 783                 cpu_leakage: cpu-leakage@17 {
 784                         reg = <0x17 0x1>;
 785                 };
 786                 temp_adjust: temp-adjust@1f {
 787                         reg = <0x1f 0x1>;
 788                 };
 789         };
 790
 791         gic: interrupt-controller@ffb71000 {
 792                 compatible = "arm,gic-400";
 793                 interrupt-controller;
 794                 #interrupt-cells = <3>;
 795                 #address-cells = <0>;
 796
 797                 reg = <0x0 0xffb71000 0x0 0x1000>,
 798                       <0x0 0xffb72000 0x0 0x2000>,
 799                       <0x0 0xffb74000 0x0 0x2000>,
 800                       <0x0 0xffb76000 0x0 0x2000>;
 801                 interrupts = <GIC_PPI 9
 802                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 803         };
 804
 805         pinctrl: pinctrl {
 806                 compatible = "rockchip,rk3368-pinctrl";
 807                 rockchip,grf = <&grf>;
 808                 rockchip,pmu = <&pmugrf>;
 809                 #address-cells = <0x2>;
 810                 #size-cells = <0x2>;
 811                 ranges;
 812
 813                 gpio0: gpio0@ff750000 {
 814                         compatible = "rockchip,gpio-bank";
 815                         reg = <0x0 0xff750000 0x0 0x100>;
 816                         clocks = <&cru PCLK_GPIO0>;
 817                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
 818
 819                         gpio-controller;
 820                         #gpio-cells = <0x2>;
 821
 822                         interrupt-controller;
 823                         #interrupt-cells = <0x2>;
 824                 };
 825
 826                 gpio1: gpio1@ff780000 {
 827                         compatible = "rockchip,gpio-bank";
 828                         reg = <0x0 0xff780000 0x0 0x100>;
 829                         clocks = <&cru PCLK_GPIO1>;
 830                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
 831
 832                         gpio-controller;
 833                         #gpio-cells = <0x2>;
 834
 835                         interrupt-controller;
 836                         #interrupt-cells = <0x2>;
 837                 };
 838
 839                 gpio2: gpio2@ff790000 {
 840                         compatible = "rockchip,gpio-bank";
 841                         reg = <0x0 0xff790000 0x0 0x100>;
 842                         clocks = <&cru PCLK_GPIO2>;
 843                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
 844
 845                         gpio-controller;
 846                         #gpio-cells = <0x2>;
 847
 848                         interrupt-controller;
 849                         #interrupt-cells = <0x2>;
 850                 };
 851
 852                 gpio3: gpio3@ff7a0000 {
 853                         compatible = "rockchip,gpio-bank";
 854                         reg = <0x0 0xff7a0000 0x0 0x100>;
 855                         clocks = <&cru PCLK_GPIO3>;
 856                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
 857
 858                         gpio-controller;
 859                         #gpio-cells = <0x2>;
 860
 861                         interrupt-controller;
 862                         #interrupt-cells = <0x2>;
 863                 };
 864
 865                 pcfg_pull_up: pcfg-pull-up {
 866                         bias-pull-up;
 867                 };
 868
 869                 pcfg_pull_down: pcfg-pull-down {
 870                         bias-pull-down;
 871                 };
 872
 873                 pcfg_pull_none: pcfg-pull-none {
 874                         bias-disable;
 875                 };
 876
 877                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 878                         bias-disable;
 879                         drive-strength = <12>;
 880                 };
 881
 882                 emmc {
 883                         emmc_clk: emmc-clk {
 884                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 885                         };
 886
 887                         emmc_cmd: emmc-cmd {
 888                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
 889                         };
 890
 891                         emmc_pwr: emmc-pwr {
 892                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
 893                         };
 894
 895                         emmc_bus1: emmc-bus1 {
 896                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
 897                         };
 898
 899                         emmc_bus4: emmc-bus4 {
 900                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 901                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 902                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 903                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
 904                         };
 905
 906                         emmc_bus8: emmc-bus8 {
 907                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 908                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 909                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 910                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
 911                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
 912                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
 913                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
 914                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
 915                         };
 916                 };
 917
 918                 gmac {
 919                         rgmii_pins: rgmii-pins {
 920                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
 921                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
 922                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
 923                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
 924                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
 925                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
 926                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
 927                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
 928                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
 929                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
 930                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
 931                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
 932                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
 933                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
 934                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
 935                         };
 936
 937                         rmii_pins: rmii-pins {
 938                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
 939                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
 940                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
 941                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
 942                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
 943                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
 944                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
 945                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
 946                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
 947                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
 948                         };
 949                 };
 950
 951                 i2c0 {
 952                         i2c0_xfer: i2c0-xfer {
 953                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
 954                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
 955                         };
 956                 };
 957
 958                 i2c1 {
 959                         i2c1_xfer: i2c1-xfer {
 960                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
 961                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
 962                         };
 963                 };
 964
 965                 i2c2 {
 966                         i2c2_xfer: i2c2-xfer {
 967                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
 968                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
 969                         };
 970                 };
 971
 972                 i2c3 {
 973                         i2c3_xfer: i2c3-xfer {
 974                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
 975                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
 976                         };
 977                 };
 978
 979                 i2c4 {
 980                         i2c4_xfer: i2c4-xfer {
 981                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
 982                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
 983                         };
 984                 };
 985
 986                 i2c5 {
 987                         i2c5_xfer: i2c5-xfer {
 988                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
 989                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
 990                         };
 991                 };
 992
 993                 i2s {
 994                         i2s_8ch_bus: i2s-8ch-bus {
 995                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
 996                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
 997                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
 998                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
 999                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1000                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1001                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1002                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1003                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1004                         };
1005                 };
1006
1007                 pwm0 {
1008                         pwm0_pin: pwm0-pin {
1009                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1010                         };
1011                 };
1012
1013                 pwm1 {
1014                         pwm1_pin: pwm1-pin {
1015                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1016                         };
1017                 };
1018
1019                 pwm3 {
1020                         pwm3_pin: pwm3-pin {
1021                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1022                         };
1023                 };
1024
1025                 sdio0 {
1026                         sdio0_bus1: sdio0-bus1 {
1027                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1028                         };
1029
1030                         sdio0_bus4: sdio0-bus4 {
1031                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1032                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1033                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1034                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1035                         };
1036
1037                         sdio0_cmd: sdio0-cmd {
1038                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1039                         };
1040
1041                         sdio0_clk: sdio0-clk {
1042                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1043                         };
1044
1045                         sdio0_cd: sdio0-cd {
1046                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1047                         };
1048
1049                         sdio0_wp: sdio0-wp {
1050                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1051                         };
1052
1053                         sdio0_pwr: sdio0-pwr {
1054                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1055                         };
1056
1057                         sdio0_bkpwr: sdio0-bkpwr {
1058                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1059                         };
1060
1061                         sdio0_int: sdio0-int {
1062                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1063                         };
1064                 };
1065
1066                 sdmmc {
1067                         sdmmc_clk: sdmmc-clk {
1068                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1069                         };
1070
1071                         sdmmc_cmd: sdmmc-cmd {
1072                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1073                         };
1074
1075                         sdmmc_cd: sdmmc-cd {
1076                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1077                         };
1078
1079                         sdmmc_bus1: sdmmc-bus1 {
1080                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1081                         };
1082
1083                         sdmmc_bus4: sdmmc-bus4 {
1084                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1085                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1086                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1087                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1088                         };
1089                 };
1090
1091                 spdif {
1092                         spdif_tx: spdif-tx {
1093                                 rockchip,pins = <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
1094                         };
1095                 };
1096
1097                 spi0 {
1098                         spi0_clk: spi0-clk {
1099                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1100                         };
1101                         spi0_cs0: spi0-cs0 {
1102                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1103                         };
1104                         spi0_cs1: spi0-cs1 {
1105                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1106                         };
1107                         spi0_tx: spi0-tx {
1108                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1109                         };
1110                         spi0_rx: spi0-rx {
1111                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1112                         };
1113                 };
1114
1115                 spi1 {
1116                         spi1_clk: spi1-clk {
1117                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1118                         };
1119                         spi1_cs0: spi1-cs0 {
1120                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1121                         };
1122                         spi1_cs1: spi1-cs1 {
1123                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1124                         };
1125                         spi1_rx: spi1-rx {
1126                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1127                         };
1128                         spi1_tx: spi1-tx {
1129                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1130                         };
1131                 };
1132
1133                 spi2 {
1134                         spi2_clk: spi2-clk {
1135                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1136                         };
1137                         spi2_cs0: spi2-cs0 {
1138                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1139                         };
1140                         spi2_rx: spi2-rx {
1141                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1142                         };
1143                         spi2_tx: spi2-tx {
1144                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1145                         };
1146                 };
1147
1148                 tsadc {
1149                         otp_gpio: otp-gpio {
1150                                 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1151                         };
1152
1153                         otp_out: otp-out {
1154                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1155                         };
1156                 };
1157
1158                 uart0 {
1159                         uart0_xfer: uart0-xfer {
1160                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1161                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1162                         };
1163
1164                         uart0_cts: uart0-cts {
1165                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1166                         };
1167
1168                         uart0_rts: uart0-rts {
1169                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1170                         };
1171                 };
1172
1173                 uart1 {
1174                         uart1_xfer: uart1-xfer {
1175                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1176                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1177                         };
1178
1179                         uart1_cts: uart1-cts {
1180                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1181                         };
1182
1183                         uart1_rts: uart1-rts {
1184                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1185                         };
1186                 };
1187
1188                 uart2 {
1189                         uart2_xfer: uart2-xfer {
1190                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1191                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1192                         };
1193                         /* no rts / cts for uart2 */
1194                 };
1195
1196                 uart3 {
1197                         uart3_xfer: uart3-xfer {
1198                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1199                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1200                         };
1201
1202                         uart3_cts: uart3-cts {
1203                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1204                         };
1205
1206                         uart3_rts: uart3-rts {
1207                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1208                         };
1209                 };
1210
1211                 uart4 {
1212                         uart4_xfer: uart4-xfer {
1213                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1214                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1215                         };
1216
1217                         uart4_cts: uart4-cts {
1218                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1219                         };
1220
1221                         uart4_rts: uart4-rts {
1222                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1223                         };
1224                 };
1225         };
1226 };