arch/arm64/boot/dts/renesas/r8a77970.dtsi

   1 /*
   2  * Device Tree Source for the r8a77970 SoC
   3  *
   4  * Copyright (C) 2016-2017 Renesas Electronics Corp.
   5  * Copyright (C) 2017 Cogent Embedded, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  15
  16 / {
  17         compatible = "renesas,r8a77970";
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         psci {
  22                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  23                 method = "smc";
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 a53_0: cpu@0 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a53", "arm,armv8";
  33                         reg = <0>;
  34                         clocks = <&cpg CPG_CORE 0>;
  35                         power-domains = <&sysc 5>;
  36                         next-level-cache = <&L2_CA53>;
  37                         enable-method = "psci";
  38                 };
  39
  40                 L2_CA53: cache-controller {
  41                         compatible = "cache";
  42                         power-domains = <&sysc 21>;
  43                         cache-unified;
  44                         cache-level = <2>;
  45                 };
  46         };
  47
  48         extal_clk: extal {
  49                 compatible = "fixed-clock";
  50                 #clock-cells = <0>;
  51                 /* This value must be overridden by the board */
  52                 clock-frequency = <0>;
  53         };
  54
  55         extalr_clk: extalr {
  56                 compatible = "fixed-clock";
  57                 #clock-cells = <0>;
  58                 /* This value must be overridden by the board */
  59                 clock-frequency = <0>;
  60         };
  61
  62         /* External SCIF clock - to be overridden by boards that provide it */
  63         scif_clk: scif {
  64                 compatible = "fixed-clock";
  65                 #clock-cells = <0>;
  66                 clock-frequency = <0>;
  67         };
  68
  69         soc {
  70                 compatible = "simple-bus";
  71                 interrupt-parent = <&gic>;
  72
  73                 #address-cells = <2>;
  74                 #size-cells = <2>;
  75                 ranges;
  76
  77                 gic: interrupt-controller@f1010000 {
  78                         compatible = "arm,gic-400";
  79                         #interrupt-cells = <3>;
  80                         #address-cells = <0>;
  81                         interrupt-controller;
  82                         reg = <0 0xf1010000 0 0x1000>,
  83                               <0 0xf1020000 0 0x20000>,
  84                               <0 0xf1040000 0 0x20000>,
  85                               <0 0xf1060000 0 0x20000>;
  86                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
  87                                       IRQ_TYPE_LEVEL_HIGH)>;
  88                         clocks = <&cpg CPG_MOD 408>;
  89                         clock-names = "clk";
  90                         power-domains = <&sysc 32>;
  91                         resets = <&cpg 408>;
  92                 };
  93
  94                 timer {
  95                         compatible = "arm,armv8-timer";
  96                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
  97                                                   IRQ_TYPE_LEVEL_LOW)>,
  98                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
  99                                                   IRQ_TYPE_LEVEL_LOW)>,
 100                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
 101                                                   IRQ_TYPE_LEVEL_LOW)>,
 102                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
 103                                                   IRQ_TYPE_LEVEL_LOW)>;
 104                 };
 105
 106                 cpg: clock-controller@e6150000 {
 107                         compatible = "renesas,r8a77970-cpg-mssr";
 108                         reg = <0 0xe6150000 0 0x1000>;
 109                         clocks = <&extal_clk>, <&extalr_clk>;
 110                         clock-names = "extal", "extalr";
 111                         #clock-cells = <2>;
 112                         #power-domain-cells = <0>;
 113                         #reset-cells = <1>;
 114                 };
 115
 116                 rst: reset-controller@e6160000 {
 117                         compatible = "renesas,r8a77970-rst";
 118                         reg = <0 0xe6160000 0 0x200>;
 119                 };
 120
 121                 sysc: system-controller@e6180000 {
 122                         compatible = "renesas,r8a77970-sysc";
 123                         reg = <0 0xe6180000 0 0x440>;
 124                         #power-domain-cells = <1>;
 125                 };
 126
 127                 intc_ex: interrupt-controller@e61c0000 {
 128                         compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
 129                         #interrupt-cells = <2>;
 130                         interrupt-controller;
 131                         reg = <0 0xe61c0000 0 0x200>;
 132                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
 133                                       GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
 134                                       GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
 135                                       GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
 136                                       GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
 137                                       GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 138                         clocks = <&cpg CPG_MOD 407>;
 139                         power-domains = <&sysc 32>;
 140                         resets = <&cpg 407>;
 141                 };
 142
 143                 prr: chipid@fff00044 {
 144                         compatible = "renesas,prr";
 145                         reg = <0 0xfff00044 0 4>;
 146                 };
 147
 148                 dmac1: dma-controller@e7300000 {
 149                         compatible = "renesas,dmac-r8a77970",
 150                                      "renesas,rcar-dmac";
 151                         reg = <0 0xe7300000 0 0x10000>;
 152                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 153                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 154                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 155                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 156                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 157                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 158                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 159                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 160                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
 161                         interrupt-names = "error",
 162                                           "ch0", "ch1", "ch2", "ch3",
 163                                           "ch4", "ch5", "ch6", "ch7";
 164                         clocks = <&cpg CPG_MOD 218>;
 165                         clock-names = "fck";
 166                         power-domains = <&sysc 32>;
 167                         resets = <&cpg 218>;
 168                         #dma-cells = <1>;
 169                         dma-channels = <8>;
 170                 };
 171
 172                 dmac2: dma-controller@e7310000 {
 173                         compatible = "renesas,dmac-r8a77970",
 174                                      "renesas,rcar-dmac";
 175                         reg = <0 0xe7310000 0 0x10000>;
 176                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
 177                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 178                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 179                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 180                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 181                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 182                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 183                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
 184                                       GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 185                         interrupt-names = "error",
 186                                           "ch0", "ch1", "ch2", "ch3",
 187                                           "ch4", "ch5", "ch6", "ch7";
 188                         clocks = <&cpg CPG_MOD 217>;
 189                         clock-names = "fck";
 190                         power-domains = <&sysc 32>;
 191                         resets = <&cpg 217>;
 192                         #dma-cells = <1>;
 193                         dma-channels = <8>;
 194                 };
 195
 196                 hscif0: serial@e6540000 {
 197                         compatible = "renesas,hscif-r8a77970",
 198                                      "renesas,rcar-gen3-hscif",
 199                                      "renesas,hscif";
 200                         reg = <0 0xe6540000 0 96>;
 201                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 202                         clocks = <&cpg CPG_MOD 520>,
 203                                  <&cpg CPG_CORE 9>,
 204                                  <&scif_clk>;
 205                         clock-names = "fck", "brg_int", "scif_clk";
 206                         dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 207                                <&dmac2 0x31>, <&dmac2 0x30>;
 208                         dma-names = "tx", "rx", "tx", "rx";
 209                         power-domains = <&sysc 32>;
 210                         resets = <&cpg 520>;
 211                         status = "disabled";
 212                 };
 213
 214                 hscif1: serial@e6550000 {
 215                         compatible = "renesas,hscif-r8a77970",
 216                                      "renesas,rcar-gen3-hscif",
 217                                      "renesas,hscif";
 218                         reg = <0 0xe6550000 0 96>;
 219                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 220                         clocks = <&cpg CPG_MOD 519>,
 221                                  <&cpg CPG_CORE 9>,
 222                                  <&scif_clk>;
 223                         clock-names = "fck", "brg_int", "scif_clk";
 224                         dmas = <&dmac1 0x33>, <&dmac1 0x32>,
 225                                <&dmac2 0x33>, <&dmac2 0x32>;
 226                         dma-names = "tx", "rx", "tx", "rx";
 227                         power-domains = <&sysc 32>;
 228                         resets = <&cpg 519>;
 229                         status = "disabled";
 230                 };
 231
 232                 hscif2: serial@e6560000 {
 233                         compatible = "renesas,hscif-r8a77970",
 234                                      "renesas,rcar-gen3-hscif",
 235                                      "renesas,hscif";
 236                         reg = <0 0xe6560000 0 96>;
 237                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 238                         clocks = <&cpg CPG_MOD 518>,
 239                                  <&cpg CPG_CORE 9>,
 240                                  <&scif_clk>;
 241                         clock-names = "fck", "brg_int", "scif_clk";
 242                         dmas = <&dmac1 0x35>, <&dmac1 0x34>,
 243                                <&dmac2 0x35>, <&dmac2 0x34>;
 244                         dma-names = "tx", "rx", "tx", "rx";
 245                         power-domains = <&sysc 32>;
 246                         resets = <&cpg 518>;
 247                         status = "disabled";
 248                 };
 249
 250                 hscif3: serial@e66a0000 {
 251                         compatible = "renesas,hscif-r8a77970",
 252                                      "renesas,rcar-gen3-hscif", "renesas,hscif";
 253                         reg = <0 0xe66a0000 0 96>;
 254                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 255                         clocks = <&cpg CPG_MOD 517>,
 256                                  <&cpg CPG_CORE 9>,
 257                                  <&scif_clk>;
 258                         clock-names = "fck", "brg_int", "scif_clk";
 259                         dmas = <&dmac1 0x37>, <&dmac1 0x36>,
 260                                <&dmac2 0x37>, <&dmac2 0x36>;
 261                         dma-names = "tx", "rx", "tx", "rx";
 262                         power-domains = <&sysc 32>;
 263                         resets = <&cpg 517>;
 264                         status = "disabled";
 265                 };
 266
 267                 scif0: serial@e6e60000 {
 268                         compatible = "renesas,scif-r8a77970",
 269                                      "renesas,rcar-gen3-scif",
 270                                      "renesas,scif";
 271                         reg = <0 0xe6e60000 0 64>;
 272                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 273                         clocks = <&cpg CPG_MOD 207>,
 274                                  <&cpg CPG_CORE 9>,
 275                                  <&scif_clk>;
 276                         clock-names = "fck", "brg_int", "scif_clk";
 277                         dmas = <&dmac1 0x51>, <&dmac1 0x50>,
 278                                <&dmac2 0x51>, <&dmac2 0x50>;
 279                         dma-names = "tx", "rx", "tx", "rx";
 280                         power-domains = <&sysc 32>;
 281                         resets = <&cpg 207>;
 282                         status = "disabled";
 283                 };
 284
 285                 scif1: serial@e6e68000 {
 286                         compatible = "renesas,scif-r8a77970",
 287                                      "renesas,rcar-gen3-scif",
 288                                      "renesas,scif";
 289                         reg = <0 0xe6e68000 0 64>;
 290                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 291                         clocks = <&cpg CPG_MOD 206>,
 292                                  <&cpg CPG_CORE 9>,
 293                                  <&scif_clk>;
 294                         clock-names = "fck", "brg_int", "scif_clk";
 295                         dmas = <&dmac1 0x53>, <&dmac1 0x52>,
 296                                <&dmac2 0x53>, <&dmac2 0x52>;
 297                         dma-names = "tx", "rx", "tx", "rx";
 298                         power-domains = <&sysc 32>;
 299                         resets = <&cpg 206>;
 300                         status = "disabled";
 301                 };
 302
 303                 scif3: serial@e6c50000 {
 304                         compatible = "renesas,scif-r8a77970",
 305                                      "renesas,rcar-gen3-scif",
 306                                      "renesas,scif";
 307                         reg = <0 0xe6c50000 0 64>;
 308                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 309                         clocks = <&cpg CPG_MOD 204>,
 310                                  <&cpg CPG_CORE 9>,
 311                                  <&scif_clk>;
 312                         clock-names = "fck", "brg_int", "scif_clk";
 313                         dmas = <&dmac1 0x57>, <&dmac1 0x56>,
 314                                <&dmac2 0x57>, <&dmac2 0x56>;
 315                         dma-names = "tx", "rx", "tx", "rx";
 316                         power-domains = <&sysc 32>;
 317                         resets = <&cpg 204>;
 318                         status = "disabled";
 319                 };
 320
 321                 scif4: serial@e6c40000 {
 322                         compatible = "renesas,scif-r8a77970",
 323                                      "renesas,rcar-gen3-scif", "renesas,scif";
 324                         reg = <0 0xe6c40000 0 64>;
 325                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 326                         clocks = <&cpg CPG_MOD 203>,
 327                                  <&cpg CPG_CORE 9>,
 328                                  <&scif_clk>;
 329                         clock-names = "fck", "brg_int", "scif_clk";
 330                         dmas = <&dmac1 0x59>, <&dmac1 0x58>,
 331                                <&dmac2 0x59>, <&dmac2 0x58>;
 332                         dma-names = "tx", "rx", "tx", "rx";
 333                         power-domains = <&sysc 32>;
 334                         resets = <&cpg 203>;
 335                         status = "disabled";
 336                 };
 337
 338                 avb: ethernet@e6800000 {
 339                         compatible = "renesas,etheravb-r8a77970",
 340                                      "renesas,etheravb-rcar-gen3";
 341                         reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
 342                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 343                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 344                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 345                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 346                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 347                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 348                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 349                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 350                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 351                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 352                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 353                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 354                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 355                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 356                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 357                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 358                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 359                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 360                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 361                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 362                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 363                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 364                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 365                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 366                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 367                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 368                                           "ch4", "ch5", "ch6", "ch7",
 369                                           "ch8", "ch9", "ch10", "ch11",
 370                                           "ch12", "ch13", "ch14", "ch15",
 371                                           "ch16", "ch17", "ch18", "ch19",
 372                                           "ch20", "ch21", "ch22", "ch23",
 373                                           "ch24";
 374                         clocks = <&cpg CPG_MOD 812>;
 375                         power-domains = <&sysc 32>;
 376                         resets = <&cpg 812>;
 377                         phy-mode = "rgmii-id";
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                 };
 381         };
 382 };