arch/arm64/boot/dts/qcom/qcs404.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2018, Linaro Limited
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
   6 #include <dt-bindings/clock/qcom,rpmcc.h>
   7
   8 / {
   9         interrupt-parent = <&intc>;
  10
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         chosen { };
  15
  16         clocks {
  17                 xo_board: xo-board {
  18                         compatible = "fixed-clock";
  19                         #clock-cells = <0>;
  20                         clock-frequency = <19200000>;
  21                 };
  22         };
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 CPU0: cpu@100 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a53";
  31                         reg = <0x100>;
  32                         enable-method = "psci";
  33                         next-level-cache = <&L2_0>;
  34                 };
  35
  36                 CPU1: cpu@101 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a53";
  39                         reg = <0x101>;
  40                         enable-method = "psci";
  41                         next-level-cache = <&L2_0>;
  42                 };
  43
  44                 CPU2: cpu@102 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a53";
  47                         reg = <0x102>;
  48                         enable-method = "psci";
  49                         next-level-cache = <&L2_0>;
  50                 };
  51
  52                 CPU3: cpu@103 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a53";
  55                         reg = <0x103>;
  56                         enable-method = "psci";
  57                         next-level-cache = <&L2_0>;
  58                 };
  59
  60                 L2_0: l2-cache {
  61                         compatible = "cache";
  62                         cache-level = <2>;
  63                 };
  64         };
  65
  66         firmware {
  67                 scm: scm {
  68                         compatible = "qcom,scm-qcs404", "qcom,scm";
  69                         #reset-cells = <1>;
  70                 };
  71         };
  72
  73         memory@80000000 {
  74                 device_type = "memory";
  75                 /* We expect the bootloader to fill in the size */
  76                 reg = <0 0x80000000 0 0>;
  77         };
  78
  79         psci {
  80                 compatible = "arm,psci-1.0";
  81                 method = "smc";
  82         };
  83
  84         remoteproc_adsp: remoteproc-adsp {
  85                 compatible = "qcom,qcs404-adsp-pas";
  86
  87                 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
  88                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
  89                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
  90                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
  91                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
  92                 interrupt-names = "wdog", "fatal", "ready",
  93                                   "handover", "stop-ack";
  94
  95                 clocks = <&xo_board>;
  96                 clock-names = "xo";
  97
  98                 memory-region = <&adsp_fw_mem>;
  99
 100                 qcom,smem-states = <&adsp_smp2p_out 0>;
 101                 qcom,smem-state-names = "stop";
 102
 103                 status = "disabled";
 104
 105                 glink-edge {
 106                         interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
 107
 108                         qcom,remote-pid = <2>;
 109                         mboxes = <&apcs_glb 8>;
 110
 111                         label = "adsp";
 112                 };
 113         };
 114
 115         remoteproc_cdsp: remoteproc-cdsp {
 116                 compatible = "qcom,qcs404-cdsp-pas";
 117
 118                 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
 119                                       <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 120                                       <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 121                                       <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 122                                       <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 123                 interrupt-names = "wdog", "fatal", "ready",
 124                                   "handover", "stop-ack";
 125
 126                 clocks = <&xo_board>;
 127                 clock-names = "xo";
 128
 129                 memory-region = <&cdsp_fw_mem>;
 130
 131                 qcom,smem-states = <&cdsp_smp2p_out 0>;
 132                 qcom,smem-state-names = "stop";
 133
 134                 status = "disabled";
 135
 136                 glink-edge {
 137                         interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
 138
 139                         qcom,remote-pid = <5>;
 140                         mboxes = <&apcs_glb 12>;
 141
 142                         label = "cdsp";
 143                 };
 144         };
 145
 146         remoteproc_wcss: remoteproc-wcss {
 147                 compatible = "qcom,qcs404-wcss-pas";
 148
 149                 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
 150                                       <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 151                                       <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 152                                       <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 153                                       <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 154                 interrupt-names = "wdog", "fatal", "ready",
 155                                   "handover", "stop-ack";
 156
 157                 clocks = <&xo_board>;
 158                 clock-names = "xo";
 159
 160                 memory-region = <&wlan_fw_mem>;
 161
 162                 qcom,smem-states = <&wcss_smp2p_out 0>;
 163                 qcom,smem-state-names = "stop";
 164
 165                 status = "disabled";
 166
 167                 glink-edge {
 168                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 169
 170                         qcom,remote-pid = <1>;
 171                         mboxes = <&apcs_glb 16>;
 172
 173                         label = "wcss";
 174                 };
 175         };
 176
 177         reserved-memory {
 178                 #address-cells = <2>;
 179                 #size-cells = <2>;
 180                 ranges;
 181
 182                 memory@85600000 {
 183                         reg = <0 0x85600000 0 0x90000>;
 184                         no-map;
 185                 };
 186
 187                 smem_region: memory@85f00000 {
 188                         reg = <0 0x85f00000 0 0x200000>;
 189                         no-map;
 190                 };
 191
 192                 memory@86100000 {
 193                         reg = <0 0x86100000 0 0x300000>;
 194                         no-map;
 195                 };
 196
 197                 wlan_fw_mem: memory@86400000 {
 198                         reg = <0 0x86400000 0 0x1c00000>;
 199                         no-map;
 200                 };
 201
 202                 adsp_fw_mem: memory@88000000 {
 203                         reg = <0 0x88000000 0 0x1a00000>;
 204                         no-map;
 205                 };
 206
 207                 cdsp_fw_mem: memory@89a00000 {
 208                         reg = <0 0x89a00000 0 0x600000>;
 209                         no-map;
 210                 };
 211
 212                 wlan_msa_mem: memory@8a000000 {
 213                         reg = <0 0x8a000000 0 0x100000>;
 214                         no-map;
 215                 };
 216         };
 217
 218         rpm-glink {
 219                 compatible = "qcom,glink-rpm";
 220
 221                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 222                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 223                 mboxes = <&apcs_glb 0>;
 224
 225                 rpm_requests: glink-channel {
 226                         compatible = "qcom,rpm-qcs404";
 227                         qcom,glink-channels = "rpm_requests";
 228
 229                         rpmcc: clock-controller {
 230                                 compatible = "qcom,rpmcc-qcs404";
 231                                 #clock-cells = <1>;
 232                         };
 233                 };
 234         };
 235
 236         smem {
 237                 compatible = "qcom,smem";
 238
 239                 memory-region = <&smem_region>;
 240                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 241
 242                 hwlocks = <&tcsr_mutex 3>;
 243         };
 244
 245         tcsr_mutex: hwlock {
 246                 compatible = "qcom,tcsr-mutex";
 247                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 248                 #hwlock-cells = <1>;
 249         };
 250
 251         soc: soc@0 {
 252                 #address-cells = <1>;
 253                 #size-cells = <1>;
 254                 ranges = <0 0 0 0xffffffff>;
 255                 compatible = "simple-bus";
 256
 257                 rpm_msg_ram: memory@60000 {
 258                         compatible = "qcom,rpm-msg-ram";
 259                         reg = <0x00060000 0x6000>;
 260                 };
 261
 262                 rng: rng@e3000 {
 263                         compatible = "qcom,prng-ee";
 264                         reg = <0x000e3000 0x1000>;
 265                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 266                         clock-names = "core";
 267                 };
 268
 269                 tlmm: pinctrl@1000000 {
 270                         compatible = "qcom,qcs404-pinctrl";
 271                         reg = <0x01000000 0x200000>,
 272                               <0x01300000 0x200000>,
 273                               <0x07b00000 0x200000>;
 274                         reg-names = "south", "north", "east";
 275                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 276                         gpio-ranges = <&tlmm 0 0 120>;
 277                         gpio-controller;
 278                         #gpio-cells = <2>;
 279                         interrupt-controller;
 280                         #interrupt-cells = <2>;
 281
 282                         blsp1_i2c0_default: blsp1-i2c0-default {
 283                                 pins = "gpio32", "gpio33";
 284                                 function = "blsp_i2c0";
 285                         };
 286
 287                         blsp1_i2c1_default: blsp1-i2c1-default {
 288                                 pins = "gpio24", "gpio25";
 289                                 function = "blsp_i2c1";
 290                         };
 291
 292                         blsp1_i2c2_default: blsp1-i2c2-default {
 293                                 sda {
 294                                         pins = "gpio19";
 295                                         function = "blsp_i2c_sda_a2";
 296                                 };
 297
 298                                 scl {
 299                                         pins = "gpio20";
 300                                         function = "blsp_i2c_scl_a2";
 301                                 };
 302                         };
 303
 304                         blsp1_i2c3_default: blsp1-i2c3-default {
 305                                 pins = "gpio84", "gpio85";
 306                                 function = "blsp_i2c3";
 307                         };
 308
 309                         blsp1_i2c4_default: blsp1-i2c4-default {
 310                                 pins = "gpio117", "gpio118";
 311                                 function = "blsp_i2c4";
 312                         };
 313
 314                         blsp1_uart0_default: blsp1-uart0-default {
 315                                 pins = "gpio30", "gpio31", "gpio32", "gpio33";
 316                                 function = "blsp_uart0";
 317                         };
 318
 319                         blsp1_uart1_default: blsp1-uart1-default {
 320                                 pins = "gpio22", "gpio23";
 321                                 function = "blsp_uart1";
 322                         };
 323
 324                         blsp1_uart2_default: blsp1-uart2-default {
 325                                 rx {
 326                                         pins = "gpio18";
 327                                         function = "blsp_uart_rx_a2";
 328                                 };
 329
 330                                 tx {
 331                                         pins = "gpio17";
 332                                         function = "blsp_uart_tx_a2";
 333                                 };
 334                         };
 335
 336                         blsp1_uart3_default: blsp1-uart3-default {
 337                                 pins = "gpio82", "gpio83", "gpio84", "gpio85";
 338                                 function = "blsp_uart3";
 339                         };
 340
 341                         blsp2_i2c0_default: blsp2-i2c0-default {
 342                                 pins = "gpio28", "gpio29";
 343                                 function = "blsp_i2c5";
 344                         };
 345
 346                         blsp1_spi0_default: blsp1-spi0-default {
 347                                 pins = "gpio30", "gpio31", "gpio32", "gpio33";
 348                                 function = "blsp_spi0";
 349                         };
 350
 351                         blsp1_spi1_default: blsp1-spi1-default {
 352                                 pins = "gpio22", "gpio23", "gpio24", "gpio25";
 353                                 function = "blsp_spi1";
 354                         };
 355
 356                         blsp1_spi2_default: blsp1-spi2-default {
 357                                 pins = "gpio17", "gpio18", "gpio19", "gpio20";
 358                                 function = "blsp_spi2";
 359                         };
 360
 361                         blsp1_spi3_default: blsp1-spi3-default {
 362                                 pins = "gpio82", "gpio83", "gpio84", "gpio85";
 363                                 function = "blsp_spi3";
 364                         };
 365
 366                         blsp1_spi4_default: blsp1-spi4-default {
 367                                 pins = "gpio37", "gpio38", "gpio117", "gpio118";
 368                                 function = "blsp_spi4";
 369                         };
 370
 371                         blsp2_spi0_default: blsp2-spi0-default {
 372                                 pins = "gpio26", "gpio27", "gpio28", "gpio29";
 373                                 function = "blsp_spi5";
 374                         };
 375
 376                         blsp2_uart0_default: blsp2-uart0-default {
 377                                 pins = "gpio26", "gpio27", "gpio28", "gpio29";
 378                                 function = "blsp_uart5";
 379                         };
 380                 };
 381
 382                 gcc: clock-controller@1800000 {
 383                         compatible = "qcom,gcc-qcs404";
 384                         reg = <0x01800000 0x80000>;
 385                         #clock-cells = <1>;
 386
 387                         assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
 388                         assigned-clock-rates = <19200000>;
 389                 };
 390
 391                 tcsr_mutex_regs: syscon@1905000 {
 392                         compatible = "syscon";
 393                         reg = <0x01905000 0x20000>;
 394                 };
 395
 396                 spmi_bus: spmi@200f000 {
 397                         compatible = "qcom,spmi-pmic-arb";
 398                         reg = <0x0200f000 0x001000>,
 399                               <0x02400000 0x800000>,
 400                               <0x02c00000 0x800000>,
 401                               <0x03800000 0x200000>,
 402                               <0x0200a000 0x002100>;
 403                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 404                         interrupt-names = "periph_irq";
 405                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 406                         qcom,ee = <0>;
 407                         qcom,channel = <0>;
 408                         #address-cells = <2>;
 409                         #size-cells = <0>;
 410                         interrupt-controller;
 411                         #interrupt-cells = <4>;
 412                 };
 413
 414                 sdcc1: sdcc@7804000 {
 415                         compatible = "qcom,sdhci-msm-v5";
 416                         reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
 417                         reg-names = "hc_mem", "cmdq_mem";
 418
 419                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 420                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 421                         interrupt-names = "hc_irq", "pwr_irq";
 422
 423                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 424                                  <&gcc GCC_SDCC1_AHB_CLK>,
 425                                  <&xo_board>;
 426                         clock-names = "core", "iface", "xo";
 427
 428                         status = "disabled";
 429                 };
 430
 431                 blsp1_dma: dma@7884000 {
 432                         compatible = "qcom,bam-v1.7.0";
 433                         reg = <0x07884000 0x25000>;
 434                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 435                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 436                         clock-names = "bam_clk";
 437                         #dma-cells = <1>;
 438                         qcom,controlled-remotely = <1>;
 439                         qcom,ee = <0>;
 440                         status = "okay";
 441                 };
 442
 443                 blsp1_uart0: serial@78af000 {
 444                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 445                         reg = <0x078af000 0x200>;
 446                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 447                         clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 448                         clock-names = "core", "iface";
 449                         dmas = <&blsp1_dma 1>, <&blsp1_dma 0>;
 450                         dma-names = "rx", "tx";
 451                         pinctrl-names = "default";
 452                         pinctrl-0 = <&blsp1_uart0_default>;
 453                         status = "disabled";
 454                 };
 455
 456                 blsp1_uart1: serial@78b0000 {
 457                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 458                         reg = <0x078b0000 0x200>;
 459                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 460                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 461                         clock-names = "core", "iface";
 462                         dmas = <&blsp1_dma 3>, <&blsp1_dma 2>;
 463                         dma-names = "rx", "tx";
 464                         pinctrl-names = "default";
 465                         pinctrl-0 = <&blsp1_uart1_default>;
 466                         status = "disabled";
 467                 };
 468
 469                 blsp1_uart2: serial@78b1000 {
 470                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 471                         reg = <0x078b1000 0x200>;
 472                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 473                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 474                         clock-names = "core", "iface";
 475                         dmas = <&blsp1_dma 5>, <&blsp1_dma 4>;
 476                         dma-names = "rx", "tx";
 477                         pinctrl-names = "default";
 478                         pinctrl-0 = <&blsp1_uart2_default>;
 479                         status = "okay";
 480                 };
 481
 482                 wifi: wifi@a000000 {
 483                         compatible = "qcom,wcn3990-wifi";
 484                         reg = <0xa000000 0x800000>;
 485                         reg-names = "membase";
 486                         memory-region = <&wlan_msa_mem>;
 487                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 488                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 489                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 490                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
 491                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
 492                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
 493                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
 494                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
 495                                      <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
 496                                      <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
 497                                      <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
 498                                      <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 499                         status = "disabled";
 500                 };
 501
 502                 blsp1_uart3: serial@78b2000 {
 503                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 504                         reg = <0x078b2000 0x200>;
 505                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 506                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 507                         clock-names = "core", "iface";
 508                         dmas = <&blsp1_dma 7>, <&blsp1_dma 6>;
 509                         dma-names = "rx", "tx";
 510                         pinctrl-names = "default";
 511                         pinctrl-0 = <&blsp1_uart3_default>;
 512                         status = "disabled";
 513                 };
 514
 515                 blsp1_i2c0: i2c@78b5000 {
 516                         compatible = "qcom,i2c-qup-v2.2.1";
 517                         reg = <0x078b5000 0x600>;
 518                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 519                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 520                                  <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
 521                         clock-names = "iface", "core";
 522                         pinctrl-names = "default";
 523                         pinctrl-0 = <&blsp1_i2c0_default>;
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         status = "disabled";
 527                 };
 528
 529                 blsp1_spi0: spi@78b5000 {
 530                         compatible = "qcom,spi-qup-v2.2.1";
 531                         reg = <0x078b5000 0x600>;
 532                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 533                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 534                                  <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
 535                         clock-names = "iface", "core";
 536                         pinctrl-names = "default";
 537                         pinctrl-0 = <&blsp1_spi0_default>;
 538                         #address-cells = <1>;
 539                         #size-cells = <0>;
 540                         status = "disabled";
 541                 };
 542
 543                 blsp1_i2c1: i2c@78b6000 {
 544                         compatible = "qcom,i2c-qup-v2.2.1";
 545                         reg = <0x078b6000 0x600>;
 546                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 547                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 548                                  <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
 549                         clock-names = "iface", "core";
 550                         pinctrl-names = "default";
 551                         pinctrl-0 = <&blsp1_i2c1_default>;
 552                         #address-cells = <1>;
 553                         #size-cells = <0>;
 554                         status = "disabled";
 555                 };
 556
 557                 blsp1_spi1: spi@78b6000 {
 558                         compatible = "qcom,spi-qup-v2.2.1";
 559                         reg = <0x078b6000 0x600>;
 560                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 561                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 562                                  <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
 563                         clock-names = "iface", "core";
 564                         pinctrl-names = "default";
 565                         pinctrl-0 = <&blsp1_spi1_default>;
 566                         #address-cells = <1>;
 567                         #size-cells = <0>;
 568                         status = "disabled";
 569                 };
 570
 571                 blsp1_i2c2: i2c@78b7000 {
 572                         compatible = "qcom,i2c-qup-v2.2.1";
 573                         reg = <0x078b7000 0x600>;
 574                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 575                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 576                                  <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 577                         clock-names = "iface", "core";
 578                         pinctrl-names = "default";
 579                         pinctrl-0 = <&blsp1_i2c2_default>;
 580                         #address-cells = <1>;
 581                         #size-cells = <0>;
 582                         status = "disabled";
 583                 };
 584
 585                 blsp1_spi2: spi@78b7000 {
 586                         compatible = "qcom,spi-qup-v2.2.1";
 587                         reg = <0x078b7000 0x600>;
 588                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 589                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 590                                  <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
 591                         clock-names = "iface", "core";
 592                         pinctrl-names = "default";
 593                         pinctrl-0 = <&blsp1_spi2_default>;
 594                         #address-cells = <1>;
 595                         #size-cells = <0>;
 596                         status = "disabled";
 597                 };
 598
 599                 blsp1_i2c3: i2c@78b8000 {
 600                         compatible = "qcom,i2c-qup-v2.2.1";
 601                         reg = <0x078b8000 0x600>;
 602                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 603                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 604                                  <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 605                         clock-names = "iface", "core";
 606                         pinctrl-names = "default";
 607                         pinctrl-0 = <&blsp1_i2c3_default>;
 608                         #address-cells = <1>;
 609                         #size-cells = <0>;
 610                         status = "disabled";
 611                 };
 612
 613                 blsp1_spi3: spi@78b8000 {
 614                         compatible = "qcom,spi-qup-v2.2.1";
 615                         reg = <0x078b8000 0x600>;
 616                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 617                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 618                                  <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
 619                         clock-names = "iface", "core";
 620                         pinctrl-names = "default";
 621                         pinctrl-0 = <&blsp1_spi3_default>;
 622                         #address-cells = <1>;
 623                         #size-cells = <0>;
 624                         status = "disabled";
 625                 };
 626
 627                 blsp1_i2c4: i2c@78b9000 {
 628                         compatible = "qcom,i2c-qup-v2.2.1";
 629                         reg = <0x078b9000 0x600>;
 630                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 631                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 632                                  <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 633                         clock-names = "iface", "core";
 634                         pinctrl-names = "default";
 635                         pinctrl-0 = <&blsp1_i2c4_default>;
 636                         #address-cells = <1>;
 637                         #size-cells = <0>;
 638                         status = "disabled";
 639                 };
 640
 641                 blsp1_spi4: spi@78b9000 {
 642                         compatible = "qcom,spi-qup-v2.2.1";
 643                         reg = <0x078b9000 0x600>;
 644                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 645                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 646                                  <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
 647                         clock-names = "iface", "core";
 648                         pinctrl-names = "default";
 649                         pinctrl-0 = <&blsp1_spi4_default>;
 650                         #address-cells = <1>;
 651                         #size-cells = <0>;
 652                         status = "disabled";
 653                 };
 654
 655                 blsp2_dma: dma@7ac4000 {
 656                         compatible = "qcom,bam-v1.7.0";
 657                         reg = <0x07ac4000 0x17000>;
 658                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 659                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 660                         clock-names = "bam_clk";
 661                         #dma-cells = <1>;
 662                         qcom,controlled-remotely = <1>;
 663                         qcom,ee = <0>;
 664                         status = "disabled";
 665                 };
 666
 667                 blsp2_uart0: serial@7aef000 {
 668                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 669                         reg = <0x07aef000 0x200>;
 670                         interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
 671                         clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 672                         clock-names = "core", "iface";
 673                         dmas = <&blsp2_dma 1>, <&blsp2_dma 0>;
 674                         dma-names = "rx", "tx";
 675                         pinctrl-names = "default";
 676                         pinctrl-0 = <&blsp2_uart0_default>;
 677                         status = "disabled";
 678                 };
 679
 680                 blsp2_i2c0: i2c@7af5000 {
 681                         compatible = "qcom,i2c-qup-v2.2.1";
 682                         reg = <0x07af5000 0x600>;
 683                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 684                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 685                                  <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
 686                         clock-names = "iface", "core";
 687                         pinctrl-names = "default";
 688                         pinctrl-0 = <&blsp2_i2c0_default>;
 689                         #address-cells = <1>;
 690                         #size-cells = <0>;
 691                         status = "disabled";
 692                 };
 693
 694                 blsp2_spi0: spi@7af5000 {
 695                         compatible = "qcom,spi-qup-v2.2.1";
 696                         reg = <0x07af5000 0x600>;
 697                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 698                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 699                                  <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
 700                         clock-names = "iface", "core";
 701                         pinctrl-names = "default";
 702                         pinctrl-0 = <&blsp2_spi0_default>;
 703                         #address-cells = <1>;
 704                         #size-cells = <0>;
 705                         status = "disabled";
 706                 };
 707
 708                 intc: interrupt-controller@b000000 {
 709                         compatible = "qcom,msm-qgic2";
 710                         interrupt-controller;
 711                         #interrupt-cells = <3>;
 712                         reg = <0x0b000000 0x1000>,
 713                               <0x0b002000 0x1000>;
 714                 };
 715
 716                 apcs_glb: mailbox@b011000 {
 717                         compatible = "qcom,qcs404-apcs-apps-global", "syscon";
 718                         reg = <0x0b011000 0x1000>;
 719                         #mbox-cells = <1>;
 720                 };
 721
 722                 timer@b120000 {
 723                         #address-cells = <1>;
 724                         #size-cells = <1>;
 725                         ranges;
 726                         compatible = "arm,armv7-timer-mem";
 727                         reg = <0x0b120000 0x1000>;
 728                         clock-frequency = <19200000>;
 729
 730                         frame@b121000 {
 731                                 frame-number = <0>;
 732                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 733                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 734                                 reg = <0x0b121000 0x1000>,
 735                                       <0x0b122000 0x1000>;
 736                         };
 737
 738                         frame@b123000 {
 739                                 frame-number = <1>;
 740                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 741                                 reg = <0x0b123000 0x1000>;
 742                                 status = "disabled";
 743                         };
 744
 745                         frame@b124000 {
 746                                 frame-number = <2>;
 747                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 748                                 reg = <0x0b124000 0x1000>;
 749                                 status = "disabled";
 750                         };
 751
 752                         frame@b125000 {
 753                                 frame-number = <3>;
 754                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 755                                 reg = <0x0b125000 0x1000>;
 756                                 status = "disabled";
 757                         };
 758
 759                         frame@b126000 {
 760                                 frame-number = <4>;
 761                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 762                                 reg = <0x0b126000 0x1000>;
 763                                 status = "disabled";
 764                         };
 765
 766                         frame@b127000 {
 767                                 frame-number = <5>;
 768                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 769                                 reg = <0xb127000 0x1000>;
 770                                 status = "disabled";
 771                         };
 772
 773                         frame@b128000 {
 774                                 frame-number = <6>;
 775                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 776                                 reg = <0x0b128000 0x1000>;
 777                                 status = "disabled";
 778                         };
 779                 };
 780         };
 781
 782         timer {
 783                 compatible = "arm,armv8-timer";
 784                 interrupts = <GIC_PPI 2 0xff08>,
 785                              <GIC_PPI 3 0xff08>,
 786                              <GIC_PPI 4 0xff08>,
 787                              <GIC_PPI 1 0xff08>;
 788         };
 789
 790         smp2p-adsp {
 791                 compatible = "qcom,smp2p";
 792                 qcom,smem = <443>, <429>;
 793                 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
 794                 mboxes = <&apcs_glb 10>;
 795                 qcom,local-pid = <0>;
 796                 qcom,remote-pid = <2>;
 797
 798                 adsp_smp2p_out: master-kernel {
 799                         qcom,entry-name = "master-kernel";
 800                         #qcom,smem-state-cells = <1>;
 801                 };
 802
 803                 adsp_smp2p_in: slave-kernel {
 804                         qcom,entry-name = "slave-kernel";
 805                         interrupt-controller;
 806                         #interrupt-cells = <2>;
 807                 };
 808         };
 809
 810         smp2p-cdsp {
 811                 compatible = "qcom,smp2p";
 812                 qcom,smem = <94>, <432>;
 813                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
 814                 mboxes = <&apcs_glb 14>;
 815                 qcom,local-pid = <0>;
 816                 qcom,remote-pid = <5>;
 817
 818                 cdsp_smp2p_out: master-kernel {
 819                         qcom,entry-name = "master-kernel";
 820                         #qcom,smem-state-cells = <1>;
 821                 };
 822
 823                 cdsp_smp2p_in: slave-kernel {
 824                         qcom,entry-name = "slave-kernel";
 825                         interrupt-controller;
 826                         #interrupt-cells = <2>;
 827                 };
 828         };
 829
 830         smp2p-wcss {
 831                 compatible = "qcom,smp2p";
 832                 qcom,smem = <435>, <428>;
 833                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 834                 mboxes = <&apcs_glb 18>;
 835                 qcom,local-pid = <0>;
 836                 qcom,remote-pid = <1>;
 837
 838                 wcss_smp2p_out: master-kernel {
 839                         qcom,entry-name = "master-kernel";
 840                         #qcom,smem-state-cells = <1>;
 841                 };
 842
 843                 wcss_smp2p_in: slave-kernel {
 844                         qcom,entry-name = "slave-kernel";
 845                         interrupt-controller;
 846                         #interrupt-cells = <2>;
 847                 };
 848         };
 849 };