1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018, Linaro Limited
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
9 interrupt-parent = <&intc>;
18 compatible = "fixed-clock";
20 clock-frequency = <19200000>;
30 compatible = "arm,cortex-a53";
32 enable-method = "psci";
33 next-level-cache = <&L2_0>;
38 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 next-level-cache = <&L2_0>;
46 compatible = "arm,cortex-a53";
48 enable-method = "psci";
49 next-level-cache = <&L2_0>;
54 compatible = "arm,cortex-a53";
56 enable-method = "psci";
57 next-level-cache = <&L2_0>;
68 compatible = "qcom,scm-qcs404", "qcom,scm";
74 device_type = "memory";
75 /* We expect the bootloader to fill in the size */
76 reg = <0 0x80000000 0 0>;
80 compatible = "arm,psci-1.0";
84 remoteproc_adsp: remoteproc-adsp {
85 compatible = "qcom,qcs404-adsp-pas";
87 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
88 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
89 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
90 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
91 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
92 interrupt-names = "wdog", "fatal", "ready",
93 "handover", "stop-ack";
98 memory-region = <&adsp_fw_mem>;
100 qcom,smem-states = <&adsp_smp2p_out 0>;
101 qcom,smem-state-names = "stop";
106 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
108 qcom,remote-pid = <2>;
109 mboxes = <&apcs_glb 8>;
115 remoteproc_cdsp: remoteproc-cdsp {
116 compatible = "qcom,qcs404-cdsp-pas";
118 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
119 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
120 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
121 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
122 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
123 interrupt-names = "wdog", "fatal", "ready",
124 "handover", "stop-ack";
126 clocks = <&xo_board>;
129 memory-region = <&cdsp_fw_mem>;
131 qcom,smem-states = <&cdsp_smp2p_out 0>;
132 qcom,smem-state-names = "stop";
137 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
139 qcom,remote-pid = <5>;
140 mboxes = <&apcs_glb 12>;
146 remoteproc_wcss: remoteproc-wcss {
147 compatible = "qcom,qcs404-wcss-pas";
149 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
150 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
151 <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
152 <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
153 <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
154 interrupt-names = "wdog", "fatal", "ready",
155 "handover", "stop-ack";
157 clocks = <&xo_board>;
160 memory-region = <&wlan_fw_mem>;
162 qcom,smem-states = <&wcss_smp2p_out 0>;
163 qcom,smem-state-names = "stop";
168 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
170 qcom,remote-pid = <1>;
171 mboxes = <&apcs_glb 16>;
178 #address-cells = <2>;
183 reg = <0 0x85600000 0 0x90000>;
187 smem_region: memory@85f00000 {
188 reg = <0 0x85f00000 0 0x200000>;
193 reg = <0 0x86100000 0 0x300000>;
197 wlan_fw_mem: memory@86400000 {
198 reg = <0 0x86400000 0 0x1c00000>;
202 adsp_fw_mem: memory@88000000 {
203 reg = <0 0x88000000 0 0x1a00000>;
207 cdsp_fw_mem: memory@89a00000 {
208 reg = <0 0x89a00000 0 0x600000>;
212 wlan_msa_mem: memory@8a000000 {
213 reg = <0 0x8a000000 0 0x100000>;
219 compatible = "qcom,glink-rpm";
221 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
222 qcom,rpm-msg-ram = <&rpm_msg_ram>;
223 mboxes = <&apcs_glb 0>;
225 rpm_requests: glink-channel {
226 compatible = "qcom,rpm-qcs404";
227 qcom,glink-channels = "rpm_requests";
229 rpmcc: clock-controller {
230 compatible = "qcom,rpmcc-qcs404";
237 compatible = "qcom,smem";
239 memory-region = <&smem_region>;
240 qcom,rpm-msg-ram = <&rpm_msg_ram>;
242 hwlocks = <&tcsr_mutex 3>;
246 compatible = "qcom,tcsr-mutex";
247 syscon = <&tcsr_mutex_regs 0 0x1000>;
252 #address-cells = <1>;
254 ranges = <0 0 0 0xffffffff>;
255 compatible = "simple-bus";
257 rpm_msg_ram: memory@60000 {
258 compatible = "qcom,rpm-msg-ram";
259 reg = <0x00060000 0x6000>;
263 compatible = "qcom,prng-ee";
264 reg = <0x000e3000 0x1000>;
265 clocks = <&gcc GCC_PRNG_AHB_CLK>;
266 clock-names = "core";
269 tlmm: pinctrl@1000000 {
270 compatible = "qcom,qcs404-pinctrl";
271 reg = <0x01000000 0x200000>,
272 <0x01300000 0x200000>,
273 <0x07b00000 0x200000>;
274 reg-names = "south", "north", "east";
275 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
276 gpio-ranges = <&tlmm 0 0 120>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
282 blsp1_i2c0_default: blsp1-i2c0-default {
283 pins = "gpio32", "gpio33";
284 function = "blsp_i2c0";
287 blsp1_i2c1_default: blsp1-i2c1-default {
288 pins = "gpio24", "gpio25";
289 function = "blsp_i2c1";
292 blsp1_i2c2_default: blsp1-i2c2-default {
295 function = "blsp_i2c_sda_a2";
300 function = "blsp_i2c_scl_a2";
304 blsp1_i2c3_default: blsp1-i2c3-default {
305 pins = "gpio84", "gpio85";
306 function = "blsp_i2c3";
309 blsp1_i2c4_default: blsp1-i2c4-default {
310 pins = "gpio117", "gpio118";
311 function = "blsp_i2c4";
314 blsp1_uart0_default: blsp1-uart0-default {
315 pins = "gpio30", "gpio31", "gpio32", "gpio33";
316 function = "blsp_uart0";
319 blsp1_uart1_default: blsp1-uart1-default {
320 pins = "gpio22", "gpio23";
321 function = "blsp_uart1";
324 blsp1_uart2_default: blsp1-uart2-default {
327 function = "blsp_uart_rx_a2";
332 function = "blsp_uart_tx_a2";
336 blsp1_uart3_default: blsp1-uart3-default {
337 pins = "gpio82", "gpio83", "gpio84", "gpio85";
338 function = "blsp_uart3";
341 blsp2_i2c0_default: blsp2-i2c0-default {
342 pins = "gpio28", "gpio29";
343 function = "blsp_i2c5";
346 blsp1_spi0_default: blsp1-spi0-default {
347 pins = "gpio30", "gpio31", "gpio32", "gpio33";
348 function = "blsp_spi0";
351 blsp1_spi1_default: blsp1-spi1-default {
352 pins = "gpio22", "gpio23", "gpio24", "gpio25";
353 function = "blsp_spi1";
356 blsp1_spi2_default: blsp1-spi2-default {
357 pins = "gpio17", "gpio18", "gpio19", "gpio20";
358 function = "blsp_spi2";
361 blsp1_spi3_default: blsp1-spi3-default {
362 pins = "gpio82", "gpio83", "gpio84", "gpio85";
363 function = "blsp_spi3";
366 blsp1_spi4_default: blsp1-spi4-default {
367 pins = "gpio37", "gpio38", "gpio117", "gpio118";
368 function = "blsp_spi4";
371 blsp2_spi0_default: blsp2-spi0-default {
372 pins = "gpio26", "gpio27", "gpio28", "gpio29";
373 function = "blsp_spi5";
376 blsp2_uart0_default: blsp2-uart0-default {
377 pins = "gpio26", "gpio27", "gpio28", "gpio29";
378 function = "blsp_uart5";
382 gcc: clock-controller@1800000 {
383 compatible = "qcom,gcc-qcs404";
384 reg = <0x01800000 0x80000>;
387 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
388 assigned-clock-rates = <19200000>;
391 tcsr_mutex_regs: syscon@1905000 {
392 compatible = "syscon";
393 reg = <0x01905000 0x20000>;
396 spmi_bus: spmi@200f000 {
397 compatible = "qcom,spmi-pmic-arb";
398 reg = <0x0200f000 0x001000>,
399 <0x02400000 0x800000>,
400 <0x02c00000 0x800000>,
401 <0x03800000 0x200000>,
402 <0x0200a000 0x002100>;
403 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
404 interrupt-names = "periph_irq";
405 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
408 #address-cells = <2>;
410 interrupt-controller;
411 #interrupt-cells = <4>;
414 sdcc1: sdcc@7804000 {
415 compatible = "qcom,sdhci-msm-v5";
416 reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
417 reg-names = "hc_mem", "cmdq_mem";
419 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
421 interrupt-names = "hc_irq", "pwr_irq";
423 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
424 <&gcc GCC_SDCC1_AHB_CLK>,
426 clock-names = "core", "iface", "xo";
431 blsp1_dma: dma@7884000 {
432 compatible = "qcom,bam-v1.7.0";
433 reg = <0x07884000 0x25000>;
434 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
436 clock-names = "bam_clk";
442 blsp1_uart0: serial@78af000 {
443 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
444 reg = <0x078af000 0x200>;
445 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
447 clock-names = "core", "iface";
448 dmas = <&blsp1_dma 1>, <&blsp1_dma 0>;
449 dma-names = "rx", "tx";
450 pinctrl-names = "default";
451 pinctrl-0 = <&blsp1_uart0_default>;
455 blsp1_uart1: serial@78b0000 {
456 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
457 reg = <0x078b0000 0x200>;
458 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
460 clock-names = "core", "iface";
461 dmas = <&blsp1_dma 3>, <&blsp1_dma 2>;
462 dma-names = "rx", "tx";
463 pinctrl-names = "default";
464 pinctrl-0 = <&blsp1_uart1_default>;
468 blsp1_uart2: serial@78b1000 {
469 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
470 reg = <0x078b1000 0x200>;
471 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
473 clock-names = "core", "iface";
474 dmas = <&blsp1_dma 5>, <&blsp1_dma 4>;
475 dma-names = "rx", "tx";
476 pinctrl-names = "default";
477 pinctrl-0 = <&blsp1_uart2_default>;
481 ethernet: ethernet@7a80000 {
482 compatible = "qcom,qcs404-ethqos";
483 reg = <0x07a80000 0x10000>,
485 reg-names = "stmmaceth", "rgmii";
486 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
487 clocks = <&gcc GCC_ETH_AXI_CLK>,
488 <&gcc GCC_ETH_SLAVE_AHB_CLK>,
489 <&gcc GCC_ETH_PTP_CLK>,
490 <&gcc GCC_ETH_RGMII_CLK>;
491 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
493 interrupt-names = "macirq", "eth_lpi";
496 rx-fifo-depth = <4096>;
497 tx-fifo-depth = <4096>;
503 compatible = "qcom,wcn3990-wifi";
504 reg = <0xa000000 0x800000>;
505 reg-names = "membase";
506 memory-region = <&wlan_msa_mem>;
507 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
522 blsp1_uart3: serial@78b2000 {
523 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
524 reg = <0x078b2000 0x200>;
525 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
527 clock-names = "core", "iface";
528 dmas = <&blsp1_dma 7>, <&blsp1_dma 6>;
529 dma-names = "rx", "tx";
530 pinctrl-names = "default";
531 pinctrl-0 = <&blsp1_uart3_default>;
535 blsp1_i2c0: i2c@78b5000 {
536 compatible = "qcom,i2c-qup-v2.2.1";
537 reg = <0x078b5000 0x600>;
538 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
540 <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
541 clock-names = "iface", "core";
542 pinctrl-names = "default";
543 pinctrl-0 = <&blsp1_i2c0_default>;
544 #address-cells = <1>;
549 blsp1_spi0: spi@78b5000 {
550 compatible = "qcom,spi-qup-v2.2.1";
551 reg = <0x078b5000 0x600>;
552 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
554 <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
555 clock-names = "iface", "core";
556 pinctrl-names = "default";
557 pinctrl-0 = <&blsp1_spi0_default>;
558 #address-cells = <1>;
563 blsp1_i2c1: i2c@78b6000 {
564 compatible = "qcom,i2c-qup-v2.2.1";
565 reg = <0x078b6000 0x600>;
566 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
568 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
569 clock-names = "iface", "core";
570 pinctrl-names = "default";
571 pinctrl-0 = <&blsp1_i2c1_default>;
572 #address-cells = <1>;
577 blsp1_spi1: spi@78b6000 {
578 compatible = "qcom,spi-qup-v2.2.1";
579 reg = <0x078b6000 0x600>;
580 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
582 <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
583 clock-names = "iface", "core";
584 pinctrl-names = "default";
585 pinctrl-0 = <&blsp1_spi1_default>;
586 #address-cells = <1>;
591 blsp1_i2c2: i2c@78b7000 {
592 compatible = "qcom,i2c-qup-v2.2.1";
593 reg = <0x078b7000 0x600>;
594 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
596 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
597 clock-names = "iface", "core";
598 pinctrl-names = "default";
599 pinctrl-0 = <&blsp1_i2c2_default>;
600 #address-cells = <1>;
605 blsp1_spi2: spi@78b7000 {
606 compatible = "qcom,spi-qup-v2.2.1";
607 reg = <0x078b7000 0x600>;
608 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
610 <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
611 clock-names = "iface", "core";
612 pinctrl-names = "default";
613 pinctrl-0 = <&blsp1_spi2_default>;
614 #address-cells = <1>;
619 blsp1_i2c3: i2c@78b8000 {
620 compatible = "qcom,i2c-qup-v2.2.1";
621 reg = <0x078b8000 0x600>;
622 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
624 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
625 clock-names = "iface", "core";
626 pinctrl-names = "default";
627 pinctrl-0 = <&blsp1_i2c3_default>;
628 #address-cells = <1>;
633 blsp1_spi3: spi@78b8000 {
634 compatible = "qcom,spi-qup-v2.2.1";
635 reg = <0x078b8000 0x600>;
636 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
638 <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
639 clock-names = "iface", "core";
640 pinctrl-names = "default";
641 pinctrl-0 = <&blsp1_spi3_default>;
642 #address-cells = <1>;
647 blsp1_i2c4: i2c@78b9000 {
648 compatible = "qcom,i2c-qup-v2.2.1";
649 reg = <0x078b9000 0x600>;
650 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
652 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
653 clock-names = "iface", "core";
654 pinctrl-names = "default";
655 pinctrl-0 = <&blsp1_i2c4_default>;
656 #address-cells = <1>;
661 blsp1_spi4: spi@78b9000 {
662 compatible = "qcom,spi-qup-v2.2.1";
663 reg = <0x078b9000 0x600>;
664 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
666 <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
667 clock-names = "iface", "core";
668 pinctrl-names = "default";
669 pinctrl-0 = <&blsp1_spi4_default>;
670 #address-cells = <1>;
675 blsp2_dma: dma@7ac4000 {
676 compatible = "qcom,bam-v1.7.0";
677 reg = <0x07ac4000 0x17000>;
678 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
680 clock-names = "bam_clk";
686 blsp2_uart0: serial@7aef000 {
687 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
688 reg = <0x07aef000 0x200>;
689 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
691 clock-names = "core", "iface";
692 dmas = <&blsp2_dma 1>, <&blsp2_dma 0>;
693 dma-names = "rx", "tx";
694 pinctrl-names = "default";
695 pinctrl-0 = <&blsp2_uart0_default>;
699 blsp2_i2c0: i2c@7af5000 {
700 compatible = "qcom,i2c-qup-v2.2.1";
701 reg = <0x07af5000 0x600>;
702 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
704 <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
705 clock-names = "iface", "core";
706 pinctrl-names = "default";
707 pinctrl-0 = <&blsp2_i2c0_default>;
708 #address-cells = <1>;
713 blsp2_spi0: spi@7af5000 {
714 compatible = "qcom,spi-qup-v2.2.1";
715 reg = <0x07af5000 0x600>;
716 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
718 <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
719 clock-names = "iface", "core";
720 pinctrl-names = "default";
721 pinctrl-0 = <&blsp2_spi0_default>;
722 #address-cells = <1>;
727 intc: interrupt-controller@b000000 {
728 compatible = "qcom,msm-qgic2";
729 interrupt-controller;
730 #interrupt-cells = <3>;
731 reg = <0x0b000000 0x1000>,
735 apcs_glb: mailbox@b011000 {
736 compatible = "qcom,qcs404-apcs-apps-global", "syscon";
737 reg = <0x0b011000 0x1000>;
742 #address-cells = <1>;
745 compatible = "arm,armv7-timer-mem";
746 reg = <0x0b120000 0x1000>;
747 clock-frequency = <19200000>;
751 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
753 reg = <0x0b121000 0x1000>,
759 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
760 reg = <0x0b123000 0x1000>;
766 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
767 reg = <0x0b124000 0x1000>;
773 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
774 reg = <0x0b125000 0x1000>;
780 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
781 reg = <0x0b126000 0x1000>;
787 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
788 reg = <0xb127000 0x1000>;
794 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
795 reg = <0x0b128000 0x1000>;
802 compatible = "arm,armv8-timer";
803 interrupts = <GIC_PPI 2 0xff08>,
810 compatible = "qcom,smp2p";
811 qcom,smem = <443>, <429>;
812 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
813 mboxes = <&apcs_glb 10>;
814 qcom,local-pid = <0>;
815 qcom,remote-pid = <2>;
817 adsp_smp2p_out: master-kernel {
818 qcom,entry-name = "master-kernel";
819 #qcom,smem-state-cells = <1>;
822 adsp_smp2p_in: slave-kernel {
823 qcom,entry-name = "slave-kernel";
824 interrupt-controller;
825 #interrupt-cells = <2>;
830 compatible = "qcom,smp2p";
831 qcom,smem = <94>, <432>;
832 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
833 mboxes = <&apcs_glb 14>;
834 qcom,local-pid = <0>;
835 qcom,remote-pid = <5>;
837 cdsp_smp2p_out: master-kernel {
838 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells = <1>;
842 cdsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "slave-kernel";
844 interrupt-controller;
845 #interrupt-cells = <2>;
850 compatible = "qcom,smp2p";
851 qcom,smem = <435>, <428>;
852 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
853 mboxes = <&apcs_glb 18>;
854 qcom,local-pid = <0>;
855 qcom,remote-pid = <1>;
857 wcss_smp2p_out: master-kernel {
858 qcom,entry-name = "master-kernel";
859 #qcom,smem-state-cells = <1>;
862 wcss_smp2p_in: slave-kernel {
863 qcom,entry-name = "slave-kernel";
864 interrupt-controller;
865 #interrupt-cells = <2>;