arch/arm64/boot/dts/qcom/msm8996.dtsi

   1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  15 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
  16 #include <dt-bindings/clock/qcom,rpmcc.h>
  17
  18 / {
  19         interrupt-parent = <&intc>;
  20
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         chosen { };
  25
  26         memory {
  27                 device_type = "memory";
  28                 /* We expect the bootloader to fill in the reg */
  29                 reg = <0 0 0 0>;
  30         };
  31
  32         reserved-memory {
  33                 #address-cells = <2>;
  34                 #size-cells = <2>;
  35                 ranges;
  36
  37                 mba_region: mba@91500000 {
  38                         reg = <0x0 0x91500000 0x0 0x200000>;
  39                         no-map;
  40                 };
  41
  42                 slpi_region: slpi@90b00000 {
  43                         reg = <0x0 0x90b00000 0x0 0xa00000>;
  44                         no-map;
  45                 };
  46
  47                 venus_region: venus@90400000 {
  48                         reg = <0x0 0x90400000 0x0 0x700000>;
  49                         no-map;
  50                 };
  51
  52                 adsp_region: adsp@8ea00000 {
  53                         reg = <0x0 0x8ea00000 0x0 0x1a00000>;
  54                         no-map;
  55                 };
  56
  57                 mpss_region: mpss@88800000 {
  58                         reg = <0x0 0x88800000 0x0 0x6200000>;
  59                         no-map;
  60                 };
  61
  62                 smem_mem: smem-mem@86000000 {
  63                         reg = <0x0 0x86000000 0x0 0x200000>;
  64                         no-map;
  65                 };
  66
  67                 memory@85800000 {
  68                         reg = <0x0 0x85800000 0x0 0x800000>;
  69                         no-map;
  70                 };
  71
  72                 memory@86200000 {
  73                         reg = <0x0 0x86200000 0x0 0x2600000>;
  74                         no-map;
  75                 };
  76
  77                 rmtfs@86700000 {
  78                         compatible = "qcom,rmtfs-mem";
  79
  80                         size = <0x0 0x200000>;
  81                         alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
  82                         no-map;
  83
  84                         qcom,client-id = <1>;
  85                         qcom,vmid = <15>;
  86                 };
  87         };
  88
  89         cpus {
  90                 #address-cells = <2>;
  91                 #size-cells = <0>;
  92
  93                 CPU0: cpu@0 {
  94                         device_type = "cpu";
  95                         compatible = "qcom,kryo";
  96                         reg = <0x0 0x0>;
  97                         enable-method = "psci";
  98                         next-level-cache = <&L2_0>;
  99                         L2_0: l2-cache {
 100                               compatible = "cache";
 101                               cache-level = <2>;
 102                         };
 103                 };
 104
 105                 CPU1: cpu@1 {
 106                         device_type = "cpu";
 107                         compatible = "qcom,kryo";
 108                         reg = <0x0 0x1>;
 109                         enable-method = "psci";
 110                         next-level-cache = <&L2_0>;
 111                 };
 112
 113                 CPU2: cpu@100 {
 114                         device_type = "cpu";
 115                         compatible = "qcom,kryo";
 116                         reg = <0x0 0x100>;
 117                         enable-method = "psci";
 118                         next-level-cache = <&L2_1>;
 119                         L2_1: l2-cache {
 120                               compatible = "cache";
 121                               cache-level = <2>;
 122                         };
 123                 };
 124
 125                 CPU3: cpu@101 {
 126                         device_type = "cpu";
 127                         compatible = "qcom,kryo";
 128                         reg = <0x0 0x101>;
 129                         enable-method = "psci";
 130                         next-level-cache = <&L2_1>;
 131                 };
 132
 133                 cpu-map {
 134                         cluster0 {
 135                                 core0 {
 136                                         cpu = <&CPU0>;
 137                                 };
 138
 139                                 core1 {
 140                                         cpu = <&CPU1>;
 141                                 };
 142                         };
 143
 144                         cluster1 {
 145                                 core0 {
 146                                         cpu = <&CPU2>;
 147                                 };
 148
 149                                 core1 {
 150                                         cpu = <&CPU3>;
 151                                 };
 152                         };
 153                 };
 154         };
 155
 156         thermal-zones {
 157                 cpu-thermal0 {
 158                         polling-delay-passive = <250>;
 159                         polling-delay = <1000>;
 160
 161                         thermal-sensors = <&tsens0 3>;
 162
 163                         trips {
 164                                 cpu_alert0: trip0 {
 165                                         temperature = <75000>;
 166                                         hysteresis = <2000>;
 167                                         type = "passive";
 168                                 };
 169
 170                                 cpu_crit0: trip1 {
 171                                         temperature = <110000>;
 172                                         hysteresis = <2000>;
 173                                         type = "critical";
 174                                 };
 175                         };
 176                 };
 177
 178                 cpu-thermal1 {
 179                         polling-delay-passive = <250>;
 180                         polling-delay = <1000>;
 181
 182                         thermal-sensors = <&tsens0 5>;
 183
 184                         trips {
 185                                 cpu_alert1: trip0 {
 186                                         temperature = <75000>;
 187                                         hysteresis = <2000>;
 188                                         type = "passive";
 189                                 };
 190
 191                                 cpu_crit1: trip1 {
 192                                         temperature = <110000>;
 193                                         hysteresis = <2000>;
 194                                         type = "critical";
 195                                 };
 196                         };
 197                 };
 198
 199                 cpu-thermal2 {
 200                         polling-delay-passive = <250>;
 201                         polling-delay = <1000>;
 202
 203                         thermal-sensors = <&tsens0 8>;
 204
 205                         trips {
 206                                 cpu_alert2: trip0 {
 207                                         temperature = <75000>;
 208                                         hysteresis = <2000>;
 209                                         type = "passive";
 210                                 };
 211
 212                                 cpu_crit2: trip1 {
 213                                         temperature = <110000>;
 214                                         hysteresis = <2000>;
 215                                         type = "critical";
 216                                 };
 217                         };
 218                 };
 219
 220                 cpu-thermal3 {
 221                         polling-delay-passive = <250>;
 222                         polling-delay = <1000>;
 223
 224                         thermal-sensors = <&tsens0 10>;
 225
 226                         trips {
 227                                 cpu_alert3: trip0 {
 228                                         temperature = <75000>;
 229                                         hysteresis = <2000>;
 230                                         type = "passive";
 231                                 };
 232
 233                                 cpu_crit3: trip1 {
 234                                         temperature = <110000>;
 235                                         hysteresis = <2000>;
 236                                         type = "critical";
 237                                 };
 238                         };
 239                 };
 240         };
 241
 242         timer {
 243                 compatible = "arm,armv8-timer";
 244                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 245                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 246                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 247                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 248         };
 249
 250         clocks {
 251                 xo_board: xo_board {
 252                         compatible = "fixed-clock";
 253                         #clock-cells = <0>;
 254                         clock-frequency = <19200000>;
 255                         clock-output-names = "xo_board";
 256                 };
 257
 258                 sleep_clk: sleep_clk {
 259                         compatible = "fixed-clock";
 260                         #clock-cells = <0>;
 261                         clock-frequency = <32764>;
 262                         clock-output-names = "sleep_clk";
 263                 };
 264         };
 265
 266         psci {
 267                 compatible = "arm,psci-1.0";
 268                 method = "smc";
 269         };
 270
 271         firmware {
 272                 scm {
 273                         compatible = "qcom,scm-msm8996";
 274
 275                         qcom,dload-mode = <&tcsr 0x13000>;
 276                 };
 277         };
 278
 279         tcsr_mutex: hwlock {
 280                 compatible = "qcom,tcsr-mutex";
 281                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 282                 #hwlock-cells = <1>;
 283         };
 284
 285         smem {
 286                 compatible = "qcom,smem";
 287                 memory-region = <&smem_mem>;
 288                 hwlocks = <&tcsr_mutex 3>;
 289         };
 290
 291         rpm-glink {
 292                 compatible = "qcom,glink-rpm";
 293
 294                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 295
 296                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 297
 298                 mboxes = <&apcs_glb 0>;
 299
 300                 rpm_requests {
 301                         compatible = "qcom,rpm-msm8996";
 302                         qcom,glink-channels = "rpm_requests";
 303
 304                         rpmcc: qcom,rpmcc {
 305                                 compatible = "qcom,rpmcc-msm8996";
 306                                 #clock-cells = <1>;
 307                         };
 308
 309                         pm8994-regulators {
 310                                 compatible = "qcom,rpm-pm8994-regulators";
 311
 312                                 pm8994_s1: s1 {};
 313                                 pm8994_s2: s2 {};
 314                                 pm8994_s3: s3 {};
 315                                 pm8994_s4: s4 {};
 316                                 pm8994_s5: s5 {};
 317                                 pm8994_s6: s6 {};
 318                                 pm8994_s7: s7 {};
 319                                 pm8994_s8: s8 {};
 320                                 pm8994_s9: s9 {};
 321                                 pm8994_s10: s10 {};
 322                                 pm8994_s11: s11 {};
 323                                 pm8994_s12: s12 {};
 324
 325                                 pm8994_l1: l1 {};
 326                                 pm8994_l2: l2 {};
 327                                 pm8994_l3: l3 {};
 328                                 pm8994_l4: l4 {};
 329                                 pm8994_l5: l5 {};
 330                                 pm8994_l6: l6 {};
 331                                 pm8994_l7: l7 {};
 332                                 pm8994_l8: l8 {};
 333                                 pm8994_l9: l9 {};
 334                                 pm8994_l10: l10 {};
 335                                 pm8994_l11: l11 {};
 336                                 pm8994_l12: l12 {};
 337                                 pm8994_l13: l13 {};
 338                                 pm8994_l14: l14 {};
 339                                 pm8994_l15: l15 {};
 340                                 pm8994_l16: l16 {};
 341                                 pm8994_l17: l17 {};
 342                                 pm8994_l18: l18 {};
 343                                 pm8994_l19: l19 {};
 344                                 pm8994_l20: l20 {};
 345                                 pm8994_l21: l21 {};
 346                                 pm8994_l22: l22 {};
 347                                 pm8994_l23: l23 {};
 348                                 pm8994_l24: l24 {};
 349                                 pm8994_l25: l25 {};
 350                                 pm8994_l26: l26 {};
 351                                 pm8994_l27: l27 {};
 352                                 pm8994_l28: l28 {};
 353                                 pm8994_l29: l29 {};
 354                                 pm8994_l30: l30 {};
 355                                 pm8994_l31: l31 {};
 356                                 pm8994_l32: l32 {};
 357                         };
 358
 359                 };
 360         };
 361
 362         soc: soc {
 363                 #address-cells = <1>;
 364                 #size-cells = <1>;
 365                 ranges = <0 0 0 0xffffffff>;
 366                 compatible = "simple-bus";
 367
 368                 rpm_msg_ram: memory@68000 {
 369                         compatible = "qcom,rpm-msg-ram";
 370                         reg = <0x68000 0x6000>;
 371                 };
 372
 373                 rng: rng@83000 {
 374                         compatible = "qcom,prng-ee";
 375                         reg = <0x00083000 0x1000>;
 376                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 377                         clock-names = "core";
 378                 };
 379
 380                 tcsr_mutex_regs: syscon@740000 {
 381                         compatible = "syscon";
 382                         reg = <0x740000 0x20000>;
 383                 };
 384
 385                 tsens0: thermal-sensor@4a9000 {
 386                         compatible = "qcom,msm8996-tsens";
 387                         reg = <0x4a9000 0x1000>, /* TM */
 388                               <0x4a8000 0x1000>; /* SROT */
 389                         #qcom,sensors = <13>;
 390                         #thermal-sensor-cells = <1>;
 391                 };
 392
 393                 tsens1: thermal-sensor@4ad000 {
 394                         compatible = "qcom,msm8996-tsens";
 395                         reg = <0x4ad000 0x1000>, /* TM */
 396                               <0x4ac000 0x1000>; /* SROT */
 397                         #qcom,sensors = <8>;
 398                         #thermal-sensor-cells = <1>;
 399                 };
 400
 401                 tcsr: syscon@7a0000 {
 402                         compatible = "qcom,tcsr-msm8996", "syscon";
 403                         reg = <0x7a0000 0x18000>;
 404                 };
 405
 406                 intc: interrupt-controller@9bc0000 {
 407                         compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
 408                         #interrupt-cells = <3>;
 409                         interrupt-controller;
 410                         #redistributor-regions = <1>;
 411                         redistributor-stride = <0x0 0x40000>;
 412                         reg = <0x09bc0000 0x10000>,
 413                               <0x09c00000 0x100000>;
 414                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 415                 };
 416
 417                 apcs_glb: mailbox@9820000 {
 418                         compatible = "qcom,msm8996-apcs-hmss-global";
 419                         reg = <0x9820000 0x1000>;
 420
 421                         #mbox-cells = <1>;
 422                 };
 423
 424                 gcc: clock-controller@300000 {
 425                         compatible = "qcom,gcc-msm8996";
 426                         #clock-cells = <1>;
 427                         #reset-cells = <1>;
 428                         #power-domain-cells = <1>;
 429                         reg = <0x300000 0x90000>;
 430                 };
 431
 432                 kryocc: clock-controller@6400000 {
 433                         compatible = "qcom,apcc-msm8996";
 434                         reg = <0x6400000 0x90000>;
 435                         #clock-cells = <1>;
 436                 };
 437
 438                 blsp1_uart1: serial@7570000 {
 439                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 440                         reg = <0x07570000 0x1000>;
 441                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 442                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 443                                  <&gcc GCC_BLSP1_AHB_CLK>;
 444                         clock-names = "core", "iface";
 445                         status = "disabled";
 446                 };
 447
 448                 blsp1_spi0: spi@7575000 {
 449                         compatible = "qcom,spi-qup-v2.2.1";
 450                         reg = <0x07575000 0x600>;
 451                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 452                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 453                                  <&gcc GCC_BLSP1_AHB_CLK>;
 454                         clock-names = "core", "iface";
 455                         pinctrl-names = "default", "sleep";
 456                         pinctrl-0 = <&blsp1_spi0_default>;
 457                         pinctrl-1 = <&blsp1_spi0_sleep>;
 458                         #address-cells = <1>;
 459                         #size-cells = <0>;
 460                         status = "disabled";
 461                 };
 462
 463                 blsp2_i2c0: i2c@75b5000 {
 464                         compatible = "qcom,i2c-qup-v2.2.1";
 465                         reg = <0x075b5000 0x1000>;
 466                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 467                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 468                                 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
 469                         clock-names = "iface", "core";
 470                         pinctrl-names = "default", "sleep";
 471                         pinctrl-0 = <&blsp2_i2c0_default>;
 472                         pinctrl-1 = <&blsp2_i2c0_sleep>;
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475                         status = "disabled";
 476                 };
 477
 478                 blsp2_uart1: serial@75b0000 {
 479                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 480                         reg = <0x75b0000 0x1000>;
 481                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 482                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 483                                  <&gcc GCC_BLSP2_AHB_CLK>;
 484                         clock-names = "core", "iface";
 485                         status = "disabled";
 486                 };
 487
 488                 blsp2_i2c1: i2c@75b6000 {
 489                         compatible = "qcom,i2c-qup-v2.2.1";
 490                         reg = <0x075b6000 0x1000>;
 491                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 492                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 493                                 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
 494                         clock-names = "iface", "core";
 495                         pinctrl-names = "default", "sleep";
 496                         pinctrl-0 = <&blsp2_i2c1_default>;
 497                         pinctrl-1 = <&blsp2_i2c1_sleep>;
 498                         #address-cells = <1>;
 499                         #size-cells = <0>;
 500                         status = "disabled";
 501                 };
 502
 503                 blsp2_uart2: serial@75b1000 {
 504                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 505                         reg = <0x075b1000 0x1000>;
 506                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 507                         clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
 508                                  <&gcc GCC_BLSP2_AHB_CLK>;
 509                         clock-names = "core", "iface";
 510                         status = "disabled";
 511                 };
 512
 513                 blsp1_i2c2: i2c@7577000 {
 514                         compatible = "qcom,i2c-qup-v2.2.1";
 515                         reg = <0x07577000 0x1000>;
 516                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 517                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 518                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 519                         clock-names = "iface", "core";
 520                         pinctrl-names = "default", "sleep";
 521                         pinctrl-0 = <&blsp1_i2c2_default>;
 522                         pinctrl-1 = <&blsp1_i2c2_sleep>;
 523                         #address-cells = <1>;
 524                         #size-cells = <0>;
 525                         status = "disabled";
 526                 };
 527
 528                 blsp2_spi5: spi@75ba000{
 529                         compatible = "qcom,spi-qup-v2.2.1";
 530                         reg = <0x075ba000 0x600>;
 531                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 532                         clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
 533                                  <&gcc GCC_BLSP2_AHB_CLK>;
 534                         clock-names = "core", "iface";
 535                         pinctrl-names = "default", "sleep";
 536                         pinctrl-0 = <&blsp2_spi5_default>;
 537                         pinctrl-1 = <&blsp2_spi5_sleep>;
 538                         #address-cells = <1>;
 539                         #size-cells = <0>;
 540                         status = "disabled";
 541                 };
 542
 543                 sdhc2: sdhci@74a4900 {
 544                          status = "disabled";
 545                          compatible = "qcom,sdhci-msm-v4";
 546                          reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
 547                          reg-names = "hc_mem", "core_mem";
 548
 549                          interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
 550                                       <0 221 IRQ_TYPE_LEVEL_HIGH>;
 551                          interrupt-names = "hc_irq", "pwr_irq";
 552
 553                          clock-names = "iface", "core", "xo";
 554                          clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 555                          <&gcc GCC_SDCC2_APPS_CLK>,
 556                          <&xo_board>;
 557                          bus-width = <4>;
 558                  };
 559
 560                 msmgpio: pinctrl@1010000 {
 561                         compatible = "qcom,msm8996-pinctrl";
 562                         reg = <0x01010000 0x300000>;
 563                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 564                         gpio-controller;
 565                         #gpio-cells = <2>;
 566                         interrupt-controller;
 567                         #interrupt-cells = <2>;
 568                 };
 569
 570                 timer@9840000 {
 571                         #address-cells = <1>;
 572                         #size-cells = <1>;
 573                         ranges;
 574                         compatible = "arm,armv7-timer-mem";
 575                         reg = <0x09840000 0x1000>;
 576                         clock-frequency = <19200000>;
 577
 578                         frame@9850000 {
 579                                 frame-number = <0>;
 580                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 581                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 582                                 reg = <0x09850000 0x1000>,
 583                                       <0x09860000 0x1000>;
 584                         };
 585
 586                         frame@9870000 {
 587                                 frame-number = <1>;
 588                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 589                                 reg = <0x09870000 0x1000>;
 590                                 status = "disabled";
 591                         };
 592
 593                         frame@9880000 {
 594                                 frame-number = <2>;
 595                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 596                                 reg = <0x09880000 0x1000>;
 597                                 status = "disabled";
 598                         };
 599
 600                         frame@9890000 {
 601                                 frame-number = <3>;
 602                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 603                                 reg = <0x09890000 0x1000>;
 604                                 status = "disabled";
 605                         };
 606
 607                         frame@98a0000 {
 608                                 frame-number = <4>;
 609                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 610                                 reg = <0x098a0000 0x1000>;
 611                                 status = "disabled";
 612                         };
 613
 614                         frame@98b0000 {
 615                                 frame-number = <5>;
 616                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 617                                 reg = <0x098b0000 0x1000>;
 618                                 status = "disabled";
 619                         };
 620
 621                         frame@98c0000 {
 622                                 frame-number = <6>;
 623                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 624                                 reg = <0x098c0000 0x1000>;
 625                                 status = "disabled";
 626                         };
 627                 };
 628
 629                 spmi_bus: qcom,spmi@400f000 {
 630                         compatible = "qcom,spmi-pmic-arb";
 631                         reg = <0x400f000 0x1000>,
 632                               <0x4400000 0x800000>,
 633                               <0x4c00000 0x800000>,
 634                               <0x5800000 0x200000>,
 635                               <0x400a000 0x002100>;
 636                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 637                         interrupt-names = "periph_irq";
 638                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
 639                         qcom,ee = <0>;
 640                         qcom,channel = <0>;
 641                         #address-cells = <2>;
 642                         #size-cells = <0>;
 643                         interrupt-controller;
 644                         #interrupt-cells = <4>;
 645                 };
 646
 647                 ufsphy: phy@627000 {
 648                         compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
 649                         reg = <0x627000 0xda8>;
 650                         reg-names = "phy_mem";
 651                         #phy-cells = <0>;
 652
 653                         vdda-phy-supply = <&pm8994_l28>;
 654                         vdda-pll-supply = <&pm8994_l12>;
 655
 656                         vdda-phy-max-microamp = <18380>;
 657                         vdda-pll-max-microamp = <9440>;
 658
 659                         vddp-ref-clk-supply = <&pm8994_l25>;
 660                         vddp-ref-clk-max-microamp = <100>;
 661                         vddp-ref-clk-always-on;
 662
 663                         clock-names = "ref_clk_src", "ref_clk";
 664                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
 665                                  <&gcc GCC_UFS_CLKREF_CLK>;
 666                         status = "disabled";
 667                 };
 668
 669                 ufshc@624000 {
 670                         compatible = "qcom,ufshc";
 671                         reg = <0x624000 0x2500>;
 672                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 673
 674                         phys = <&ufsphy>;
 675                         phy-names = "ufsphy";
 676
 677                         vcc-supply = <&pm8994_l20>;
 678                         vccq-supply = <&pm8994_l25>;
 679                         vccq2-supply = <&pm8994_s4>;
 680
 681                         vcc-max-microamp = <600000>;
 682                         vccq-max-microamp = <450000>;
 683                         vccq2-max-microamp = <450000>;
 684
 685                         power-domains = <&gcc UFS_GDSC>;
 686
 687                         clock-names =
 688                                 "core_clk_src",
 689                                 "core_clk",
 690                                 "bus_clk",
 691                                 "bus_aggr_clk",
 692                                 "iface_clk",
 693                                 "core_clk_unipro_src",
 694                                 "core_clk_unipro",
 695                                 "core_clk_ice",
 696                                 "ref_clk",
 697                                 "tx_lane0_sync_clk",
 698                                 "rx_lane0_sync_clk";
 699                         clocks =
 700                                 <&gcc UFS_AXI_CLK_SRC>,
 701                                 <&gcc GCC_UFS_AXI_CLK>,
 702                                 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
 703                                 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
 704                                 <&gcc GCC_UFS_AHB_CLK>,
 705                                 <&gcc UFS_ICE_CORE_CLK_SRC>,
 706                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
 707                                 <&gcc GCC_UFS_ICE_CORE_CLK>,
 708                                 <&rpmcc RPM_SMD_LN_BB_CLK>,
 709                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
 710                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
 711                         freq-table-hz =
 712                                 <100000000 200000000>,
 713                                 <0 0>,
 714                                 <0 0>,
 715                                 <0 0>,
 716                                 <0 0>,
 717                                 <150000000 300000000>,
 718                                 <0 0>,
 719                                 <0 0>,
 720                                 <0 0>,
 721                                 <0 0>,
 722                                 <0 0>;
 723
 724                         lanes-per-direction = <1>;
 725                         status = "disabled";
 726
 727                         ufs_variant {
 728                                 compatible = "qcom,ufs_variant";
 729                         };
 730                 };
 731
 732                 mmcc: clock-controller@8c0000 {
 733                         compatible = "qcom,mmcc-msm8996";
 734                         #clock-cells = <1>;
 735                         #reset-cells = <1>;
 736                         #power-domain-cells = <1>;
 737                         reg = <0x8c0000 0x40000>;
 738                         assigned-clocks = <&mmcc MMPLL9_PLL>,
 739                                           <&mmcc MMPLL1_PLL>,
 740                                           <&mmcc MMPLL3_PLL>,
 741                                           <&mmcc MMPLL4_PLL>,
 742                                           <&mmcc MMPLL5_PLL>;
 743                         assigned-clock-rates = <624000000>,
 744                                                <810000000>,
 745                                                <980000000>,
 746                                                <960000000>,
 747                                                <825000000>;
 748                 };
 749
 750                 qfprom@74000 {
 751                         compatible = "qcom,qfprom";
 752                         reg = <0x74000 0x8ff>;
 753                         #address-cells = <1>;
 754                         #size-cells = <1>;
 755
 756                         qusb2p_hstx_trim: hstx_trim@24e {
 757                                 reg = <0x24e 0x2>;
 758                                 bits = <5 4>;
 759                         };
 760
 761                         qusb2s_hstx_trim: hstx_trim@24f {
 762                                 reg = <0x24f 0x1>;
 763                                 bits = <1 4>;
 764                         };
 765                 };
 766
 767                 phy@34000 {
 768                         compatible = "qcom,msm8996-qmp-pcie-phy";
 769                         reg = <0x34000 0x488>;
 770                         #clock-cells = <1>;
 771                         #address-cells = <1>;
 772                         #size-cells = <1>;
 773                         ranges;
 774
 775                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 776                                 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
 777                                 <&gcc GCC_PCIE_CLKREF_CLK>;
 778                         clock-names = "aux", "cfg_ahb", "ref";
 779
 780                         vdda-phy-supply = <&pm8994_l28>;
 781                         vdda-pll-supply = <&pm8994_l12>;
 782
 783                         resets = <&gcc GCC_PCIE_PHY_BCR>,
 784                                 <&gcc GCC_PCIE_PHY_COM_BCR>,
 785                                 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
 786                         reset-names = "phy", "common", "cfg";
 787                         status = "disabled";
 788
 789                         pciephy_0: lane@35000 {
 790                                 reg = <0x035000 0x130>,
 791                                         <0x035200 0x200>,
 792                                         <0x035400 0x1dc>;
 793                                 #phy-cells = <0>;
 794
 795                                 clock-output-names = "pcie_0_pipe_clk_src";
 796                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 797                                 clock-names = "pipe0";
 798                                 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
 799                                 reset-names = "lane0";
 800                         };
 801
 802                         pciephy_1: lane@36000 {
 803                                 reg = <0x036000 0x130>,
 804                                         <0x036200 0x200>,
 805                                         <0x036400 0x1dc>;
 806                                 #phy-cells = <0>;
 807
 808                                 clock-output-names = "pcie_1_pipe_clk_src";
 809                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
 810                                 clock-names = "pipe1";
 811                                 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
 812                                 reset-names = "lane1";
 813                         };
 814
 815                         pciephy_2: lane@37000 {
 816                                 reg = <0x037000 0x130>,
 817                                         <0x037200 0x200>,
 818                                         <0x037400 0x1dc>;
 819                                 #phy-cells = <0>;
 820
 821                                 clock-output-names = "pcie_2_pipe_clk_src";
 822                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
 823                                 clock-names = "pipe2";
 824                                 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
 825                                 reset-names = "lane2";
 826                         };
 827                 };
 828
 829                 phy@7410000 {
 830                         compatible = "qcom,msm8996-qmp-usb3-phy";
 831                         reg = <0x7410000 0x1c4>;
 832                         #clock-cells = <1>;
 833                         #address-cells = <1>;
 834                         #size-cells = <1>;
 835                         ranges;
 836
 837                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
 838                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 839                                 <&gcc GCC_USB3_CLKREF_CLK>;
 840                         clock-names = "aux", "cfg_ahb", "ref";
 841
 842                         vdda-phy-supply = <&pm8994_l28>;
 843                         vdda-pll-supply = <&pm8994_l12>;
 844
 845                         resets = <&gcc GCC_USB3_PHY_BCR>,
 846                                 <&gcc GCC_USB3PHY_PHY_BCR>;
 847                         reset-names = "phy", "common";
 848                         status = "disabled";
 849
 850                         ssusb_phy_0: lane@7410200 {
 851                                 reg = <0x7410200 0x200>,
 852                                         <0x7410400 0x130>,
 853                                         <0x7410600 0x1a8>;
 854                                 #phy-cells = <0>;
 855
 856                                 clock-output-names = "usb3_phy_pipe_clk_src";
 857                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
 858                                 clock-names = "pipe0";
 859                         };
 860                 };
 861
 862                 hsusb_phy1: phy@7411000 {
 863                         compatible = "qcom,msm8996-qusb2-phy";
 864                         reg = <0x7411000 0x180>;
 865                         #phy-cells = <0>;
 866
 867                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 868                                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
 869                         clock-names = "cfg_ahb", "ref";
 870
 871                         vdda-pll-supply = <&pm8994_l12>;
 872                         vdda-phy-dpdm-supply = <&pm8994_l24>;
 873
 874                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 875                         nvmem-cells = <&qusb2p_hstx_trim>;
 876                         status = "disabled";
 877                 };
 878
 879                 hsusb_phy2: phy@7412000 {
 880                         compatible = "qcom,msm8996-qusb2-phy";
 881                         reg = <0x7412000 0x180>;
 882                         #phy-cells = <0>;
 883
 884                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 885                                 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
 886                         clock-names = "cfg_ahb", "ref";
 887
 888                         vdda-pll-supply = <&pm8994_l12>;
 889                         vdda-phy-dpdm-supply = <&pm8994_l24>;
 890
 891                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
 892                         nvmem-cells = <&qusb2s_hstx_trim>;
 893                         status = "disabled";
 894                 };
 895
 896                 usb2: usb@76f8800 {
 897                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
 898                         reg = <0x76f8800 0x400>;
 899                         #address-cells = <1>;
 900                         #size-cells = <1>;
 901                         ranges;
 902
 903                         clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
 904                                 <&gcc GCC_USB20_MASTER_CLK>,
 905                                 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 906                                 <&gcc GCC_USB20_SLEEP_CLK>,
 907                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
 908
 909                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 910                                           <&gcc GCC_USB20_MASTER_CLK>;
 911                         assigned-clock-rates = <19200000>, <60000000>;
 912
 913                         power-domains = <&gcc USB30_GDSC>;
 914                         status = "disabled";
 915
 916                         dwc3@7600000 {
 917                                 compatible = "snps,dwc3";
 918                                 reg = <0x7600000 0xcc00>;
 919                                 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
 920                                 phys = <&hsusb_phy2>;
 921                                 phy-names = "usb2-phy";
 922                         };
 923                 };
 924
 925                 usb3: usb@6af8800 {
 926                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
 927                         reg = <0x6af8800 0x400>;
 928                         #address-cells = <1>;
 929                         #size-cells = <1>;
 930                         ranges;
 931
 932                         clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
 933                                 <&gcc GCC_USB30_MASTER_CLK>,
 934                                 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
 935                                 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 936                                 <&gcc GCC_USB30_SLEEP_CLK>,
 937                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
 938
 939                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 940                                           <&gcc GCC_USB30_MASTER_CLK>;
 941                         assigned-clock-rates = <19200000>, <120000000>;
 942
 943                         power-domains = <&gcc USB30_GDSC>;
 944                         status = "disabled";
 945
 946                         dwc3@6a00000 {
 947                                 compatible = "snps,dwc3";
 948                                 reg = <0x6a00000 0xcc00>;
 949                                 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
 950                                 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
 951                                 phy-names = "usb2-phy", "usb3-phy";
 952                         };
 953                 };
 954
 955                 vfe_smmu: arm,smmu@da0000 {
 956                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
 957                         reg = <0xda0000 0x10000>;
 958
 959                         #global-interrupts = <1>;
 960                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 961                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
 962                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
 963                         power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
 964                         clocks = <&mmcc SMMU_VFE_AHB_CLK>,
 965                                  <&mmcc SMMU_VFE_AXI_CLK>;
 966                         clock-names = "iface",
 967                                       "bus";
 968                         #iommu-cells = <1>;
 969                         status = "ok";
 970                 };
 971
 972                 camss: camss@a00000 {
 973                         compatible = "qcom,msm8996-camss";
 974                         reg = <0xa34000 0x1000>,
 975                                 <0xa00030 0x4>,
 976                                 <0xa35000 0x1000>,
 977                                 <0xa00038 0x4>,
 978                                 <0xa36000 0x1000>,
 979                                 <0xa00040 0x4>,
 980                                 <0xa30000 0x100>,
 981                                 <0xa30400 0x100>,
 982                                 <0xa30800 0x100>,
 983                                 <0xa30c00 0x100>,
 984                                 <0xa31000 0x500>,
 985                                 <0xa00020 0x10>,
 986                                 <0xa10000 0x1000>,
 987                                 <0xa14000 0x1000>;
 988                         reg-names = "csiphy0",
 989                                 "csiphy0_clk_mux",
 990                                 "csiphy1",
 991                                 "csiphy1_clk_mux",
 992                                 "csiphy2",
 993                                 "csiphy2_clk_mux",
 994                                 "csid0",
 995                                 "csid1",
 996                                 "csid2",
 997                                 "csid3",
 998                                 "ispif",
 999                                 "csi_clk_mux",
1000                                 "vfe0",
1001                                 "vfe1";
1002                         interrupts = <GIC_SPI 78 0>,
1003                                 <GIC_SPI 79 0>,
1004                                 <GIC_SPI 80 0>,
1005                                 <GIC_SPI 296 0>,
1006                                 <GIC_SPI 297 0>,
1007                                 <GIC_SPI 298 0>,
1008                                 <GIC_SPI 299 0>,
1009                                 <GIC_SPI 309 0>,
1010                                 <GIC_SPI 314 0>,
1011                                 <GIC_SPI 315 0>;
1012                         interrupt-names = "csiphy0",
1013                                 "csiphy1",
1014                                 "csiphy2",
1015                                 "csid0",
1016                                 "csid1",
1017                                 "csid2",
1018                                 "csid3",
1019                                 "ispif",
1020                                 "vfe0",
1021                                 "vfe1";
1022                         power-domains = <&mmcc VFE0_GDSC>;
1023                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1024                                 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1025                                 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1026                                 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1027                                 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1028                                 <&mmcc CAMSS_CSI0_AHB_CLK>,
1029                                 <&mmcc CAMSS_CSI0_CLK>,
1030                                 <&mmcc CAMSS_CSI0PHY_CLK>,
1031                                 <&mmcc CAMSS_CSI0PIX_CLK>,
1032                                 <&mmcc CAMSS_CSI0RDI_CLK>,
1033                                 <&mmcc CAMSS_CSI1_AHB_CLK>,
1034                                 <&mmcc CAMSS_CSI1_CLK>,
1035                                 <&mmcc CAMSS_CSI1PHY_CLK>,
1036                                 <&mmcc CAMSS_CSI1PIX_CLK>,
1037                                 <&mmcc CAMSS_CSI1RDI_CLK>,
1038                                 <&mmcc CAMSS_CSI2_AHB_CLK>,
1039                                 <&mmcc CAMSS_CSI2_CLK>,
1040                                 <&mmcc CAMSS_CSI2PHY_CLK>,
1041                                 <&mmcc CAMSS_CSI2PIX_CLK>,
1042                                 <&mmcc CAMSS_CSI2RDI_CLK>,
1043                                 <&mmcc CAMSS_CSI3_AHB_CLK>,
1044                                 <&mmcc CAMSS_CSI3_CLK>,
1045                                 <&mmcc CAMSS_CSI3PHY_CLK>,
1046                                 <&mmcc CAMSS_CSI3PIX_CLK>,
1047                                 <&mmcc CAMSS_CSI3RDI_CLK>,
1048                                 <&mmcc CAMSS_AHB_CLK>,
1049                                 <&mmcc CAMSS_VFE0_CLK>,
1050                                 <&mmcc CAMSS_CSI_VFE0_CLK>,
1051                                 <&mmcc CAMSS_VFE0_AHB_CLK>,
1052                                 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1053                                 <&mmcc CAMSS_VFE1_CLK>,
1054                                 <&mmcc CAMSS_CSI_VFE1_CLK>,
1055                                 <&mmcc CAMSS_VFE1_AHB_CLK>,
1056                                 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1057                                 <&mmcc CAMSS_VFE_AHB_CLK>,
1058                                 <&mmcc CAMSS_VFE_AXI_CLK>;
1059                         clock-names = "top_ahb",
1060                                 "ispif_ahb",
1061                                 "csiphy0_timer",
1062                                 "csiphy1_timer",
1063                                 "csiphy2_timer",
1064                                 "csi0_ahb",
1065                                 "csi0",
1066                                 "csi0_phy",
1067                                 "csi0_pix",
1068                                 "csi0_rdi",
1069                                 "csi1_ahb",
1070                                 "csi1",
1071                                 "csi1_phy",
1072                                 "csi1_pix",
1073                                 "csi1_rdi",
1074                                 "csi2_ahb",
1075                                 "csi2",
1076                                 "csi2_phy",
1077                                 "csi2_pix",
1078                                 "csi2_rdi",
1079                                 "csi3_ahb",
1080                                 "csi3",
1081                                 "csi3_phy",
1082                                 "csi3_pix",
1083                                 "csi3_rdi",
1084                                 "ahb",
1085                                 "vfe0",
1086                                 "csi_vfe0",
1087                                 "vfe0_ahb",
1088                                 "vfe0_stream",
1089                                 "vfe1",
1090                                 "csi_vfe1",
1091                                 "vfe1_ahb",
1092                                 "vfe1_stream",
1093                                 "vfe_ahb",
1094                                 "vfe_axi";
1095                         vdda-supply = <&pm8994_l2>;
1096                         iommus = <&vfe_smmu 0>,
1097                                  <&vfe_smmu 1>,
1098                                  <&vfe_smmu 2>,
1099                                  <&vfe_smmu 3>;
1100                         status = "disabled";
1101                         ports {
1102                                 #address-cells = <1>;
1103                                 #size-cells = <0>;
1104                         };
1105                 };
1106
1107                 agnoc@0 {
1108                         power-domains = <&gcc AGGRE0_NOC_GDSC>;
1109                         compatible = "simple-pm-bus";
1110                         #address-cells = <1>;
1111                         #size-cells = <1>;
1112                         ranges;
1113
1114                         pcie0: pcie@600000 {
1115                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1116                                 status = "disabled";
1117                                 power-domains = <&gcc PCIE0_GDSC>;
1118                                 bus-range = <0x00 0xff>;
1119                                 num-lanes = <1>;
1120
1121                                 reg = <0x00600000 0x2000>,
1122                                       <0x0c000000 0xf1d>,
1123                                       <0x0c000f20 0xa8>,
1124                                       <0x0c100000 0x100000>;
1125                                 reg-names = "parf", "dbi", "elbi","config";
1126
1127                                 phys = <&pciephy_0>;
1128                                 phy-names = "pciephy";
1129
1130                                 #address-cells = <3>;
1131                                 #size-cells = <2>;
1132                                 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1133                                         <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1134
1135                                 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1136                                 interrupt-names = "msi";
1137                                 #interrupt-cells = <1>;
1138                                 interrupt-map-mask = <0 0 0 0x7>;
1139                                 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1140                                                 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1141                                                 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1142                                                 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1143
1144                                 pinctrl-names = "default", "sleep";
1145                                 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
1146                                 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
1147
1148
1149                                 vdda-supply = <&pm8994_l28>;
1150
1151                                 linux,pci-domain = <0>;
1152
1153                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1154                                         <&gcc GCC_PCIE_0_AUX_CLK>,
1155                                         <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1156                                         <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1157                                         <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1158
1159                                 clock-names =  "pipe",
1160                                                 "aux",
1161                                                 "cfg",
1162                                                 "bus_master",
1163                                                 "bus_slave";
1164
1165                         };
1166
1167                         pcie1: pcie@608000 {
1168                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1169                                 power-domains = <&gcc PCIE1_GDSC>;
1170                                 bus-range = <0x00 0xff>;
1171                                 num-lanes = <1>;
1172
1173                                 status  = "disabled";
1174
1175                                 reg = <0x00608000 0x2000>,
1176                                       <0x0d000000 0xf1d>,
1177                                       <0x0d000f20 0xa8>,
1178                                       <0x0d100000 0x100000>;
1179
1180                                 reg-names = "parf", "dbi", "elbi","config";
1181
1182                                 phys = <&pciephy_1>;
1183                                 phy-names = "pciephy";
1184
1185                                 #address-cells = <3>;
1186                                 #size-cells = <2>;
1187                                 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1188                                         <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1189
1190                                 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1191                                 interrupt-names = "msi";
1192                                 #interrupt-cells = <1>;
1193                                 interrupt-map-mask = <0 0 0 0x7>;
1194                                 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1195                                                 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1196                                                 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1197                                                 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1198
1199                                 pinctrl-names = "default", "sleep";
1200                                 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
1201                                 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
1202
1203
1204                                 vdda-supply = <&pm8994_l28>;
1205                                 linux,pci-domain = <1>;
1206
1207                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1208                                         <&gcc GCC_PCIE_1_AUX_CLK>,
1209                                         <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1210                                         <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1211                                         <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1212
1213                                 clock-names =  "pipe",
1214                                                 "aux",
1215                                                 "cfg",
1216                                                 "bus_master",
1217                                                 "bus_slave";
1218                         };
1219
1220                         pcie2: pcie@610000 {
1221                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1222                                 power-domains = <&gcc PCIE2_GDSC>;
1223                                 bus-range = <0x00 0xff>;
1224                                 num-lanes = <1>;
1225                                 status = "disabled";
1226                                 reg = <0x00610000 0x2000>,
1227                                       <0x0e000000 0xf1d>,
1228                                       <0x0e000f20 0xa8>,
1229                                       <0x0e100000 0x100000>;
1230
1231                                 reg-names = "parf", "dbi", "elbi","config";
1232
1233                                 phys = <&pciephy_2>;
1234                                 phy-names = "pciephy";
1235
1236                                 #address-cells = <3>;
1237                                 #size-cells = <2>;
1238                                 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1239                                         <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1240
1241                                 device_type = "pci";
1242
1243                                 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1244                                 interrupt-names = "msi";
1245                                 #interrupt-cells = <1>;
1246                                 interrupt-map-mask = <0 0 0 0x7>;
1247                                 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1248                                                 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1249                                                 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1250                                                 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1251
1252                                 pinctrl-names = "default", "sleep";
1253                                 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
1254                                 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
1255
1256                                 vdda-supply = <&pm8994_l28>;
1257
1258                                 linux,pci-domain = <2>;
1259                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1260                                         <&gcc GCC_PCIE_2_AUX_CLK>,
1261                                         <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1262                                         <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1263                                         <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1264
1265                                 clock-names =  "pipe",
1266                                                 "aux",
1267                                                 "cfg",
1268                                                 "bus_master",
1269                                                 "bus_slave";
1270                         };
1271                 };
1272         };
1273
1274         adsp-pil {
1275                 compatible = "qcom,msm8996-adsp-pil";
1276
1277                 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
1278                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1279                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1280                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1281                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1282                 interrupt-names = "wdog", "fatal", "ready",
1283                                   "handover", "stop-ack";
1284
1285                 clocks = <&xo_board>;
1286                 clock-names = "xo";
1287
1288                 memory-region = <&adsp_region>;
1289
1290                 qcom,smem-states = <&adsp_smp2p_out 0>;
1291                 qcom,smem-state-names = "stop";
1292
1293                 smd-edge {
1294                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1295
1296                         label = "lpass";
1297                         mboxes = <&apcs_glb 8>;
1298                         qcom,smd-edge = <1>;
1299                         qcom,remote-pid = <2>;
1300                 };
1301         };
1302
1303         adsp-smp2p {
1304                 compatible = "qcom,smp2p";
1305                 qcom,smem = <443>, <429>;
1306
1307                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
1308
1309                 mboxes = <&apcs_glb 10>;
1310
1311                 qcom,local-pid = <0>;
1312                 qcom,remote-pid = <2>;
1313
1314                 adsp_smp2p_out: master-kernel {
1315                         qcom,entry-name = "master-kernel";
1316                         #qcom,smem-state-cells = <1>;
1317                 };
1318
1319                 adsp_smp2p_in: slave-kernel {
1320                         qcom,entry-name = "slave-kernel";
1321
1322                         interrupt-controller;
1323                         #interrupt-cells = <2>;
1324                 };
1325         };
1326
1327         modem-smp2p {
1328                 compatible = "qcom,smp2p";
1329                 qcom,smem = <435>, <428>;
1330
1331                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1332
1333                 mboxes = <&apcs_glb 14>;
1334
1335                 qcom,local-pid = <0>;
1336                 qcom,remote-pid = <1>;
1337
1338                 modem_smp2p_out: master-kernel {
1339                         qcom,entry-name = "master-kernel";
1340                         #qcom,smem-state-cells = <1>;
1341                 };
1342
1343                 modem_smp2p_in: slave-kernel {
1344                         qcom,entry-name = "slave-kernel";
1345
1346                         interrupt-controller;
1347                         #interrupt-cells = <2>;
1348                 };
1349         };
1350
1351         smp2p-slpi {
1352                 compatible = "qcom,smp2p";
1353                 qcom,smem = <481>, <430>;
1354
1355                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
1356
1357                 mboxes = <&apcs_glb 26>;
1358
1359                 qcom,local-pid = <0>;
1360                 qcom,remote-pid = <3>;
1361
1362                 slpi_smp2p_in: slave-kernel {
1363                         qcom,entry-name = "slave-kernel";
1364                         interrupt-controller;
1365                         #interrupt-cells = <2>;
1366                 };
1367
1368                 slpi_smp2p_out: master-kernel {
1369                         qcom,entry-name = "master-kernel";
1370                         #qcom,smem-state-cells = <1>;
1371                 };
1372         };
1373
1374 };
1375 #include "msm8996-pins.dtsi"