arch/arm64/boot/dts/qcom/msm8996.dtsi

   1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  15 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
  16 #include <dt-bindings/clock/qcom,rpmcc.h>
  17
  18 / {
  19         model = "Qualcomm Technologies, Inc. MSM8996";
  20
  21         interrupt-parent = <&intc>;
  22
  23         #address-cells = <2>;
  24         #size-cells = <2>;
  25
  26         chosen { };
  27
  28         memory {
  29                 device_type = "memory";
  30                 /* We expect the bootloader to fill in the reg */
  31                 reg = <0 0 0 0>;
  32         };
  33
  34         reserved-memory {
  35                 #address-cells = <2>;
  36                 #size-cells = <2>;
  37                 ranges;
  38
  39                 mba_region: mba@91500000 {
  40                         reg = <0x0 0x91500000 0x0 0x200000>;
  41                         no-map;
  42                 };
  43
  44                 slpi_region: slpi@90b00000 {
  45                         reg = <0x0 0x90b00000 0x0 0xa00000>;
  46                         no-map;
  47                 };
  48
  49                 venus_region: venus@90400000 {
  50                         reg = <0x0 0x90400000 0x0 0x700000>;
  51                         no-map;
  52                 };
  53
  54                 adsp_region: adsp@8ea00000 {
  55                         reg = <0x0 0x8ea00000 0x0 0x1a00000>;
  56                         no-map;
  57                 };
  58
  59                 mpss_region: mpss@88800000 {
  60                         reg = <0x0 0x88800000 0x0 0x6200000>;
  61                         no-map;
  62                 };
  63
  64                 smem_mem: smem-mem@86000000 {
  65                         reg = <0x0 0x86000000 0x0 0x200000>;
  66                         no-map;
  67                 };
  68
  69                 memory@85800000 {
  70                         reg = <0x0 0x85800000 0x0 0x800000>;
  71                         no-map;
  72                 };
  73
  74                 memory@86200000 {
  75                         reg = <0x0 0x86200000 0x0 0x2600000>;
  76                         no-map;
  77                 };
  78
  79                 rmtfs@86700000 {
  80                         compatible = "qcom,rmtfs-mem";
  81
  82                         size = <0x0 0x200000>;
  83                         alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
  84                         no-map;
  85
  86                         qcom,client-id = <1>;
  87                         qcom,vmid = <15>;
  88                 };
  89         };
  90
  91         cpus {
  92                 #address-cells = <2>;
  93                 #size-cells = <0>;
  94
  95                 CPU0: cpu@0 {
  96                         device_type = "cpu";
  97                         compatible = "qcom,kryo";
  98                         reg = <0x0 0x0>;
  99                         enable-method = "psci";
 100                         next-level-cache = <&L2_0>;
 101                         L2_0: l2-cache {
 102                               compatible = "cache";
 103                               cache-level = <2>;
 104                         };
 105                 };
 106
 107                 CPU1: cpu@1 {
 108                         device_type = "cpu";
 109                         compatible = "qcom,kryo";
 110                         reg = <0x0 0x1>;
 111                         enable-method = "psci";
 112                         next-level-cache = <&L2_0>;
 113                 };
 114
 115                 CPU2: cpu@100 {
 116                         device_type = "cpu";
 117                         compatible = "qcom,kryo";
 118                         reg = <0x0 0x100>;
 119                         enable-method = "psci";
 120                         next-level-cache = <&L2_1>;
 121                         L2_1: l2-cache {
 122                               compatible = "cache";
 123                               cache-level = <2>;
 124                         };
 125                 };
 126
 127                 CPU3: cpu@101 {
 128                         device_type = "cpu";
 129                         compatible = "qcom,kryo";
 130                         reg = <0x0 0x101>;
 131                         enable-method = "psci";
 132                         next-level-cache = <&L2_1>;
 133                 };
 134
 135                 cpu-map {
 136                         cluster0 {
 137                                 core0 {
 138                                         cpu = <&CPU0>;
 139                                 };
 140
 141                                 core1 {
 142                                         cpu = <&CPU1>;
 143                                 };
 144                         };
 145
 146                         cluster1 {
 147                                 core0 {
 148                                         cpu = <&CPU2>;
 149                                 };
 150
 151                                 core1 {
 152                                         cpu = <&CPU3>;
 153                                 };
 154                         };
 155                 };
 156         };
 157
 158         thermal-zones {
 159                 cpu-thermal0 {
 160                         polling-delay-passive = <250>;
 161                         polling-delay = <1000>;
 162
 163                         thermal-sensors = <&tsens0 3>;
 164
 165                         trips {
 166                                 cpu_alert0: trip0 {
 167                                         temperature = <75000>;
 168                                         hysteresis = <2000>;
 169                                         type = "passive";
 170                                 };
 171
 172                                 cpu_crit0: trip1 {
 173                                         temperature = <110000>;
 174                                         hysteresis = <2000>;
 175                                         type = "critical";
 176                                 };
 177                         };
 178                 };
 179
 180                 cpu-thermal1 {
 181                         polling-delay-passive = <250>;
 182                         polling-delay = <1000>;
 183
 184                         thermal-sensors = <&tsens0 5>;
 185
 186                         trips {
 187                                 cpu_alert1: trip0 {
 188                                         temperature = <75000>;
 189                                         hysteresis = <2000>;
 190                                         type = "passive";
 191                                 };
 192
 193                                 cpu_crit1: trip1 {
 194                                         temperature = <110000>;
 195                                         hysteresis = <2000>;
 196                                         type = "critical";
 197                                 };
 198                         };
 199                 };
 200
 201                 cpu-thermal2 {
 202                         polling-delay-passive = <250>;
 203                         polling-delay = <1000>;
 204
 205                         thermal-sensors = <&tsens0 8>;
 206
 207                         trips {
 208                                 cpu_alert2: trip0 {
 209                                         temperature = <75000>;
 210                                         hysteresis = <2000>;
 211                                         type = "passive";
 212                                 };
 213
 214                                 cpu_crit2: trip1 {
 215                                         temperature = <110000>;
 216                                         hysteresis = <2000>;
 217                                         type = "critical";
 218                                 };
 219                         };
 220                 };
 221
 222                 cpu-thermal3 {
 223                         polling-delay-passive = <250>;
 224                         polling-delay = <1000>;
 225
 226                         thermal-sensors = <&tsens0 10>;
 227
 228                         trips {
 229                                 cpu_alert3: trip0 {
 230                                         temperature = <75000>;
 231                                         hysteresis = <2000>;
 232                                         type = "passive";
 233                                 };
 234
 235                                 cpu_crit3: trip1 {
 236                                         temperature = <110000>;
 237                                         hysteresis = <2000>;
 238                                         type = "critical";
 239                                 };
 240                         };
 241                 };
 242         };
 243
 244         timer {
 245                 compatible = "arm,armv8-timer";
 246                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 247                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 248                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 249                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 250         };
 251
 252         clocks {
 253                 xo_board: xo_board {
 254                         compatible = "fixed-clock";
 255                         #clock-cells = <0>;
 256                         clock-frequency = <19200000>;
 257                         clock-output-names = "xo_board";
 258                 };
 259
 260                 sleep_clk: sleep_clk {
 261                         compatible = "fixed-clock";
 262                         #clock-cells = <0>;
 263                         clock-frequency = <32764>;
 264                         clock-output-names = "sleep_clk";
 265                 };
 266         };
 267
 268         psci {
 269                 compatible = "arm,psci-1.0";
 270                 method = "smc";
 271         };
 272
 273         firmware {
 274                 scm {
 275                         compatible = "qcom,scm-msm8996";
 276
 277                         qcom,dload-mode = <&tcsr 0x13000>;
 278                 };
 279         };
 280
 281         tcsr_mutex: hwlock {
 282                 compatible = "qcom,tcsr-mutex";
 283                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 284                 #hwlock-cells = <1>;
 285         };
 286
 287         smem {
 288                 compatible = "qcom,smem";
 289                 memory-region = <&smem_mem>;
 290                 hwlocks = <&tcsr_mutex 3>;
 291         };
 292
 293         rpm-glink {
 294                 compatible = "qcom,glink-rpm";
 295
 296                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 297
 298                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 299
 300                 mboxes = <&apcs_glb 0>;
 301
 302                 rpm_requests {
 303                         compatible = "qcom,rpm-msm8996";
 304                         qcom,glink-channels = "rpm_requests";
 305
 306                         rpmcc: qcom,rpmcc {
 307                                 compatible = "qcom,rpmcc-msm8996";
 308                                 #clock-cells = <1>;
 309                         };
 310
 311                         pm8994-regulators {
 312                                 compatible = "qcom,rpm-pm8994-regulators";
 313
 314                                 pm8994_s1: s1 {};
 315                                 pm8994_s2: s2 {};
 316                                 pm8994_s3: s3 {};
 317                                 pm8994_s4: s4 {};
 318                                 pm8994_s5: s5 {};
 319                                 pm8994_s6: s6 {};
 320                                 pm8994_s7: s7 {};
 321                                 pm8994_s8: s8 {};
 322                                 pm8994_s9: s9 {};
 323                                 pm8994_s10: s10 {};
 324                                 pm8994_s11: s11 {};
 325                                 pm8994_s12: s12 {};
 326
 327                                 pm8994_l1: l1 {};
 328                                 pm8994_l2: l2 {};
 329                                 pm8994_l3: l3 {};
 330                                 pm8994_l4: l4 {};
 331                                 pm8994_l5: l5 {};
 332                                 pm8994_l6: l6 {};
 333                                 pm8994_l7: l7 {};
 334                                 pm8994_l8: l8 {};
 335                                 pm8994_l9: l9 {};
 336                                 pm8994_l10: l10 {};
 337                                 pm8994_l11: l11 {};
 338                                 pm8994_l12: l12 {};
 339                                 pm8994_l13: l13 {};
 340                                 pm8994_l14: l14 {};
 341                                 pm8994_l15: l15 {};
 342                                 pm8994_l16: l16 {};
 343                                 pm8994_l17: l17 {};
 344                                 pm8994_l18: l18 {};
 345                                 pm8994_l19: l19 {};
 346                                 pm8994_l20: l20 {};
 347                                 pm8994_l21: l21 {};
 348                                 pm8994_l22: l22 {};
 349                                 pm8994_l23: l23 {};
 350                                 pm8994_l24: l24 {};
 351                                 pm8994_l25: l25 {};
 352                                 pm8994_l26: l26 {};
 353                                 pm8994_l27: l27 {};
 354                                 pm8994_l28: l28 {};
 355                                 pm8994_l29: l29 {};
 356                                 pm8994_l30: l30 {};
 357                                 pm8994_l31: l31 {};
 358                                 pm8994_l32: l32 {};
 359                         };
 360
 361                 };
 362         };
 363
 364         soc: soc {
 365                 #address-cells = <1>;
 366                 #size-cells = <1>;
 367                 ranges = <0 0 0 0xffffffff>;
 368                 compatible = "simple-bus";
 369
 370                 rpm_msg_ram: memory@68000 {
 371                         compatible = "qcom,rpm-msg-ram";
 372                         reg = <0x68000 0x6000>;
 373                 };
 374
 375                 tcsr_mutex_regs: syscon@740000 {
 376                         compatible = "syscon";
 377                         reg = <0x740000 0x20000>;
 378                 };
 379
 380                 tcsr: syscon@7a0000 {
 381                         compatible = "qcom,tcsr-msm8996", "syscon";
 382                         reg = <0x7a0000 0x18000>;
 383                 };
 384
 385                 intc: interrupt-controller@9bc0000 {
 386                         compatible = "arm,gic-v3";
 387                         #interrupt-cells = <3>;
 388                         interrupt-controller;
 389                         #redistributor-regions = <1>;
 390                         redistributor-stride = <0x0 0x40000>;
 391                         reg = <0x09bc0000 0x10000>,
 392                               <0x09c00000 0x100000>;
 393                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 394                 };
 395
 396                 apcs: syscon@9820000 {
 397                         compatible = "syscon";
 398                         reg = <0x9820000 0x1000>;
 399                 };
 400
 401                 apcs_glb: mailbox@9820000 {
 402                         compatible = "qcom,msm8996-apcs-hmss-global";
 403                         reg = <0x9820000 0x1000>;
 404
 405                         #mbox-cells = <1>;
 406                 };
 407
 408                 gcc: clock-controller@300000 {
 409                         compatible = "qcom,gcc-msm8996";
 410                         #clock-cells = <1>;
 411                         #reset-cells = <1>;
 412                         #power-domain-cells = <1>;
 413                         reg = <0x300000 0x90000>;
 414                 };
 415
 416                 kryocc: clock-controller@6400000 {
 417                         compatible = "qcom,apcc-msm8996";
 418                         reg = <0x6400000 0x90000>;
 419                         #clock-cells = <1>;
 420                 };
 421
 422                 blsp1_spi0: spi@7575000 {
 423                         compatible = "qcom,spi-qup-v2.2.1";
 424                         reg = <0x07575000 0x600>;
 425                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 426                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 427                                  <&gcc GCC_BLSP1_AHB_CLK>;
 428                         clock-names = "core", "iface";
 429                         pinctrl-names = "default", "sleep";
 430                         pinctrl-0 = <&blsp1_spi0_default>;
 431                         pinctrl-1 = <&blsp1_spi0_sleep>;
 432                         #address-cells = <1>;
 433                         #size-cells = <0>;
 434                         status = "disabled";
 435                 };
 436
 437                 blsp2_i2c0: i2c@75b5000 {
 438                         compatible = "qcom,i2c-qup-v2.2.1";
 439                         reg = <0x075b5000 0x1000>;
 440                         interrupts = <GIC_SPI 101 0>;
 441                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 442                                 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
 443                         clock-names = "iface", "core";
 444                         pinctrl-names = "default", "sleep";
 445                         pinctrl-0 = <&blsp2_i2c0_default>;
 446                         pinctrl-1 = <&blsp2_i2c0_sleep>;
 447                         #address-cells = <1>;
 448                         #size-cells = <0>;
 449                         status = "disabled";
 450                 };
 451
 452                 tsens0: thermal-sensor@4a8000 {
 453                         compatible = "qcom,msm8996-tsens";
 454                         reg = <0x4a8000 0x2000>;
 455                         #thermal-sensor-cells = <1>;
 456                 };
 457
 458                 blsp2_uart1: serial@75b0000 {
 459                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 460                         reg = <0x75b0000 0x1000>;
 461                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 462                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 463                                  <&gcc GCC_BLSP2_AHB_CLK>;
 464                         clock-names = "core", "iface";
 465                         status = "disabled";
 466                 };
 467
 468                 blsp2_i2c1: i2c@75b6000 {
 469                         compatible = "qcom,i2c-qup-v2.2.1";
 470                         reg = <0x075b6000 0x1000>;
 471                         interrupts = <GIC_SPI 102 0>;
 472                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 473                                 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
 474                         clock-names = "iface", "core";
 475                         pinctrl-names = "default", "sleep";
 476                         pinctrl-0 = <&blsp2_i2c1_default>;
 477                         pinctrl-1 = <&blsp2_i2c1_sleep>;
 478                         #address-cells = <1>;
 479                         #size-cells = <0>;
 480                         status = "disabled";
 481                 };
 482
 483                 blsp2_uart2: serial@75b1000 {
 484                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 485                         reg = <0x075b1000 0x1000>;
 486                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 487                         clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
 488                                  <&gcc GCC_BLSP2_AHB_CLK>;
 489                         clock-names = "core", "iface";
 490                         status = "disabled";
 491                 };
 492
 493                 blsp1_i2c2: i2c@7577000 {
 494                         compatible = "qcom,i2c-qup-v2.2.1";
 495                         reg = <0x07577000 0x1000>;
 496                         interrupts = <GIC_SPI 97 0>;
 497                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 498                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 499                         clock-names = "iface", "core";
 500                         pinctrl-names = "default", "sleep";
 501                         pinctrl-0 = <&blsp1_i2c2_default>;
 502                         pinctrl-1 = <&blsp1_i2c2_sleep>;
 503                         #address-cells = <1>;
 504                         #size-cells = <0>;
 505                         status = "disabled";
 506                 };
 507
 508                 blsp2_spi5: spi@75ba000{
 509                         compatible = "qcom,spi-qup-v2.2.1";
 510                         reg = <0x075ba000 0x600>;
 511                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 512                         clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
 513                                  <&gcc GCC_BLSP2_AHB_CLK>;
 514                         clock-names = "core", "iface";
 515                         pinctrl-names = "default", "sleep";
 516                         pinctrl-0 = <&blsp2_spi5_default>;
 517                         pinctrl-1 = <&blsp2_spi5_sleep>;
 518                         #address-cells = <1>;
 519                         #size-cells = <0>;
 520                         status = "disabled";
 521                 };
 522
 523                 sdhc2: sdhci@74a4900 {
 524                          status = "disabled";
 525                          compatible = "qcom,sdhci-msm-v4";
 526                          reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
 527                          reg-names = "hc_mem", "core_mem";
 528
 529                          interrupts = <0 125 0>, <0 221 0>;
 530                          interrupt-names = "hc_irq", "pwr_irq";
 531
 532                          clock-names = "iface", "core", "xo";
 533                          clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 534                          <&gcc GCC_SDCC2_APPS_CLK>,
 535                          <&xo_board>;
 536                          bus-width = <4>;
 537                  };
 538
 539                 msmgpio: pinctrl@1010000 {
 540                         compatible = "qcom,msm8996-pinctrl";
 541                         reg = <0x01010000 0x300000>;
 542                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 543                         gpio-controller;
 544                         #gpio-cells = <2>;
 545                         interrupt-controller;
 546                         #interrupt-cells = <2>;
 547                 };
 548
 549                 timer@9840000 {
 550                         #address-cells = <1>;
 551                         #size-cells = <1>;
 552                         ranges;
 553                         compatible = "arm,armv7-timer-mem";
 554                         reg = <0x09840000 0x1000>;
 555                         clock-frequency = <19200000>;
 556
 557                         frame@9850000 {
 558                                 frame-number = <0>;
 559                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 560                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 561                                 reg = <0x09850000 0x1000>,
 562                                       <0x09860000 0x1000>;
 563                         };
 564
 565                         frame@9870000 {
 566                                 frame-number = <1>;
 567                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 568                                 reg = <0x09870000 0x1000>;
 569                                 status = "disabled";
 570                         };
 571
 572                         frame@9880000 {
 573                                 frame-number = <2>;
 574                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 575                                 reg = <0x09880000 0x1000>;
 576                                 status = "disabled";
 577                         };
 578
 579                         frame@9890000 {
 580                                 frame-number = <3>;
 581                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 582                                 reg = <0x09890000 0x1000>;
 583                                 status = "disabled";
 584                         };
 585
 586                         frame@98a0000 {
 587                                 frame-number = <4>;
 588                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 589                                 reg = <0x098a0000 0x1000>;
 590                                 status = "disabled";
 591                         };
 592
 593                         frame@98b0000 {
 594                                 frame-number = <5>;
 595                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 596                                 reg = <0x098b0000 0x1000>;
 597                                 status = "disabled";
 598                         };
 599
 600                         frame@98c0000 {
 601                                 frame-number = <6>;
 602                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 603                                 reg = <0x098c0000 0x1000>;
 604                                 status = "disabled";
 605                         };
 606                 };
 607
 608                 spmi_bus: qcom,spmi@400f000 {
 609                         compatible = "qcom,spmi-pmic-arb";
 610                         reg = <0x400f000 0x1000>,
 611                               <0x4400000 0x800000>,
 612                               <0x4c00000 0x800000>,
 613                               <0x5800000 0x200000>,
 614                               <0x400a000 0x002100>;
 615                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 616                         interrupt-names = "periph_irq";
 617                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
 618                         qcom,ee = <0>;
 619                         qcom,channel = <0>;
 620                         #address-cells = <2>;
 621                         #size-cells = <0>;
 622                         interrupt-controller;
 623                         #interrupt-cells = <4>;
 624                 };
 625
 626                 mmcc: clock-controller@8c0000 {
 627                         compatible = "qcom,mmcc-msm8996";
 628                         #clock-cells = <1>;
 629                         #reset-cells = <1>;
 630                         #power-domain-cells = <1>;
 631                         reg = <0x8c0000 0x40000>;
 632                         assigned-clocks = <&mmcc MMPLL9_PLL>,
 633                                           <&mmcc MMPLL1_PLL>,
 634                                           <&mmcc MMPLL3_PLL>,
 635                                           <&mmcc MMPLL4_PLL>,
 636                                           <&mmcc MMPLL5_PLL>;
 637                         assigned-clock-rates = <624000000>,
 638                                                <810000000>,
 639                                                <980000000>,
 640                                                <960000000>,
 641                                                <825000000>;
 642                 };
 643
 644                 qfprom@74000 {
 645                         compatible = "qcom,qfprom";
 646                         reg = <0x74000 0x8ff>;
 647                         #address-cells = <1>;
 648                         #size-cells = <1>;
 649
 650                         qusb2p_hstx_trim: hstx_trim@24e {
 651                                 reg = <0x24e 0x2>;
 652                                 bits = <5 4>;
 653                         };
 654
 655                         qusb2s_hstx_trim: hstx_trim@24f {
 656                                 reg = <0x24f 0x1>;
 657                                 bits = <1 4>;
 658                         };
 659                 };
 660
 661                 phy@34000 {
 662                         compatible = "qcom,msm8996-qmp-pcie-phy";
 663                         reg = <0x34000 0x488>;
 664                         #clock-cells = <1>;
 665                         #address-cells = <1>;
 666                         #size-cells = <1>;
 667                         ranges;
 668
 669                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 670                                 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
 671                                 <&gcc GCC_PCIE_CLKREF_CLK>;
 672                         clock-names = "aux", "cfg_ahb", "ref";
 673
 674                         vdda-phy-supply = <&pm8994_l28>;
 675                         vdda-pll-supply = <&pm8994_l12>;
 676
 677                         resets = <&gcc GCC_PCIE_PHY_BCR>,
 678                                 <&gcc GCC_PCIE_PHY_COM_BCR>,
 679                                 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
 680                         reset-names = "phy", "common", "cfg";
 681                         status = "disabled";
 682
 683                         pciephy_0: lane@35000 {
 684                                 reg = <0x035000 0x130>,
 685                                         <0x035200 0x200>,
 686                                         <0x035400 0x1dc>;
 687                                 #phy-cells = <0>;
 688
 689                                 clock-output-names = "pcie_0_pipe_clk_src";
 690                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 691                                 clock-names = "pipe0";
 692                                 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
 693                                 reset-names = "lane0";
 694                         };
 695
 696                         pciephy_1: lane@36000 {
 697                                 reg = <0x036000 0x130>,
 698                                         <0x036200 0x200>,
 699                                         <0x036400 0x1dc>;
 700                                 #phy-cells = <0>;
 701
 702                                 clock-output-names = "pcie_1_pipe_clk_src";
 703                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
 704                                 clock-names = "pipe1";
 705                                 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
 706                                 reset-names = "lane1";
 707                         };
 708
 709                         pciephy_2: lane@37000 {
 710                                 reg = <0x037000 0x130>,
 711                                         <0x037200 0x200>,
 712                                         <0x037400 0x1dc>;
 713                                 #phy-cells = <0>;
 714
 715                                 clock-output-names = "pcie_2_pipe_clk_src";
 716                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
 717                                 clock-names = "pipe2";
 718                                 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
 719                                 reset-names = "lane2";
 720                         };
 721                 };
 722
 723                 phy@7410000 {
 724                         compatible = "qcom,msm8996-qmp-usb3-phy";
 725                         reg = <0x7410000 0x1c4>;
 726                         #clock-cells = <1>;
 727                         #address-cells = <1>;
 728                         #size-cells = <1>;
 729                         ranges;
 730
 731                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
 732                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 733                                 <&gcc GCC_USB3_CLKREF_CLK>;
 734                         clock-names = "aux", "cfg_ahb", "ref";
 735
 736                         vdda-phy-supply = <&pm8994_l28>;
 737                         vdda-pll-supply = <&pm8994_l12>;
 738
 739                         resets = <&gcc GCC_USB3_PHY_BCR>,
 740                                 <&gcc GCC_USB3PHY_PHY_BCR>;
 741                         reset-names = "phy", "common";
 742                         status = "disabled";
 743
 744                         ssusb_phy_0: lane@7410200 {
 745                                 reg = <0x7410200 0x200>,
 746                                         <0x7410400 0x130>,
 747                                         <0x7410600 0x1a8>;
 748                                 #phy-cells = <0>;
 749
 750                                 clock-output-names = "usb3_phy_pipe_clk_src";
 751                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
 752                                 clock-names = "pipe0";
 753                         };
 754                 };
 755
 756                 hsusb_phy1: phy@7411000 {
 757                         compatible = "qcom,msm8996-qusb2-phy";
 758                         reg = <0x7411000 0x180>;
 759                         #phy-cells = <0>;
 760
 761                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 762                                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
 763                         clock-names = "cfg_ahb", "ref";
 764
 765                         vdda-pll-supply = <&pm8994_l12>;
 766                         vdda-phy-dpdm-supply = <&pm8994_l24>;
 767
 768                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 769                         nvmem-cells = <&qusb2p_hstx_trim>;
 770                         status = "disabled";
 771                 };
 772
 773                 hsusb_phy2: phy@7412000 {
 774                         compatible = "qcom,msm8996-qusb2-phy";
 775                         reg = <0x7412000 0x180>;
 776                         #phy-cells = <0>;
 777
 778                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 779                                 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
 780                         clock-names = "cfg_ahb", "ref";
 781
 782                         vdda-pll-supply = <&pm8994_l12>;
 783                         vdda-phy-dpdm-supply = <&pm8994_l24>;
 784
 785                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
 786                         nvmem-cells = <&qusb2s_hstx_trim>;
 787                         status = "disabled";
 788                 };
 789
 790                 usb2: usb@7600000 {
 791                         compatible = "qcom,dwc3";
 792                         #address-cells = <1>;
 793                         #size-cells = <1>;
 794                         ranges;
 795
 796                         clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
 797                                 <&gcc GCC_USB20_MASTER_CLK>,
 798                                 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 799                                 <&gcc GCC_USB20_SLEEP_CLK>,
 800                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
 801
 802                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 803                                           <&gcc GCC_USB20_MASTER_CLK>;
 804                         assigned-clock-rates = <19200000>, <60000000>;
 805
 806                         power-domains = <&gcc USB30_GDSC>;
 807                         status = "disabled";
 808
 809                         dwc3@7600000 {
 810                                 compatible = "snps,dwc3";
 811                                 reg = <0x7600000 0xcc00>;
 812                                 interrupts = <0 138 0>;
 813                                 phys = <&hsusb_phy2>;
 814                                 phy-names = "usb2-phy";
 815                         };
 816                 };
 817
 818                 usb3: usb@6a00000 {
 819                         compatible = "qcom,dwc3";
 820                         #address-cells = <1>;
 821                         #size-cells = <1>;
 822                         ranges;
 823
 824                         clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
 825                                 <&gcc GCC_USB30_MASTER_CLK>,
 826                                 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
 827                                 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 828                                 <&gcc GCC_USB30_SLEEP_CLK>,
 829                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
 830
 831                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 832                                           <&gcc GCC_USB30_MASTER_CLK>;
 833                         assigned-clock-rates = <19200000>, <120000000>;
 834
 835                         power-domains = <&gcc USB30_GDSC>;
 836                         status = "disabled";
 837
 838                         dwc3@6a00000 {
 839                                 compatible = "snps,dwc3";
 840                                 reg = <0x6a00000 0xcc00>;
 841                                 interrupts = <0 131 0>;
 842                                 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
 843                                 phy-names = "usb2-phy", "usb3-phy";
 844                         };
 845                 };
 846
 847                 agnoc@0 {
 848                         power-domains = <&gcc AGGRE0_NOC_GDSC>;
 849                         compatible = "simple-pm-bus";
 850                         #address-cells = <1>;
 851                         #size-cells = <1>;
 852                         ranges;
 853
 854                         pcie0: qcom,pcie@600000 {
 855                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
 856                                 status = "disabled";
 857                                 power-domains = <&gcc PCIE0_GDSC>;
 858                                 bus-range = <0x00 0xff>;
 859                                 num-lanes = <1>;
 860
 861                                 reg = <0x00600000 0x2000>,
 862                                       <0x0c000000 0xf1d>,
 863                                       <0x0c000f20 0xa8>,
 864                                       <0x0c100000 0x100000>;
 865                                 reg-names = "parf", "dbi", "elbi","config";
 866
 867                                 phys = <&pciephy_0>;
 868                                 phy-names = "pciephy";
 869
 870                                 #address-cells = <3>;
 871                                 #size-cells = <2>;
 872                                 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
 873                                         <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
 874
 875                                 interrupts = <GIC_SPI 405 IRQ_TYPE_NONE>;
 876                                 interrupt-names = "msi";
 877                                 #interrupt-cells = <1>;
 878                                 interrupt-map-mask = <0 0 0 0x7>;
 879                                 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 880                                                 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 881                                                 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 882                                                 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 883
 884                                 pinctrl-names = "default", "sleep";
 885                                 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
 886                                 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
 887
 888
 889                                 vdda-supply = <&pm8994_l28>;
 890
 891                                 linux,pci-domain = <0>;
 892
 893                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
 894                                         <&gcc GCC_PCIE_0_AUX_CLK>,
 895                                         <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 896                                         <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 897                                         <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
 898
 899                                 clock-names =  "pipe",
 900                                                 "aux",
 901                                                 "cfg",
 902                                                 "bus_master",
 903                                                 "bus_slave";
 904
 905                         };
 906
 907                         pcie1: qcom,pcie@608000 {
 908                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
 909                                 power-domains = <&gcc PCIE1_GDSC>;
 910                                 bus-range = <0x00 0xff>;
 911                                 num-lanes = <1>;
 912
 913                                 status  = "disabled";
 914
 915                                 reg = <0x00608000 0x2000>,
 916                                       <0x0d000000 0xf1d>,
 917                                       <0x0d000f20 0xa8>,
 918                                       <0x0d100000 0x100000>;
 919
 920                                 reg-names = "parf", "dbi", "elbi","config";
 921
 922                                 phys = <&pciephy_1>;
 923                                 phy-names = "pciephy";
 924
 925                                 #address-cells = <3>;
 926                                 #size-cells = <2>;
 927                                 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
 928                                         <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
 929
 930                                 interrupts = <GIC_SPI 413 IRQ_TYPE_NONE>;
 931                                 interrupt-names = "msi";
 932                                 #interrupt-cells = <1>;
 933                                 interrupt-map-mask = <0 0 0 0x7>;
 934                                 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 935                                                 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 936                                                 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 937                                                 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 938
 939                                 pinctrl-names = "default", "sleep";
 940                                 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
 941                                 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
 942
 943
 944                                 vdda-supply = <&pm8994_l28>;
 945                                 linux,pci-domain = <1>;
 946
 947                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
 948                                         <&gcc GCC_PCIE_1_AUX_CLK>,
 949                                         <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
 950                                         <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
 951                                         <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
 952
 953                                 clock-names =  "pipe",
 954                                                 "aux",
 955                                                 "cfg",
 956                                                 "bus_master",
 957                                                 "bus_slave";
 958                         };
 959
 960                         pcie2: qcom,pcie@610000 {
 961                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
 962                                 power-domains = <&gcc PCIE2_GDSC>;
 963                                 bus-range = <0x00 0xff>;
 964                                 num-lanes = <1>;
 965                                 status = "disabled";
 966                                 reg = <0x00610000 0x2000>,
 967                                       <0x0e000000 0xf1d>,
 968                                       <0x0e000f20 0xa8>,
 969                                       <0x0e100000 0x100000>;
 970
 971                                 reg-names = "parf", "dbi", "elbi","config";
 972
 973                                 phys = <&pciephy_2>;
 974                                 phy-names = "pciephy";
 975
 976                                 #address-cells = <3>;
 977                                 #size-cells = <2>;
 978                                 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
 979                                         <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
 980
 981                                 device_type = "pci";
 982
 983                                 interrupts = <GIC_SPI 421 IRQ_TYPE_NONE>;
 984                                 interrupt-names = "msi";
 985                                 #interrupt-cells = <1>;
 986                                 interrupt-map-mask = <0 0 0 0x7>;
 987                                 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 988                                                 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 989                                                 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 990                                                 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 991
 992                                 pinctrl-names = "default", "sleep";
 993                                 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
 994                                 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
 995
 996                                 vdda-supply = <&pm8994_l28>;
 997
 998                                 linux,pci-domain = <2>;
 999                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1000                                         <&gcc GCC_PCIE_2_AUX_CLK>,
1001                                         <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1002                                         <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1003                                         <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1004
1005                                 clock-names =  "pipe",
1006                                                 "aux",
1007                                                 "cfg",
1008                                                 "bus_master",
1009                                                 "bus_slave";
1010                         };
1011                 };
1012         };
1013
1014         adsp-pil {
1015                 compatible = "qcom,msm8996-adsp-pil";
1016
1017                 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
1018                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1019                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1020                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1021                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1022                 interrupt-names = "wdog", "fatal", "ready",
1023                                   "handover", "stop-ack";
1024
1025                 clocks = <&xo_board>;
1026                 clock-names = "xo";
1027
1028                 memory-region = <&adsp_region>;
1029
1030                 qcom,smem-states = <&adsp_smp2p_out 0>;
1031                 qcom,smem-state-names = "stop";
1032
1033                 smd-edge {
1034                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1035
1036                         label = "lpass";
1037                         qcom,ipc = <&apcs 16 8>;
1038                         qcom,smd-edge = <1>;
1039                         qcom,remote-pid = <2>;
1040                 };
1041         };
1042
1043         adsp-smp2p {
1044                 compatible = "qcom,smp2p";
1045                 qcom,smem = <443>, <429>;
1046
1047                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
1048
1049                 qcom,ipc = <&apcs 16 10>;
1050
1051                 qcom,local-pid = <0>;
1052                 qcom,remote-pid = <2>;
1053
1054                 adsp_smp2p_out: master-kernel {
1055                         qcom,entry-name = "master-kernel";
1056                         #qcom,smem-state-cells = <1>;
1057                 };
1058
1059                 adsp_smp2p_in: slave-kernel {
1060                         qcom,entry-name = "slave-kernel";
1061
1062                         interrupt-controller;
1063                         #interrupt-cells = <2>;
1064                 };
1065         };
1066
1067         modem-smp2p {
1068                 compatible = "qcom,smp2p";
1069                 qcom,smem = <435>, <428>;
1070
1071                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1072
1073                 qcom,ipc = <&apcs 16 14>;
1074
1075                 qcom,local-pid = <0>;
1076                 qcom,remote-pid = <1>;
1077
1078                 modem_smp2p_out: master-kernel {
1079                         qcom,entry-name = "master-kernel";
1080                         #qcom,smem-state-cells = <1>;
1081                 };
1082
1083                 modem_smp2p_in: slave-kernel {
1084                         qcom,entry-name = "slave-kernel";
1085
1086                         interrupt-controller;
1087                         #interrupt-cells = <2>;
1088                 };
1089         };
1090
1091         smp2p-slpi {
1092                 compatible = "qcom,smp2p";
1093                 qcom,smem = <481>, <430>;
1094
1095                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
1096
1097                 qcom,ipc = <&apcs 16 26>;
1098
1099                 qcom,local-pid = <0>;
1100                 qcom,remote-pid = <3>;
1101
1102                 slpi_smp2p_in: slave-kernel {
1103                         qcom,entry-name = "slave-kernel";
1104                         interrupt-controller;
1105                         #interrupt-cells = <2>;
1106                 };
1107
1108                 slpi_smp2p_out: master-kernel {
1109                         qcom,entry-name = "master-kernel";
1110                         #qcom,smem-state-cells = <1>;
1111                 };
1112         };
1113
1114 };
1115 #include "msm8996-pins.dtsi"