arch/arm64/boot/dts/qcom/msm8996.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/soc/qcom,apr.h>
  10
  11 / {
  12         interrupt-parent = <&intc>;
  13
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         chosen { };
  18
  19         memory {
  20                 device_type = "memory";
  21                 /* We expect the bootloader to fill in the reg */
  22                 reg = <0 0 0 0>;
  23         };
  24
  25         reserved-memory {
  26                 #address-cells = <2>;
  27                 #size-cells = <2>;
  28                 ranges;
  29
  30                 mba_region: mba@91500000 {
  31                         reg = <0x0 0x91500000 0x0 0x200000>;
  32                         no-map;
  33                 };
  34
  35                 slpi_region: slpi@90b00000 {
  36                         reg = <0x0 0x90b00000 0x0 0xa00000>;
  37                         no-map;
  38                 };
  39
  40                 venus_region: venus@90400000 {
  41                         reg = <0x0 0x90400000 0x0 0x700000>;
  42                         no-map;
  43                 };
  44
  45                 adsp_region: adsp@8ea00000 {
  46                         reg = <0x0 0x8ea00000 0x0 0x1a00000>;
  47                         no-map;
  48                 };
  49
  50                 mpss_region: mpss@88800000 {
  51                         reg = <0x0 0x88800000 0x0 0x6200000>;
  52                         no-map;
  53                 };
  54
  55                 smem_mem: smem-mem@86000000 {
  56                         reg = <0x0 0x86000000 0x0 0x200000>;
  57                         no-map;
  58                 };
  59
  60                 memory@85800000 {
  61                         reg = <0x0 0x85800000 0x0 0x800000>;
  62                         no-map;
  63                 };
  64
  65                 memory@86200000 {
  66                         reg = <0x0 0x86200000 0x0 0x2600000>;
  67                         no-map;
  68                 };
  69
  70                 rmtfs@86700000 {
  71                         compatible = "qcom,rmtfs-mem";
  72
  73                         size = <0x0 0x200000>;
  74                         alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
  75                         no-map;
  76
  77                         qcom,client-id = <1>;
  78                         qcom,vmid = <15>;
  79                 };
  80
  81                 zap_shader_region: gpu@8f200000 {
  82                         compatible = "shared-dma-pool";
  83                         reg = <0x0 0x90b00000 0x0 0xa00000>;
  84                         no-map;
  85                 };
  86         };
  87
  88         cpus {
  89                 #address-cells = <2>;
  90                 #size-cells = <0>;
  91
  92                 CPU0: cpu@0 {
  93                         device_type = "cpu";
  94                         compatible = "qcom,kryo";
  95                         reg = <0x0 0x0>;
  96                         enable-method = "psci";
  97                         next-level-cache = <&L2_0>;
  98                         L2_0: l2-cache {
  99                               compatible = "cache";
 100                               cache-level = <2>;
 101                         };
 102                 };
 103
 104                 CPU1: cpu@1 {
 105                         device_type = "cpu";
 106                         compatible = "qcom,kryo";
 107                         reg = <0x0 0x1>;
 108                         enable-method = "psci";
 109                         next-level-cache = <&L2_0>;
 110                 };
 111
 112                 CPU2: cpu@100 {
 113                         device_type = "cpu";
 114                         compatible = "qcom,kryo";
 115                         reg = <0x0 0x100>;
 116                         enable-method = "psci";
 117                         next-level-cache = <&L2_1>;
 118                         L2_1: l2-cache {
 119                               compatible = "cache";
 120                               cache-level = <2>;
 121                         };
 122                 };
 123
 124                 CPU3: cpu@101 {
 125                         device_type = "cpu";
 126                         compatible = "qcom,kryo";
 127                         reg = <0x0 0x101>;
 128                         enable-method = "psci";
 129                         next-level-cache = <&L2_1>;
 130                 };
 131
 132                 cpu-map {
 133                         cluster0 {
 134                                 core0 {
 135                                         cpu = <&CPU0>;
 136                                 };
 137
 138                                 core1 {
 139                                         cpu = <&CPU1>;
 140                                 };
 141                         };
 142
 143                         cluster1 {
 144                                 core0 {
 145                                         cpu = <&CPU2>;
 146                                 };
 147
 148                                 core1 {
 149                                         cpu = <&CPU3>;
 150                                 };
 151                         };
 152                 };
 153         };
 154
 155         thermal-zones {
 156                 cpu0-thermal {
 157                         polling-delay-passive = <250>;
 158                         polling-delay = <1000>;
 159
 160                         thermal-sensors = <&tsens0 3>;
 161
 162                         trips {
 163                                 cpu0_alert0: trip-point@0 {
 164                                         temperature = <75000>;
 165                                         hysteresis = <2000>;
 166                                         type = "passive";
 167                                 };
 168
 169                                 cpu0_crit: cpu_crit {
 170                                         temperature = <110000>;
 171                                         hysteresis = <2000>;
 172                                         type = "critical";
 173                                 };
 174                         };
 175                 };
 176
 177                 cpu1-thermal {
 178                         polling-delay-passive = <250>;
 179                         polling-delay = <1000>;
 180
 181                         thermal-sensors = <&tsens0 5>;
 182
 183                         trips {
 184                                 cpu1_alert0: trip-point@0 {
 185                                         temperature = <75000>;
 186                                         hysteresis = <2000>;
 187                                         type = "passive";
 188                                 };
 189
 190                                 cpu1_crit: cpu_crit {
 191                                         temperature = <110000>;
 192                                         hysteresis = <2000>;
 193                                         type = "critical";
 194                                 };
 195                         };
 196                 };
 197
 198                 cpu2-thermal {
 199                         polling-delay-passive = <250>;
 200                         polling-delay = <1000>;
 201
 202                         thermal-sensors = <&tsens0 8>;
 203
 204                         trips {
 205                                 cpu2_alert0: trip-point@0 {
 206                                         temperature = <75000>;
 207                                         hysteresis = <2000>;
 208                                         type = "passive";
 209                                 };
 210
 211                                 cpu2_crit: cpu_crit {
 212                                         temperature = <110000>;
 213                                         hysteresis = <2000>;
 214                                         type = "critical";
 215                                 };
 216                         };
 217                 };
 218
 219                 cpu3-thermal {
 220                         polling-delay-passive = <250>;
 221                         polling-delay = <1000>;
 222
 223                         thermal-sensors = <&tsens0 10>;
 224
 225                         trips {
 226                                 cpu3_alert0: trip-point@0 {
 227                                         temperature = <75000>;
 228                                         hysteresis = <2000>;
 229                                         type = "passive";
 230                                 };
 231
 232                                 cpu3_crit: cpu_crit {
 233                                         temperature = <110000>;
 234                                         hysteresis = <2000>;
 235                                         type = "critical";
 236                                 };
 237                         };
 238                 };
 239
 240                 gpu-thermal-top {
 241                         polling-delay-passive = <250>;
 242                         polling-delay = <1000>;
 243
 244                         thermal-sensors = <&tsens1 6>;
 245
 246                         trips {
 247                                 gpu1_alert0: trip-point@0 {
 248                                         temperature = <90000>;
 249                                         hysteresis = <2000>;
 250                                         type = "hot";
 251                                 };
 252                         };
 253                 };
 254
 255                 gpu-thermal-bottom {
 256                         polling-delay-passive = <250>;
 257                         polling-delay = <1000>;
 258
 259                         thermal-sensors = <&tsens1 7>;
 260
 261                         trips {
 262                                 gpu2_alert0: trip-point@0 {
 263                                         temperature = <90000>;
 264                                         hysteresis = <2000>;
 265                                         type = "hot";
 266                                 };
 267                         };
 268                 };
 269
 270                 m4m-thermal {
 271                         polling-delay-passive = <250>;
 272                         polling-delay = <1000>;
 273
 274                         thermal-sensors = <&tsens0 1>;
 275
 276                         trips {
 277                                 m4m_alert0: trip-point@0 {
 278                                         temperature = <90000>;
 279                                         hysteresis = <2000>;
 280                                         type = "hot";
 281                                 };
 282                         };
 283                 };
 284
 285                 l3-or-venus-thermal {
 286                         polling-delay-passive = <250>;
 287                         polling-delay = <1000>;
 288
 289                         thermal-sensors = <&tsens0 2>;
 290
 291                         trips {
 292                                 l3_or_venus_alert0: trip-point@0 {
 293                                         temperature = <90000>;
 294                                         hysteresis = <2000>;
 295                                         type = "hot";
 296                                 };
 297                         };
 298                 };
 299
 300                 cluster0-l2-thermal {
 301                         polling-delay-passive = <250>;
 302                         polling-delay = <1000>;
 303
 304                         thermal-sensors = <&tsens0 7>;
 305
 306                         trips {
 307                                 cluster0_l2_alert0: trip-point@0 {
 308                                         temperature = <90000>;
 309                                         hysteresis = <2000>;
 310                                         type = "hot";
 311                                 };
 312                         };
 313                 };
 314
 315                 cluster1-l2-thermal {
 316                         polling-delay-passive = <250>;
 317                         polling-delay = <1000>;
 318
 319                         thermal-sensors = <&tsens0 12>;
 320
 321                         trips {
 322                                 cluster1_l2_alert0: trip-point@0 {
 323                                         temperature = <90000>;
 324                                         hysteresis = <2000>;
 325                                         type = "hot";
 326                                 };
 327                         };
 328                 };
 329
 330                 camera-thermal {
 331                         polling-delay-passive = <250>;
 332                         polling-delay = <1000>;
 333
 334                         thermal-sensors = <&tsens1 1>;
 335
 336                         trips {
 337                                 camera_alert0: trip-point@0 {
 338                                         temperature = <90000>;
 339                                         hysteresis = <2000>;
 340                                         type = "hot";
 341                                 };
 342                         };
 343                 };
 344
 345                 q6-dsp-thermal {
 346                         polling-delay-passive = <250>;
 347                         polling-delay = <1000>;
 348
 349                         thermal-sensors = <&tsens1 2>;
 350
 351                         trips {
 352                                 q6_dsp_alert0: trip-point@0 {
 353                                         temperature = <90000>;
 354                                         hysteresis = <2000>;
 355                                         type = "hot";
 356                                 };
 357                         };
 358                 };
 359
 360                 mem-thermal {
 361                         polling-delay-passive = <250>;
 362                         polling-delay = <1000>;
 363
 364                         thermal-sensors = <&tsens1 3>;
 365
 366                         trips {
 367                                 mem_alert0: trip-point@0 {
 368                                         temperature = <90000>;
 369                                         hysteresis = <2000>;
 370                                         type = "hot";
 371                                 };
 372                         };
 373                 };
 374
 375                 modemtx-thermal {
 376                         polling-delay-passive = <250>;
 377                         polling-delay = <1000>;
 378
 379                         thermal-sensors = <&tsens1 4>;
 380
 381                         trips {
 382                                 modemtx_alert0: trip-point@0 {
 383                                         temperature = <90000>;
 384                                         hysteresis = <2000>;
 385                                         type = "hot";
 386                                 };
 387                         };
 388                 };
 389         };
 390
 391         timer {
 392                 compatible = "arm,armv8-timer";
 393                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 394                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 395                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 396                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 397         };
 398
 399         clocks {
 400                 xo_board: xo_board {
 401                         compatible = "fixed-clock";
 402                         #clock-cells = <0>;
 403                         clock-frequency = <19200000>;
 404                         clock-output-names = "xo_board";
 405                 };
 406
 407                 sleep_clk: sleep_clk {
 408                         compatible = "fixed-clock";
 409                         #clock-cells = <0>;
 410                         clock-frequency = <32764>;
 411                         clock-output-names = "sleep_clk";
 412                 };
 413         };
 414
 415         psci {
 416                 compatible = "arm,psci-1.0";
 417                 method = "smc";
 418         };
 419
 420         firmware {
 421                 scm {
 422                         compatible = "qcom,scm-msm8996";
 423
 424                         qcom,dload-mode = <&tcsr 0x13000>;
 425                 };
 426         };
 427
 428         tcsr_mutex: hwlock {
 429                 compatible = "qcom,tcsr-mutex";
 430                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 431                 #hwlock-cells = <1>;
 432         };
 433
 434         smem {
 435                 compatible = "qcom,smem";
 436                 memory-region = <&smem_mem>;
 437                 hwlocks = <&tcsr_mutex 3>;
 438         };
 439
 440         rpm-glink {
 441                 compatible = "qcom,glink-rpm";
 442
 443                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 444
 445                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 446
 447                 mboxes = <&apcs_glb 0>;
 448
 449                 rpm_requests {
 450                         compatible = "qcom,rpm-msm8996";
 451                         qcom,glink-channels = "rpm_requests";
 452
 453                         rpmcc: qcom,rpmcc {
 454                                 compatible = "qcom,rpmcc-msm8996";
 455                                 #clock-cells = <1>;
 456                         };
 457
 458                         rpmpd: power-controller {
 459                                 compatible = "qcom,msm8996-rpmpd";
 460                                 #power-domain-cells = <1>;
 461                                 operating-points-v2 = <&rpmpd_opp_table>;
 462
 463                                 rpmpd_opp_table: opp-table {
 464                                         compatible = "operating-points-v2";
 465
 466                                         rpmpd_opp1: opp1 {
 467                                                 opp-level = <1>;
 468                                         };
 469
 470                                         rpmpd_opp2: opp2 {
 471                                                 opp-level = <2>;
 472                                         };
 473
 474                                         rpmpd_opp3: opp3 {
 475                                                 opp-level = <3>;
 476                                         };
 477
 478                                         rpmpd_opp4: opp4 {
 479                                                 opp-level = <4>;
 480                                         };
 481
 482                                         rpmpd_opp5: opp5 {
 483                                                 opp-level = <5>;
 484                                         };
 485
 486                                         rpmpd_opp6: opp6 {
 487                                                 opp-level = <6>;
 488                                         };
 489                                 };
 490                         };
 491
 492                         pm8994-regulators {
 493                                 compatible = "qcom,rpm-pm8994-regulators";
 494
 495                                 pm8994_s1: s1 {};
 496                                 pm8994_s2: s2 {};
 497                                 pm8994_s3: s3 {};
 498                                 pm8994_s4: s4 {};
 499                                 pm8994_s5: s5 {};
 500                                 pm8994_s6: s6 {};
 501                                 pm8994_s7: s7 {};
 502                                 pm8994_s8: s8 {};
 503                                 pm8994_s9: s9 {};
 504                                 pm8994_s10: s10 {};
 505                                 pm8994_s11: s11 {};
 506                                 pm8994_s12: s12 {};
 507
 508                                 pm8994_l1: l1 {};
 509                                 pm8994_l2: l2 {};
 510                                 pm8994_l3: l3 {};
 511                                 pm8994_l4: l4 {};
 512                                 pm8994_l5: l5 {};
 513                                 pm8994_l6: l6 {};
 514                                 pm8994_l7: l7 {};
 515                                 pm8994_l8: l8 {};
 516                                 pm8994_l9: l9 {};
 517                                 pm8994_l10: l10 {};
 518                                 pm8994_l11: l11 {};
 519                                 pm8994_l12: l12 {};
 520                                 pm8994_l13: l13 {};
 521                                 pm8994_l14: l14 {};
 522                                 pm8994_l15: l15 {};
 523                                 pm8994_l16: l16 {};
 524                                 pm8994_l17: l17 {};
 525                                 pm8994_l18: l18 {};
 526                                 pm8994_l19: l19 {};
 527                                 pm8994_l20: l20 {};
 528                                 pm8994_l21: l21 {};
 529                                 pm8994_l22: l22 {};
 530                                 pm8994_l23: l23 {};
 531                                 pm8994_l24: l24 {};
 532                                 pm8994_l25: l25 {};
 533                                 pm8994_l26: l26 {};
 534                                 pm8994_l27: l27 {};
 535                                 pm8994_l28: l28 {};
 536                                 pm8994_l29: l29 {};
 537                                 pm8994_l30: l30 {};
 538                                 pm8994_l31: l31 {};
 539                                 pm8994_l32: l32 {};
 540                         };
 541
 542                 };
 543         };
 544
 545         soc: soc {
 546                 #address-cells = <1>;
 547                 #size-cells = <1>;
 548                 ranges = <0 0 0 0xffffffff>;
 549                 compatible = "simple-bus";
 550
 551                 rpm_msg_ram: memory@68000 {
 552                         compatible = "qcom,rpm-msg-ram";
 553                         reg = <0x68000 0x6000>;
 554                 };
 555
 556                 rng: rng@83000 {
 557                         compatible = "qcom,prng-ee";
 558                         reg = <0x00083000 0x1000>;
 559                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 560                         clock-names = "core";
 561                 };
 562
 563                 tcsr_mutex_regs: syscon@740000 {
 564                         compatible = "syscon";
 565                         reg = <0x740000 0x20000>;
 566                 };
 567
 568                 tsens0: thermal-sensor@4a9000 {
 569                         compatible = "qcom,msm8996-tsens";
 570                         reg = <0x4a9000 0x1000>, /* TM */
 571                               <0x4a8000 0x1000>; /* SROT */
 572                         #qcom,sensors = <13>;
 573                         #thermal-sensor-cells = <1>;
 574                 };
 575
 576                 tsens1: thermal-sensor@4ad000 {
 577                         compatible = "qcom,msm8996-tsens";
 578                         reg = <0x4ad000 0x1000>, /* TM */
 579                               <0x4ac000 0x1000>; /* SROT */
 580                         #qcom,sensors = <8>;
 581                         #thermal-sensor-cells = <1>;
 582                 };
 583
 584                 tcsr: syscon@7a0000 {
 585                         compatible = "qcom,tcsr-msm8996", "syscon";
 586                         reg = <0x7a0000 0x18000>;
 587                 };
 588
 589                 intc: interrupt-controller@9bc0000 {
 590                         compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
 591                         #interrupt-cells = <3>;
 592                         interrupt-controller;
 593                         #redistributor-regions = <1>;
 594                         redistributor-stride = <0x0 0x40000>;
 595                         reg = <0x09bc0000 0x10000>,
 596                               <0x09c00000 0x100000>;
 597                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 598                 };
 599
 600                 apcs_glb: mailbox@9820000 {
 601                         compatible = "qcom,msm8996-apcs-hmss-global";
 602                         reg = <0x9820000 0x1000>;
 603
 604                         #mbox-cells = <1>;
 605                 };
 606
 607                 gcc: clock-controller@300000 {
 608                         compatible = "qcom,gcc-msm8996";
 609                         #clock-cells = <1>;
 610                         #reset-cells = <1>;
 611                         #power-domain-cells = <1>;
 612                         reg = <0x300000 0x90000>;
 613                 };
 614
 615                 kryocc: clock-controller@6400000 {
 616                         compatible = "qcom,apcc-msm8996";
 617                         reg = <0x6400000 0x90000>;
 618                         #clock-cells = <1>;
 619                 };
 620
 621                 blsp1_uart1: serial@7570000 {
 622                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 623                         reg = <0x07570000 0x1000>;
 624                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 625                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 626                                  <&gcc GCC_BLSP1_AHB_CLK>;
 627                         clock-names = "core", "iface";
 628                         status = "disabled";
 629                 };
 630
 631                 blsp1_spi0: spi@7575000 {
 632                         compatible = "qcom,spi-qup-v2.2.1";
 633                         reg = <0x07575000 0x600>;
 634                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 635                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 636                                  <&gcc GCC_BLSP1_AHB_CLK>;
 637                         clock-names = "core", "iface";
 638                         pinctrl-names = "default", "sleep";
 639                         pinctrl-0 = <&blsp1_spi0_default>;
 640                         pinctrl-1 = <&blsp1_spi0_sleep>;
 641                         #address-cells = <1>;
 642                         #size-cells = <0>;
 643                         status = "disabled";
 644                 };
 645
 646                 blsp2_i2c0: i2c@75b5000 {
 647                         compatible = "qcom,i2c-qup-v2.2.1";
 648                         reg = <0x075b5000 0x1000>;
 649                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 650                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 651                                 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
 652                         clock-names = "iface", "core";
 653                         pinctrl-names = "default", "sleep";
 654                         pinctrl-0 = <&blsp2_i2c0_default>;
 655                         pinctrl-1 = <&blsp2_i2c0_sleep>;
 656                         #address-cells = <1>;
 657                         #size-cells = <0>;
 658                         status = "disabled";
 659                 };
 660
 661                 blsp2_uart1: serial@75b0000 {
 662                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 663                         reg = <0x75b0000 0x1000>;
 664                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 665                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 666                                  <&gcc GCC_BLSP2_AHB_CLK>;
 667                         clock-names = "core", "iface";
 668                         status = "disabled";
 669                 };
 670
 671                 blsp2_i2c1: i2c@75b6000 {
 672                         compatible = "qcom,i2c-qup-v2.2.1";
 673                         reg = <0x075b6000 0x1000>;
 674                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 675                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 676                                 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
 677                         clock-names = "iface", "core";
 678                         pinctrl-names = "default", "sleep";
 679                         pinctrl-0 = <&blsp2_i2c1_default>;
 680                         pinctrl-1 = <&blsp2_i2c1_sleep>;
 681                         #address-cells = <1>;
 682                         #size-cells = <0>;
 683                         status = "disabled";
 684                 };
 685
 686                 blsp2_uart2: serial@75b1000 {
 687                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 688                         reg = <0x075b1000 0x1000>;
 689                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 690                         clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
 691                                  <&gcc GCC_BLSP2_AHB_CLK>;
 692                         clock-names = "core", "iface";
 693                         status = "disabled";
 694                 };
 695
 696                 blsp1_i2c2: i2c@7577000 {
 697                         compatible = "qcom,i2c-qup-v2.2.1";
 698                         reg = <0x07577000 0x1000>;
 699                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 700                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 701                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 702                         clock-names = "iface", "core";
 703                         pinctrl-names = "default", "sleep";
 704                         pinctrl-0 = <&blsp1_i2c2_default>;
 705                         pinctrl-1 = <&blsp1_i2c2_sleep>;
 706                         #address-cells = <1>;
 707                         #size-cells = <0>;
 708                         status = "disabled";
 709                 };
 710
 711                 blsp2_spi5: spi@75ba000{
 712                         compatible = "qcom,spi-qup-v2.2.1";
 713                         reg = <0x075ba000 0x600>;
 714                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 715                         clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
 716                                  <&gcc GCC_BLSP2_AHB_CLK>;
 717                         clock-names = "core", "iface";
 718                         pinctrl-names = "default", "sleep";
 719                         pinctrl-0 = <&blsp2_spi5_default>;
 720                         pinctrl-1 = <&blsp2_spi5_sleep>;
 721                         #address-cells = <1>;
 722                         #size-cells = <0>;
 723                         status = "disabled";
 724                 };
 725
 726                 sdhc2: sdhci@74a4900 {
 727                          status = "disabled";
 728                          compatible = "qcom,sdhci-msm-v4";
 729                          reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
 730                          reg-names = "hc_mem", "core_mem";
 731
 732                          interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
 733                                       <0 221 IRQ_TYPE_LEVEL_HIGH>;
 734                          interrupt-names = "hc_irq", "pwr_irq";
 735
 736                          clock-names = "iface", "core", "xo";
 737                          clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 738                          <&gcc GCC_SDCC2_APPS_CLK>,
 739                          <&xo_board>;
 740                          bus-width = <4>;
 741                  };
 742
 743                 msmgpio: pinctrl@1010000 {
 744                         compatible = "qcom,msm8996-pinctrl";
 745                         reg = <0x01010000 0x300000>;
 746                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 747                         gpio-controller;
 748                         #gpio-cells = <2>;
 749                         interrupt-controller;
 750                         #interrupt-cells = <2>;
 751                 };
 752
 753                 timer@9840000 {
 754                         #address-cells = <1>;
 755                         #size-cells = <1>;
 756                         ranges;
 757                         compatible = "arm,armv7-timer-mem";
 758                         reg = <0x09840000 0x1000>;
 759                         clock-frequency = <19200000>;
 760
 761                         frame@9850000 {
 762                                 frame-number = <0>;
 763                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 764                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 765                                 reg = <0x09850000 0x1000>,
 766                                       <0x09860000 0x1000>;
 767                         };
 768
 769                         frame@9870000 {
 770                                 frame-number = <1>;
 771                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 772                                 reg = <0x09870000 0x1000>;
 773                                 status = "disabled";
 774                         };
 775
 776                         frame@9880000 {
 777                                 frame-number = <2>;
 778                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 779                                 reg = <0x09880000 0x1000>;
 780                                 status = "disabled";
 781                         };
 782
 783                         frame@9890000 {
 784                                 frame-number = <3>;
 785                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 786                                 reg = <0x09890000 0x1000>;
 787                                 status = "disabled";
 788                         };
 789
 790                         frame@98a0000 {
 791                                 frame-number = <4>;
 792                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 793                                 reg = <0x098a0000 0x1000>;
 794                                 status = "disabled";
 795                         };
 796
 797                         frame@98b0000 {
 798                                 frame-number = <5>;
 799                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 800                                 reg = <0x098b0000 0x1000>;
 801                                 status = "disabled";
 802                         };
 803
 804                         frame@98c0000 {
 805                                 frame-number = <6>;
 806                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 807                                 reg = <0x098c0000 0x1000>;
 808                                 status = "disabled";
 809                         };
 810                 };
 811
 812                 spmi_bus: qcom,spmi@400f000 {
 813                         compatible = "qcom,spmi-pmic-arb";
 814                         reg = <0x400f000 0x1000>,
 815                               <0x4400000 0x800000>,
 816                               <0x4c00000 0x800000>,
 817                               <0x5800000 0x200000>,
 818                               <0x400a000 0x002100>;
 819                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 820                         interrupt-names = "periph_irq";
 821                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
 822                         qcom,ee = <0>;
 823                         qcom,channel = <0>;
 824                         #address-cells = <2>;
 825                         #size-cells = <0>;
 826                         interrupt-controller;
 827                         #interrupt-cells = <4>;
 828                 };
 829
 830                 ufsphy: phy@627000 {
 831                         compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
 832                         reg = <0x627000 0xda8>;
 833                         reg-names = "phy_mem";
 834                         #phy-cells = <0>;
 835
 836                         vdda-phy-supply = <&pm8994_l28>;
 837                         vdda-pll-supply = <&pm8994_l12>;
 838
 839                         vdda-phy-max-microamp = <18380>;
 840                         vdda-pll-max-microamp = <9440>;
 841
 842                         vddp-ref-clk-supply = <&pm8994_l25>;
 843                         vddp-ref-clk-max-microamp = <100>;
 844                         vddp-ref-clk-always-on;
 845
 846                         clock-names = "ref_clk_src", "ref_clk";
 847                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
 848                                  <&gcc GCC_UFS_CLKREF_CLK>;
 849                         status = "disabled";
 850                 };
 851
 852                 ufshc@624000 {
 853                         compatible = "qcom,ufshc";
 854                         reg = <0x624000 0x2500>;
 855                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 856
 857                         phys = <&ufsphy>;
 858                         phy-names = "ufsphy";
 859
 860                         vcc-supply = <&pm8994_l20>;
 861                         vccq-supply = <&pm8994_l25>;
 862                         vccq2-supply = <&pm8994_s4>;
 863
 864                         vcc-max-microamp = <600000>;
 865                         vccq-max-microamp = <450000>;
 866                         vccq2-max-microamp = <450000>;
 867
 868                         power-domains = <&gcc UFS_GDSC>;
 869
 870                         clock-names =
 871                                 "core_clk_src",
 872                                 "core_clk",
 873                                 "bus_clk",
 874                                 "bus_aggr_clk",
 875                                 "iface_clk",
 876                                 "core_clk_unipro_src",
 877                                 "core_clk_unipro",
 878                                 "core_clk_ice",
 879                                 "ref_clk",
 880                                 "tx_lane0_sync_clk",
 881                                 "rx_lane0_sync_clk";
 882                         clocks =
 883                                 <&gcc UFS_AXI_CLK_SRC>,
 884                                 <&gcc GCC_UFS_AXI_CLK>,
 885                                 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
 886                                 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
 887                                 <&gcc GCC_UFS_AHB_CLK>,
 888                                 <&gcc UFS_ICE_CORE_CLK_SRC>,
 889                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
 890                                 <&gcc GCC_UFS_ICE_CORE_CLK>,
 891                                 <&rpmcc RPM_SMD_LN_BB_CLK>,
 892                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
 893                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
 894                         freq-table-hz =
 895                                 <100000000 200000000>,
 896                                 <0 0>,
 897                                 <0 0>,
 898                                 <0 0>,
 899                                 <0 0>,
 900                                 <150000000 300000000>,
 901                                 <0 0>,
 902                                 <0 0>,
 903                                 <0 0>,
 904                                 <0 0>,
 905                                 <0 0>;
 906
 907                         lanes-per-direction = <1>;
 908                         status = "disabled";
 909
 910                         ufs_variant {
 911                                 compatible = "qcom,ufs_variant";
 912                         };
 913                 };
 914
 915                 mmcc: clock-controller@8c0000 {
 916                         compatible = "qcom,mmcc-msm8996";
 917                         #clock-cells = <1>;
 918                         #reset-cells = <1>;
 919                         #power-domain-cells = <1>;
 920                         reg = <0x8c0000 0x40000>;
 921                         assigned-clocks = <&mmcc MMPLL9_PLL>,
 922                                           <&mmcc MMPLL1_PLL>,
 923                                           <&mmcc MMPLL3_PLL>,
 924                                           <&mmcc MMPLL4_PLL>,
 925                                           <&mmcc MMPLL5_PLL>;
 926                         assigned-clock-rates = <624000000>,
 927                                                <810000000>,
 928                                                <980000000>,
 929                                                <960000000>,
 930                                                <825000000>;
 931                 };
 932
 933                 qfprom@74000 {
 934                         compatible = "qcom,qfprom";
 935                         reg = <0x74000 0x8ff>;
 936                         #address-cells = <1>;
 937                         #size-cells = <1>;
 938
 939                         qusb2p_hstx_trim: hstx_trim@24e {
 940                                 reg = <0x24e 0x2>;
 941                                 bits = <5 4>;
 942                         };
 943
 944                         qusb2s_hstx_trim: hstx_trim@24f {
 945                                 reg = <0x24f 0x1>;
 946                                 bits = <1 4>;
 947                         };
 948
 949                         gpu_speed_bin: gpu_speed_bin@133 {
 950                                 reg = <0x133 0x1>;
 951                                 bits = <5 3>;
 952                         };
 953                 };
 954
 955                 phy@34000 {
 956                         compatible = "qcom,msm8996-qmp-pcie-phy";
 957                         reg = <0x34000 0x488>;
 958                         #clock-cells = <1>;
 959                         #address-cells = <1>;
 960                         #size-cells = <1>;
 961                         ranges;
 962
 963                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 964                                 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
 965                                 <&gcc GCC_PCIE_CLKREF_CLK>;
 966                         clock-names = "aux", "cfg_ahb", "ref";
 967
 968                         vdda-phy-supply = <&pm8994_l28>;
 969                         vdda-pll-supply = <&pm8994_l12>;
 970
 971                         resets = <&gcc GCC_PCIE_PHY_BCR>,
 972                                 <&gcc GCC_PCIE_PHY_COM_BCR>,
 973                                 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
 974                         reset-names = "phy", "common", "cfg";
 975                         status = "disabled";
 976
 977                         pciephy_0: lane@35000 {
 978                                 reg = <0x035000 0x130>,
 979                                         <0x035200 0x200>,
 980                                         <0x035400 0x1dc>;
 981                                 #phy-cells = <0>;
 982
 983                                 clock-output-names = "pcie_0_pipe_clk_src";
 984                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 985                                 clock-names = "pipe0";
 986                                 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
 987                                 reset-names = "lane0";
 988                         };
 989
 990                         pciephy_1: lane@36000 {
 991                                 reg = <0x036000 0x130>,
 992                                         <0x036200 0x200>,
 993                                         <0x036400 0x1dc>;
 994                                 #phy-cells = <0>;
 995
 996                                 clock-output-names = "pcie_1_pipe_clk_src";
 997                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
 998                                 clock-names = "pipe1";
 999                                 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1000                                 reset-names = "lane1";
1001                         };
1002
1003                         pciephy_2: lane@37000 {
1004                                 reg = <0x037000 0x130>,
1005                                         <0x037200 0x200>,
1006                                         <0x037400 0x1dc>;
1007                                 #phy-cells = <0>;
1008
1009                                 clock-output-names = "pcie_2_pipe_clk_src";
1010                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
1011                                 clock-names = "pipe2";
1012                                 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
1013                                 reset-names = "lane2";
1014                         };
1015                 };
1016
1017                 phy@7410000 {
1018                         compatible = "qcom,msm8996-qmp-usb3-phy";
1019                         reg = <0x7410000 0x1c4>;
1020                         #clock-cells = <1>;
1021                         #address-cells = <1>;
1022                         #size-cells = <1>;
1023                         ranges;
1024
1025                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1026                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1027                                 <&gcc GCC_USB3_CLKREF_CLK>;
1028                         clock-names = "aux", "cfg_ahb", "ref";
1029
1030                         vdda-phy-supply = <&pm8994_l28>;
1031                         vdda-pll-supply = <&pm8994_l12>;
1032
1033                         resets = <&gcc GCC_USB3_PHY_BCR>,
1034                                 <&gcc GCC_USB3PHY_PHY_BCR>;
1035                         reset-names = "phy", "common";
1036                         status = "disabled";
1037
1038                         ssusb_phy_0: lane@7410200 {
1039                                 reg = <0x7410200 0x200>,
1040                                         <0x7410400 0x130>,
1041                                         <0x7410600 0x1a8>;
1042                                 #phy-cells = <0>;
1043
1044                                 clock-output-names = "usb3_phy_pipe_clk_src";
1045                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
1046                                 clock-names = "pipe0";
1047                         };
1048                 };
1049
1050                 hsusb_phy1: phy@7411000 {
1051                         compatible = "qcom,msm8996-qusb2-phy";
1052                         reg = <0x7411000 0x180>;
1053                         #phy-cells = <0>;
1054
1055                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1056                                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1057                         clock-names = "cfg_ahb", "ref";
1058
1059                         vdda-pll-supply = <&pm8994_l12>;
1060                         vdda-phy-dpdm-supply = <&pm8994_l24>;
1061
1062                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1063                         nvmem-cells = <&qusb2p_hstx_trim>;
1064                         status = "disabled";
1065                 };
1066
1067                 hsusb_phy2: phy@7412000 {
1068                         compatible = "qcom,msm8996-qusb2-phy";
1069                         reg = <0x7412000 0x180>;
1070                         #phy-cells = <0>;
1071
1072                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1073                                 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
1074                         clock-names = "cfg_ahb", "ref";
1075
1076                         vdda-pll-supply = <&pm8994_l12>;
1077                         vdda-phy-dpdm-supply = <&pm8994_l24>;
1078
1079                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1080                         nvmem-cells = <&qusb2s_hstx_trim>;
1081                         status = "disabled";
1082                 };
1083
1084                 usb2: usb@76f8800 {
1085                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1086                         reg = <0x76f8800 0x400>;
1087                         #address-cells = <1>;
1088                         #size-cells = <1>;
1089                         ranges;
1090
1091                         clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
1092                                 <&gcc GCC_USB20_MASTER_CLK>,
1093                                 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1094                                 <&gcc GCC_USB20_SLEEP_CLK>,
1095                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1096
1097                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1098                                           <&gcc GCC_USB20_MASTER_CLK>;
1099                         assigned-clock-rates = <19200000>, <60000000>;
1100
1101                         power-domains = <&gcc USB30_GDSC>;
1102                         status = "disabled";
1103
1104                         dwc3@7600000 {
1105                                 compatible = "snps,dwc3";
1106                                 reg = <0x7600000 0xcc00>;
1107                                 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
1108                                 phys = <&hsusb_phy2>;
1109                                 phy-names = "usb2-phy";
1110                         };
1111                 };
1112
1113                 usb3: usb@6af8800 {
1114                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1115                         reg = <0x6af8800 0x400>;
1116                         #address-cells = <1>;
1117                         #size-cells = <1>;
1118                         ranges;
1119
1120                         clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
1121                                 <&gcc GCC_USB30_MASTER_CLK>,
1122                                 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1123                                 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1124                                 <&gcc GCC_USB30_SLEEP_CLK>,
1125                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1126
1127                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1128                                           <&gcc GCC_USB30_MASTER_CLK>;
1129                         assigned-clock-rates = <19200000>, <120000000>;
1130
1131                         power-domains = <&gcc USB30_GDSC>;
1132                         status = "disabled";
1133
1134                         dwc3@6a00000 {
1135                                 compatible = "snps,dwc3";
1136                                 reg = <0x6a00000 0xcc00>;
1137                                 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
1138                                 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
1139                                 phy-names = "usb2-phy", "usb3-phy";
1140                         };
1141                 };
1142
1143                 vfe_smmu: arm,smmu@da0000 {
1144                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1145                         reg = <0xda0000 0x10000>;
1146
1147                         #global-interrupts = <1>;
1148                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1149                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1150                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1151                         power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
1152                         clocks = <&mmcc SMMU_VFE_AHB_CLK>,
1153                                  <&mmcc SMMU_VFE_AXI_CLK>;
1154                         clock-names = "iface",
1155                                       "bus";
1156                         #iommu-cells = <1>;
1157                         status = "disabled";
1158                 };
1159
1160                 camss: camss@a00000 {
1161                         compatible = "qcom,msm8996-camss";
1162                         reg = <0xa34000 0x1000>,
1163                                 <0xa00030 0x4>,
1164                                 <0xa35000 0x1000>,
1165                                 <0xa00038 0x4>,
1166                                 <0xa36000 0x1000>,
1167                                 <0xa00040 0x4>,
1168                                 <0xa30000 0x100>,
1169                                 <0xa30400 0x100>,
1170                                 <0xa30800 0x100>,
1171                                 <0xa30c00 0x100>,
1172                                 <0xa31000 0x500>,
1173                                 <0xa00020 0x10>,
1174                                 <0xa10000 0x1000>,
1175                                 <0xa14000 0x1000>;
1176                         reg-names = "csiphy0",
1177                                 "csiphy0_clk_mux",
1178                                 "csiphy1",
1179                                 "csiphy1_clk_mux",
1180                                 "csiphy2",
1181                                 "csiphy2_clk_mux",
1182                                 "csid0",
1183                                 "csid1",
1184                                 "csid2",
1185                                 "csid3",
1186                                 "ispif",
1187                                 "csi_clk_mux",
1188                                 "vfe0",
1189                                 "vfe1";
1190                         interrupts = <GIC_SPI 78 0>,
1191                                 <GIC_SPI 79 0>,
1192                                 <GIC_SPI 80 0>,
1193                                 <GIC_SPI 296 0>,
1194                                 <GIC_SPI 297 0>,
1195                                 <GIC_SPI 298 0>,
1196                                 <GIC_SPI 299 0>,
1197                                 <GIC_SPI 309 0>,
1198                                 <GIC_SPI 314 0>,
1199                                 <GIC_SPI 315 0>;
1200                         interrupt-names = "csiphy0",
1201                                 "csiphy1",
1202                                 "csiphy2",
1203                                 "csid0",
1204                                 "csid1",
1205                                 "csid2",
1206                                 "csid3",
1207                                 "ispif",
1208                                 "vfe0",
1209                                 "vfe1";
1210                         power-domains = <&mmcc VFE0_GDSC>;
1211                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1212                                 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1213                                 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1214                                 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1215                                 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1216                                 <&mmcc CAMSS_CSI0_AHB_CLK>,
1217                                 <&mmcc CAMSS_CSI0_CLK>,
1218                                 <&mmcc CAMSS_CSI0PHY_CLK>,
1219                                 <&mmcc CAMSS_CSI0PIX_CLK>,
1220                                 <&mmcc CAMSS_CSI0RDI_CLK>,
1221                                 <&mmcc CAMSS_CSI1_AHB_CLK>,
1222                                 <&mmcc CAMSS_CSI1_CLK>,
1223                                 <&mmcc CAMSS_CSI1PHY_CLK>,
1224                                 <&mmcc CAMSS_CSI1PIX_CLK>,
1225                                 <&mmcc CAMSS_CSI1RDI_CLK>,
1226                                 <&mmcc CAMSS_CSI2_AHB_CLK>,
1227                                 <&mmcc CAMSS_CSI2_CLK>,
1228                                 <&mmcc CAMSS_CSI2PHY_CLK>,
1229                                 <&mmcc CAMSS_CSI2PIX_CLK>,
1230                                 <&mmcc CAMSS_CSI2RDI_CLK>,
1231                                 <&mmcc CAMSS_CSI3_AHB_CLK>,
1232                                 <&mmcc CAMSS_CSI3_CLK>,
1233                                 <&mmcc CAMSS_CSI3PHY_CLK>,
1234                                 <&mmcc CAMSS_CSI3PIX_CLK>,
1235                                 <&mmcc CAMSS_CSI3RDI_CLK>,
1236                                 <&mmcc CAMSS_AHB_CLK>,
1237                                 <&mmcc CAMSS_VFE0_CLK>,
1238                                 <&mmcc CAMSS_CSI_VFE0_CLK>,
1239                                 <&mmcc CAMSS_VFE0_AHB_CLK>,
1240                                 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1241                                 <&mmcc CAMSS_VFE1_CLK>,
1242                                 <&mmcc CAMSS_CSI_VFE1_CLK>,
1243                                 <&mmcc CAMSS_VFE1_AHB_CLK>,
1244                                 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1245                                 <&mmcc CAMSS_VFE_AHB_CLK>,
1246                                 <&mmcc CAMSS_VFE_AXI_CLK>;
1247                         clock-names = "top_ahb",
1248                                 "ispif_ahb",
1249                                 "csiphy0_timer",
1250                                 "csiphy1_timer",
1251                                 "csiphy2_timer",
1252                                 "csi0_ahb",
1253                                 "csi0",
1254                                 "csi0_phy",
1255                                 "csi0_pix",
1256                                 "csi0_rdi",
1257                                 "csi1_ahb",
1258                                 "csi1",
1259                                 "csi1_phy",
1260                                 "csi1_pix",
1261                                 "csi1_rdi",
1262                                 "csi2_ahb",
1263                                 "csi2",
1264                                 "csi2_phy",
1265                                 "csi2_pix",
1266                                 "csi2_rdi",
1267                                 "csi3_ahb",
1268                                 "csi3",
1269                                 "csi3_phy",
1270                                 "csi3_pix",
1271                                 "csi3_rdi",
1272                                 "ahb",
1273                                 "vfe0",
1274                                 "csi_vfe0",
1275                                 "vfe0_ahb",
1276                                 "vfe0_stream",
1277                                 "vfe1",
1278                                 "csi_vfe1",
1279                                 "vfe1_ahb",
1280                                 "vfe1_stream",
1281                                 "vfe_ahb",
1282                                 "vfe_axi";
1283                         vdda-supply = <&pm8994_l2>;
1284                         iommus = <&vfe_smmu 0>,
1285                                  <&vfe_smmu 1>,
1286                                  <&vfe_smmu 2>,
1287                                  <&vfe_smmu 3>;
1288                         status = "disabled";
1289                         ports {
1290                                 #address-cells = <1>;
1291                                 #size-cells = <0>;
1292                         };
1293                 };
1294
1295                 adreno_smmu: arm,smmu@b40000 {
1296                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1297                         reg = <0xb40000 0x10000>;
1298
1299                         #global-interrupts = <1>;
1300                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1301                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1302                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1303                         #iommu-cells = <1>;
1304
1305                         clocks = <&mmcc GPU_AHB_CLK>,
1306                                  <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1307                         clock-names = "iface", "bus";
1308
1309                         power-domains = <&mmcc GPU_GDSC>;
1310
1311                         status = "disabled";
1312                 };
1313
1314                 mdp_smmu: arm,smmu@d00000 {
1315                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1316                         reg = <0xd00000 0x10000>;
1317
1318                         #global-interrupts = <1>;
1319                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1320                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1321                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1322                         #iommu-cells = <1>;
1323                         clocks = <&mmcc SMMU_MDP_AHB_CLK>,
1324                                  <&mmcc SMMU_MDP_AXI_CLK>;
1325                         clock-names = "iface", "bus";
1326
1327                         power-domains = <&mmcc MDSS_GDSC>;
1328
1329                         status = "disabled";
1330                 };
1331
1332                 lpass_q6_smmu: arm,smmu-lpass_q6@1600000 {
1333                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1334                         reg = <0x1600000 0x20000>;
1335                         #iommu-cells = <1>;
1336                         power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
1337
1338                         #global-interrupts = <1>;
1339                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1340                                 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1341                                 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1342                                 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1343                                 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1344                                 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1345                                 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1346                                 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1347                                 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1348                                 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1349                                 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1350                                 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1351                                 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
1352
1353                         clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
1354                                  <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
1355                         clock-names = "iface", "bus";
1356                         status = "disabled";
1357                 };
1358
1359                 agnoc@0 {
1360                         power-domains = <&gcc AGGRE0_NOC_GDSC>;
1361                         compatible = "simple-pm-bus";
1362                         #address-cells = <1>;
1363                         #size-cells = <1>;
1364                         ranges;
1365
1366                         pcie0: pcie@600000 {
1367                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1368                                 status = "disabled";
1369                                 power-domains = <&gcc PCIE0_GDSC>;
1370                                 bus-range = <0x00 0xff>;
1371                                 num-lanes = <1>;
1372
1373                                 reg = <0x00600000 0x2000>,
1374                                       <0x0c000000 0xf1d>,
1375                                       <0x0c000f20 0xa8>,
1376                                       <0x0c100000 0x100000>;
1377                                 reg-names = "parf", "dbi", "elbi","config";
1378
1379                                 phys = <&pciephy_0>;
1380                                 phy-names = "pciephy";
1381
1382                                 #address-cells = <3>;
1383                                 #size-cells = <2>;
1384                                 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1385                                         <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1386
1387                                 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1388                                 interrupt-names = "msi";
1389                                 #interrupt-cells = <1>;
1390                                 interrupt-map-mask = <0 0 0 0x7>;
1391                                 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1392                                                 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1393                                                 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1394                                                 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1395
1396                                 pinctrl-names = "default", "sleep";
1397                                 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
1398                                 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
1399
1400
1401                                 vdda-supply = <&pm8994_l28>;
1402
1403                                 linux,pci-domain = <0>;
1404
1405                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1406                                         <&gcc GCC_PCIE_0_AUX_CLK>,
1407                                         <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1408                                         <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1409                                         <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1410
1411                                 clock-names =  "pipe",
1412                                                 "aux",
1413                                                 "cfg",
1414                                                 "bus_master",
1415                                                 "bus_slave";
1416
1417                         };
1418
1419                         pcie1: pcie@608000 {
1420                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1421                                 power-domains = <&gcc PCIE1_GDSC>;
1422                                 bus-range = <0x00 0xff>;
1423                                 num-lanes = <1>;
1424
1425                                 status  = "disabled";
1426
1427                                 reg = <0x00608000 0x2000>,
1428                                       <0x0d000000 0xf1d>,
1429                                       <0x0d000f20 0xa8>,
1430                                       <0x0d100000 0x100000>;
1431
1432                                 reg-names = "parf", "dbi", "elbi","config";
1433
1434                                 phys = <&pciephy_1>;
1435                                 phy-names = "pciephy";
1436
1437                                 #address-cells = <3>;
1438                                 #size-cells = <2>;
1439                                 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1440                                         <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1441
1442                                 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1443                                 interrupt-names = "msi";
1444                                 #interrupt-cells = <1>;
1445                                 interrupt-map-mask = <0 0 0 0x7>;
1446                                 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1447                                                 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1448                                                 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1449                                                 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1450
1451                                 pinctrl-names = "default", "sleep";
1452                                 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
1453                                 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
1454
1455
1456                                 vdda-supply = <&pm8994_l28>;
1457                                 linux,pci-domain = <1>;
1458
1459                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1460                                         <&gcc GCC_PCIE_1_AUX_CLK>,
1461                                         <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1462                                         <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1463                                         <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1464
1465                                 clock-names =  "pipe",
1466                                                 "aux",
1467                                                 "cfg",
1468                                                 "bus_master",
1469                                                 "bus_slave";
1470                         };
1471
1472                         pcie2: pcie@610000 {
1473                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1474                                 power-domains = <&gcc PCIE2_GDSC>;
1475                                 bus-range = <0x00 0xff>;
1476                                 num-lanes = <1>;
1477                                 status = "disabled";
1478                                 reg = <0x00610000 0x2000>,
1479                                       <0x0e000000 0xf1d>,
1480                                       <0x0e000f20 0xa8>,
1481                                       <0x0e100000 0x100000>;
1482
1483                                 reg-names = "parf", "dbi", "elbi","config";
1484
1485                                 phys = <&pciephy_2>;
1486                                 phy-names = "pciephy";
1487
1488                                 #address-cells = <3>;
1489                                 #size-cells = <2>;
1490                                 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1491                                         <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1492
1493                                 device_type = "pci";
1494
1495                                 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1496                                 interrupt-names = "msi";
1497                                 #interrupt-cells = <1>;
1498                                 interrupt-map-mask = <0 0 0 0x7>;
1499                                 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1500                                                 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1501                                                 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1502                                                 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1503
1504                                 pinctrl-names = "default", "sleep";
1505                                 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
1506                                 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
1507
1508                                 vdda-supply = <&pm8994_l28>;
1509
1510                                 linux,pci-domain = <2>;
1511                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1512                                         <&gcc GCC_PCIE_2_AUX_CLK>,
1513                                         <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1514                                         <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1515                                         <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1516
1517                                 clock-names =  "pipe",
1518                                                 "aux",
1519                                                 "cfg",
1520                                                 "bus_master",
1521                                                 "bus_slave";
1522                         };
1523                 };
1524
1525                 slimbam:dma@9184000
1526                 {
1527                         compatible = "qcom,bam-v1.7.0";
1528                         qcom,controlled-remotely;
1529                         reg = <0x9184000 0x32000>;
1530                         num-channels  = <31>;
1531                         interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
1532                         #dma-cells = <1>;
1533                         qcom,ee = <1>;
1534                         qcom,num-ees = <2>;
1535                 };
1536
1537                 slim_msm: slim@91c0000 {
1538                         compatible = "qcom,slim-ngd-v1.5.0";
1539                         reg = <0x91c0000 0x2C000>;
1540                         reg-names = "ctrl";
1541                         interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
1542                         dmas =  <&slimbam 3>, <&slimbam 4>,
1543                                 <&slimbam 5>, <&slimbam 6>;
1544                         dma-names = "rx", "tx", "tx2", "rx2";
1545                         #address-cells = <1>;
1546                         #size-cells = <0>;
1547                         ngd@1 {
1548                                 reg = <1>;
1549                                 #address-cells = <1>;
1550                                 #size-cells = <1>;
1551
1552                                 tasha_ifd: tas-ifd {
1553                                         compatible = "slim217,1a0";
1554                                         reg  = <0 0>;
1555                                 };
1556
1557                                 wcd9335: codec@1{
1558                                         pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
1559                                         pinctrl-names = "default";
1560
1561                                         compatible = "slim217,1a0";
1562                                         reg  = <1 0>;
1563
1564                                         interrupt-parent = <&msmgpio>;
1565                                         interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
1566                                                      <53 IRQ_TYPE_LEVEL_HIGH>;
1567                                         interrupt-names  = "intr1", "intr2";
1568                                         interrupt-controller;
1569                                         #interrupt-cells = <1>;
1570                                         reset-gpios = <&msmgpio 64 0>;
1571
1572                                         slim-ifc-dev  = <&tasha_ifd>;
1573
1574                                         vdd-buck-supply = <&pm8994_s4>;
1575                                         vdd-buck-sido-supply = <&pm8994_s4>;
1576                                         vdd-tx-supply = <&pm8994_s4>;
1577                                         vdd-rx-supply = <&pm8994_s4>;
1578                                         vdd-io-supply = <&pm8994_s4>;
1579
1580                                         #sound-dai-cells = <1>;
1581                                 };
1582                         };
1583                 };
1584
1585                 gpu@b00000 {
1586                         compatible = "qcom,adreno-530.2", "qcom,adreno";
1587                         #stream-id-cells = <16>;
1588
1589                         reg = <0xb00000 0x3f000>;
1590                         reg-names = "kgsl_3d0_reg_memory";
1591
1592                         interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1593
1594                         clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1595                                 <&mmcc GPU_AHB_CLK>,
1596                                 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1597                                 <&gcc GCC_BIMC_GFX_CLK>,
1598                                 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1599
1600                         clock-names = "core",
1601                                 "iface",
1602                                 "rbbmtimer",
1603                                 "mem",
1604                                 "mem_iface";
1605
1606                         power-domains = <&mmcc GPU_GDSC>;
1607                         iommus = <&adreno_smmu 0>;
1608
1609                         nvmem-cells = <&gpu_speed_bin>;
1610                         nvmem-cell-names = "speed_bin";
1611
1612                         qcom,gpu-quirk-two-pass-use-wfi;
1613                         qcom,gpu-quirk-fault-detect-mask;
1614
1615                         operating-points-v2 = <&gpu_opp_table>;
1616
1617                         gpu_opp_table: opp-table {
1618                                 compatible  ="operating-points-v2";
1619
1620                                 /*
1621                                  * 624Mhz and 560Mhz are only available on speed
1622                                  * bin (1 << 0). All the rest are available on
1623                                  * all bins of the hardware
1624                                  */
1625                                 opp-624000000 {
1626                                         opp-hz = /bits/ 64 <624000000>;
1627                                         opp-supported-hw = <0x01>;
1628                                 };
1629                                 opp-560000000 {
1630                                         opp-hz = /bits/ 64 <560000000>;
1631                                         opp-supported-hw = <0x01>;
1632                                 };
1633                                 opp-510000000 {
1634                                         opp-hz = /bits/ 64 <510000000>;
1635                                         opp-supported-hw = <0xFF>;
1636                                 };
1637                                 opp-401800000 {
1638                                         opp-hz = /bits/ 64 <401800000>;
1639                                         opp-supported-hw = <0xFF>;
1640                                 };
1641                                 opp-315000000 {
1642                                         opp-hz = /bits/ 64 <315000000>;
1643                                         opp-supported-hw = <0xFF>;
1644                                 };
1645                                 opp-214000000 {
1646                                         opp-hz = /bits/ 64 <214000000>;
1647                                         opp-supported-hw = <0xFF>;
1648                                 };
1649                                 opp-133000000 {
1650                                         opp-hz = /bits/ 64 <133000000>;
1651                                         opp-supported-hw = <0xFF>;
1652                                 };
1653                         };
1654
1655                         zap-shader {
1656                                 memory-region = <&zap_shader_region>;
1657                         };
1658                 };
1659
1660                 mdss: mdss@900000 {
1661                         compatible = "qcom,mdss";
1662
1663                         reg = <0x900000 0x1000>,
1664                               <0x9b0000 0x1040>,
1665                               <0x9b8000 0x1040>;
1666                         reg-names = "mdss_phys",
1667                                     "vbif_phys",
1668                                     "vbif_nrt_phys";
1669
1670                         power-domains = <&mmcc MDSS_GDSC>;
1671                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1672
1673                         interrupt-controller;
1674                         #interrupt-cells = <1>;
1675
1676                         clocks = <&mmcc MDSS_AHB_CLK>;
1677                         clock-names = "iface_clk";
1678
1679                         #address-cells = <1>;
1680                         #size-cells = <1>;
1681                         ranges;
1682
1683                         mdp: mdp@901000 {
1684                                 compatible = "qcom,mdp5";
1685                                 reg = <0x901000 0x90000>;
1686                                 reg-names = "mdp_phys";
1687
1688                                 interrupt-parent = <&mdss>;
1689                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
1690
1691                                 clocks = <&mmcc MDSS_AHB_CLK>,
1692                                          <&mmcc MDSS_AXI_CLK>,
1693                                          <&mmcc MDSS_MDP_CLK>,
1694                                          <&mmcc SMMU_MDP_AXI_CLK>,
1695                                          <&mmcc MDSS_VSYNC_CLK>;
1696                                 clock-names = "iface_clk",
1697                                               "bus_clk",
1698                                               "core_clk",
1699                                               "iommu_clk",
1700                                               "vsync_clk";
1701
1702                                 iommus = <&mdp_smmu 0>;
1703
1704                                 ports {
1705                                         #address-cells = <1>;
1706                                         #size-cells = <0>;
1707
1708                                         port@0 {
1709                                                 reg = <0>;
1710                                                 mdp5_intf3_out: endpoint {
1711                                                         remote-endpoint = <&hdmi_in>;
1712                                                 };
1713                                         };
1714                                 };
1715                         };
1716
1717                         hdmi: hdmi-tx@9a0000 {
1718                                 compatible = "qcom,hdmi-tx-8996";
1719                                 reg =   <0x009a0000 0x50c>,
1720                                         <0x00070000 0x6158>,
1721                                         <0x009e0000 0xfff>;
1722                                 reg-names = "core_physical",
1723                                             "qfprom_physical",
1724                                             "hdcp_physical";
1725
1726                                 interrupt-parent = <&mdss>;
1727                                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1728
1729                                 clocks = <&mmcc MDSS_MDP_CLK>,
1730                                          <&mmcc MDSS_AHB_CLK>,
1731                                          <&mmcc MDSS_HDMI_CLK>,
1732                                          <&mmcc MDSS_HDMI_AHB_CLK>,
1733                                          <&mmcc MDSS_EXTPCLK_CLK>;
1734                                 clock-names =
1735                                         "mdp_core_clk",
1736                                         "iface_clk",
1737                                         "core_clk",
1738                                         "alt_iface_clk",
1739                                         "extp_clk";
1740
1741                                 phys = <&hdmi_phy>;
1742                                 phy-names = "hdmi_phy";
1743                                 #sound-dai-cells = <1>;
1744
1745                                 ports {
1746                                         #address-cells = <1>;
1747                                         #size-cells = <0>;
1748
1749                                         port@0 {
1750                                                 reg = <0>;
1751                                                 hdmi_in: endpoint {
1752                                                         remote-endpoint = <&mdp5_intf3_out>;
1753                                                 };
1754                                         };
1755                                 };
1756                         };
1757
1758                         hdmi_phy: hdmi-phy@9a0600 {
1759                                 #phy-cells = <0>;
1760                                 compatible = "qcom,hdmi-phy-8996";
1761                                 reg = <0x9a0600 0x1c4>,
1762                                       <0x9a0a00 0x124>,
1763                                       <0x9a0c00 0x124>,
1764                                       <0x9a0e00 0x124>,
1765                                       <0x9a1000 0x124>,
1766                                       <0x9a1200 0x0c8>;
1767                                 reg-names = "hdmi_pll",
1768                                             "hdmi_tx_l0",
1769                                             "hdmi_tx_l1",
1770                                             "hdmi_tx_l2",
1771                                             "hdmi_tx_l3",
1772                                             "hdmi_phy";
1773
1774                                 clocks = <&mmcc MDSS_AHB_CLK>,
1775                                          <&gcc GCC_HDMI_CLKREF_CLK>;
1776                                 clock-names = "iface_clk",
1777                                               "ref_clk";
1778                         };
1779                 };
1780         };
1781
1782         sound: sound {
1783         };
1784
1785         adsp-pil {
1786                 compatible = "qcom,msm8996-adsp-pil";
1787
1788                 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
1789                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1790                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1791                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1792                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1793                 interrupt-names = "wdog", "fatal", "ready",
1794                                   "handover", "stop-ack";
1795
1796                 clocks = <&xo_board>;
1797                 clock-names = "xo";
1798
1799                 memory-region = <&adsp_region>;
1800
1801                 qcom,smem-states = <&adsp_smp2p_out 0>;
1802                 qcom,smem-state-names = "stop";
1803
1804                 smd-edge {
1805                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1806
1807                         label = "lpass";
1808                         mboxes = <&apcs_glb 8>;
1809                         qcom,smd-edge = <1>;
1810                         qcom,remote-pid = <2>;
1811                         #address-cells = <1>;
1812                         #size-cells = <0>;
1813                         apr {
1814                                 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
1815                                 compatible = "qcom,apr-v2";
1816                                 qcom,smd-channels = "apr_audio_svc";
1817                                 reg = <APR_DOMAIN_ADSP>;
1818                                 #address-cells = <1>;
1819                                 #size-cells = <0>;
1820
1821                                 q6core {
1822                                         reg = <APR_SVC_ADSP_CORE>;
1823                                         compatible = "qcom,q6core";
1824                                 };
1825
1826                                 q6afe: q6afe {
1827                                         compatible = "qcom,q6afe";
1828                                         reg = <APR_SVC_AFE>;
1829                                         q6afedai: dais {
1830                                                 compatible = "qcom,q6afe-dais";
1831                                                 #address-cells = <1>;
1832                                                 #size-cells = <0>;
1833                                                 #sound-dai-cells = <1>;
1834                                                 hdmi@1 {
1835                                                         reg = <1>;
1836                                                 };
1837                                         };
1838                                 };
1839
1840                                 q6asm: q6asm {
1841                                         compatible = "qcom,q6asm";
1842                                         reg = <APR_SVC_ASM>;
1843                                         q6asmdai: dais {
1844                                                 compatible = "qcom,q6asm-dais";
1845                                                 #sound-dai-cells = <1>;
1846                                                 iommus = <&lpass_q6_smmu 1>;
1847                                         };
1848                                 };
1849
1850                                 q6adm: q6adm {
1851                                         compatible = "qcom,q6adm";
1852                                         reg = <APR_SVC_ADM>;
1853                                         q6routing: routing {
1854                                                 compatible = "qcom,q6adm-routing";
1855                                                 #sound-dai-cells = <0>;
1856                                         };
1857                                 };
1858                         };
1859
1860                 };
1861         };
1862
1863         adsp-smp2p {
1864                 compatible = "qcom,smp2p";
1865                 qcom,smem = <443>, <429>;
1866
1867                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
1868
1869                 mboxes = <&apcs_glb 10>;
1870
1871                 qcom,local-pid = <0>;
1872                 qcom,remote-pid = <2>;
1873
1874                 adsp_smp2p_out: master-kernel {
1875                         qcom,entry-name = "master-kernel";
1876                         #qcom,smem-state-cells = <1>;
1877                 };
1878
1879                 adsp_smp2p_in: slave-kernel {
1880                         qcom,entry-name = "slave-kernel";
1881
1882                         interrupt-controller;
1883                         #interrupt-cells = <2>;
1884                 };
1885         };
1886
1887         modem-smp2p {
1888                 compatible = "qcom,smp2p";
1889                 qcom,smem = <435>, <428>;
1890
1891                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1892
1893                 mboxes = <&apcs_glb 14>;
1894
1895                 qcom,local-pid = <0>;
1896                 qcom,remote-pid = <1>;
1897
1898                 modem_smp2p_out: master-kernel {
1899                         qcom,entry-name = "master-kernel";
1900                         #qcom,smem-state-cells = <1>;
1901                 };
1902
1903                 modem_smp2p_in: slave-kernel {
1904                         qcom,entry-name = "slave-kernel";
1905
1906                         interrupt-controller;
1907                         #interrupt-cells = <2>;
1908                 };
1909         };
1910
1911         smp2p-slpi {
1912                 compatible = "qcom,smp2p";
1913                 qcom,smem = <481>, <430>;
1914
1915                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
1916
1917                 mboxes = <&apcs_glb 26>;
1918
1919                 qcom,local-pid = <0>;
1920                 qcom,remote-pid = <3>;
1921
1922                 slpi_smp2p_in: slave-kernel {
1923                         qcom,entry-name = "slave-kernel";
1924                         interrupt-controller;
1925                         #interrupt-cells = <2>;
1926                 };
1927
1928                 slpi_smp2p_out: master-kernel {
1929                         qcom,entry-name = "master-kernel";
1930                         #qcom,smem-state-cells = <1>;
1931                 };
1932         };
1933
1934 };
1935 #include "msm8996-pins.dtsi"