arch/arm64/boot/dts/mediatek/mt2712e.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: YT Shen <yt.shen@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         compatible = "mediatek,mt2712";
  13         interrupt-parent = <&sysirq>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu-map {
  22                         cluster0 {
  23                                 core0 {
  24                                         cpu = <&cpu0>;
  25                                 };
  26                                 core1 {
  27                                         cpu = <&cpu1>;
  28                                 };
  29                         };
  30
  31                         cluster1 {
  32                                 core0 {
  33                                         cpu = <&cpu2>;
  34                                 };
  35                         };
  36                 };
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a35";
  41                         reg = <0x000>;
  42                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  43                 };
  44
  45                 cpu1: cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a35";
  48                         reg = <0x001>;
  49                         enable-method = "psci";
  50                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  51                 };
  52
  53                 cpu2: cpu@200 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a72";
  56                         reg = <0x200>;
  57                         enable-method = "psci";
  58                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  59                 };
  60
  61                 idle-states {
  62                         entry-method = "arm,psci";
  63
  64                         CPU_SLEEP_0: cpu-sleep-0 {
  65                                 compatible = "arm,idle-state";
  66                                 local-timer-stop;
  67                                 entry-latency-us = <100>;
  68                                 exit-latency-us = <80>;
  69                                 min-residency-us = <2000>;
  70                                 arm,psci-suspend-param = <0x0010000>;
  71                         };
  72
  73                         CLUSTER_SLEEP_0: cluster-sleep-0 {
  74                                 compatible = "arm,idle-state";
  75                                 local-timer-stop;
  76                                 entry-latency-us = <350>;
  77                                 exit-latency-us = <80>;
  78                                 min-residency-us = <3000>;
  79                                 arm,psci-suspend-param = <0x1010000>;
  80                         };
  81                 };
  82         };
  83
  84         psci {
  85                 compatible = "arm,psci-0.2";
  86                 method = "smc";
  87         };
  88
  89         baud_clk: dummy26m {
  90                 compatible = "fixed-clock";
  91                 clock-frequency = <26000000>;
  92                 #clock-cells = <0>;
  93         };
  94
  95         sys_clk: dummyclk {
  96                 compatible = "fixed-clock";
  97                 clock-frequency = <26000000>;
  98                 #clock-cells = <0>;
  99         };
 100
 101         timer {
 102                 compatible = "arm,armv8-timer";
 103                 interrupt-parent = <&gic>;
 104                 interrupts = <GIC_PPI 13
 105                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
 106                              <GIC_PPI 14
 107                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
 108                              <GIC_PPI 11
 109                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
 110                              <GIC_PPI 10
 111                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
 112         };
 113
 114         uart5: serial@1000f000 {
 115                 compatible = "mediatek,mt2712-uart",
 116                              "mediatek,mt6577-uart";
 117                 reg = <0 0x1000f000 0 0x400>;
 118                 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
 119                 clocks = <&baud_clk>, <&sys_clk>;
 120                 clock-names = "baud", "bus";
 121                 status = "disabled";
 122         };
 123
 124         sysirq: interrupt-controller@10220a80 {
 125                 compatible = "mediatek,mt2712-sysirq",
 126                              "mediatek,mt6577-sysirq";
 127                 interrupt-controller;
 128                 #interrupt-cells = <3>;
 129                 interrupt-parent = <&gic>;
 130                 reg = <0 0x10220a80 0 0x40>;
 131         };
 132
 133         gic: interrupt-controller@10510000 {
 134                 compatible = "arm,gic-400";
 135                 #interrupt-cells = <3>;
 136                 interrupt-parent = <&gic>;
 137                 interrupt-controller;
 138                 reg = <0 0x10510000 0 0x10000>,
 139                       <0 0x10520000 0 0x20000>,
 140                       <0 0x10540000 0 0x20000>,
 141                       <0 0x10560000 0 0x20000>;
 142                 interrupts = <GIC_PPI 9
 143                          (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
 144         };
 145
 146         uart0: serial@11002000 {
 147                 compatible = "mediatek,mt2712-uart",
 148                              "mediatek,mt6577-uart";
 149                 reg = <0 0x11002000 0 0x400>;
 150                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 151                 clocks = <&baud_clk>, <&sys_clk>;
 152                 clock-names = "baud", "bus";
 153                 status = "disabled";
 154         };
 155
 156         uart1: serial@11003000 {
 157                 compatible = "mediatek,mt2712-uart",
 158                              "mediatek,mt6577-uart";
 159                 reg = <0 0x11003000 0 0x400>;
 160                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 161                 clocks = <&baud_clk>, <&sys_clk>;
 162                 clock-names = "baud", "bus";
 163                 status = "disabled";
 164         };
 165
 166         uart2: serial@11004000 {
 167                 compatible = "mediatek,mt2712-uart",
 168                              "mediatek,mt6577-uart";
 169                 reg = <0 0x11004000 0 0x400>;
 170                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 171                 clocks = <&baud_clk>, <&sys_clk>;
 172                 clock-names = "baud", "bus";
 173                 status = "disabled";
 174         };
 175
 176         uart3: serial@11005000 {
 177                 compatible = "mediatek,mt2712-uart",
 178                              "mediatek,mt6577-uart";
 179                 reg = <0 0x11005000 0 0x400>;
 180                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
 181                 clocks = <&baud_clk>, <&sys_clk>;
 182                 clock-names = "baud", "bus";
 183                 status = "disabled";
 184         };
 185
 186         uart4: serial@11019000 {
 187                 compatible = "mediatek,mt2712-uart",
 188                              "mediatek,mt6577-uart";
 189                 reg = <0 0x11019000 0 0x400>;
 190                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
 191                 clocks = <&baud_clk>, <&sys_clk>;
 192                 clock-names = "baud", "bus";
 193                 status = "disabled";
 194         };
 195 };
 196