arch/arm64/boot/dts/mediatek/mt2712e.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: YT Shen <yt.shen@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 #include <dt-bindings/clock/mt2712-clk.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/power/mt2712-power.h>
  12
  13 / {
  14         compatible = "mediatek,mt2712";
  15         interrupt-parent = <&sysirq>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         cluster0_opp: opp_table0 {
  20                 compatible = "operating-points-v2";
  21                 opp-shared;
  22                 opp00 {
  23                         opp-hz = /bits/ 64 <598000000>;
  24                         opp-microvolt = <1000000>;
  25                 };
  26                 opp01 {
  27                         opp-hz = /bits/ 64 <702000000>;
  28                         opp-microvolt = <1000000>;
  29                 };
  30                 opp02 {
  31                         opp-hz = /bits/ 64 <793000000>;
  32                         opp-microvolt = <1000000>;
  33                 };
  34         };
  35
  36         cluster1_opp: opp_table1 {
  37                 compatible = "operating-points-v2";
  38                 opp-shared;
  39                 opp00 {
  40                         opp-hz = /bits/ 64 <598000000>;
  41                         opp-microvolt = <1000000>;
  42                 };
  43                 opp01 {
  44                         opp-hz = /bits/ 64 <702000000>;
  45                         opp-microvolt = <1000000>;
  46                 };
  47                 opp02 {
  48                         opp-hz = /bits/ 64 <793000000>;
  49                         opp-microvolt = <1000000>;
  50                 };
  51                 opp03 {
  52                         opp-hz = /bits/ 64 <897000000>;
  53                         opp-microvolt = <1000000>;
  54                 };
  55                 opp04 {
  56                         opp-hz = /bits/ 64 <1001000000>;
  57                         opp-microvolt = <1000000>;
  58                 };
  59         };
  60
  61         cpus {
  62                 #address-cells = <1>;
  63                 #size-cells = <0>;
  64
  65                 cpu-map {
  66                         cluster0 {
  67                                 core0 {
  68                                         cpu = <&cpu0>;
  69                                 };
  70                                 core1 {
  71                                         cpu = <&cpu1>;
  72                                 };
  73                         };
  74
  75                         cluster1 {
  76                                 core0 {
  77                                         cpu = <&cpu2>;
  78                                 };
  79                         };
  80                 };
  81
  82                 cpu0: cpu@0 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a35";
  85                         reg = <0x000>;
  86                         clocks = <&mcucfg CLK_MCU_MP0_SEL>,
  87                                 <&topckgen CLK_TOP_F_MP0_PLL1>;
  88                         clock-names = "cpu", "intermediate";
  89                         proc-supply = <&cpus_fixed_vproc0>;
  90                         operating-points-v2 = <&cluster0_opp>;
  91                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  92                 };
  93
  94                 cpu1: cpu@1 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a35";
  97                         reg = <0x001>;
  98                         enable-method = "psci";
  99                         clocks = <&mcucfg CLK_MCU_MP0_SEL>,
 100                                 <&topckgen CLK_TOP_F_MP0_PLL1>;
 101                         clock-names = "cpu", "intermediate";
 102                         proc-supply = <&cpus_fixed_vproc0>;
 103                         operating-points-v2 = <&cluster0_opp>;
 104                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 105                 };
 106
 107                 cpu2: cpu@200 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a72";
 110                         reg = <0x200>;
 111                         enable-method = "psci";
 112                         clocks = <&mcucfg CLK_MCU_MP2_SEL>,
 113                                 <&topckgen CLK_TOP_F_BIG_PLL1>;
 114                         clock-names = "cpu", "intermediate";
 115                         proc-supply = <&cpus_fixed_vproc1>;
 116                         operating-points-v2 = <&cluster1_opp>;
 117                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 118                 };
 119
 120                 idle-states {
 121                         entry-method = "arm,psci";
 122
 123                         CPU_SLEEP_0: cpu-sleep-0 {
 124                                 compatible = "arm,idle-state";
 125                                 local-timer-stop;
 126                                 entry-latency-us = <100>;
 127                                 exit-latency-us = <80>;
 128                                 min-residency-us = <2000>;
 129                                 arm,psci-suspend-param = <0x0010000>;
 130                         };
 131
 132                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 133                                 compatible = "arm,idle-state";
 134                                 local-timer-stop;
 135                                 entry-latency-us = <350>;
 136                                 exit-latency-us = <80>;
 137                                 min-residency-us = <3000>;
 138                                 arm,psci-suspend-param = <0x1010000>;
 139                         };
 140                 };
 141         };
 142
 143         psci {
 144                 compatible = "arm,psci-0.2";
 145                 method = "smc";
 146         };
 147
 148         baud_clk: dummy26m {
 149                 compatible = "fixed-clock";
 150                 clock-frequency = <26000000>;
 151                 #clock-cells = <0>;
 152         };
 153
 154         sys_clk: dummyclk {
 155                 compatible = "fixed-clock";
 156                 clock-frequency = <26000000>;
 157                 #clock-cells = <0>;
 158         };
 159
 160         clk26m: oscillator@0 {
 161                 compatible = "fixed-clock";
 162                 #clock-cells = <0>;
 163                 clock-frequency = <26000000>;
 164                 clock-output-names = "clk26m";
 165         };
 166
 167         clk32k: oscillator@1 {
 168                 compatible = "fixed-clock";
 169                 #clock-cells = <0>;
 170                 clock-frequency = <32768>;
 171                 clock-output-names = "clk32k";
 172         };
 173
 174         clkfpc: oscillator@2 {
 175                 compatible = "fixed-clock";
 176                 #clock-cells = <0>;
 177                 clock-frequency = <50000000>;
 178                 clock-output-names = "clkfpc";
 179         };
 180
 181         clkaud_ext_i_0: oscillator@3 {
 182                 compatible = "fixed-clock";
 183                 #clock-cells = <0>;
 184                 clock-frequency = <6500000>;
 185                 clock-output-names = "clkaud_ext_i_0";
 186         };
 187
 188         clkaud_ext_i_1: oscillator@4 {
 189                 compatible = "fixed-clock";
 190                 #clock-cells = <0>;
 191                 clock-frequency = <196608000>;
 192                 clock-output-names = "clkaud_ext_i_1";
 193         };
 194
 195         clkaud_ext_i_2: oscillator@5 {
 196                 compatible = "fixed-clock";
 197                 #clock-cells = <0>;
 198                 clock-frequency = <180633600>;
 199                 clock-output-names = "clkaud_ext_i_2";
 200         };
 201
 202         timer {
 203                 compatible = "arm,armv8-timer";
 204                 interrupt-parent = <&gic>;
 205                 interrupts = <GIC_PPI 13
 206                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
 207                              <GIC_PPI 14
 208                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
 209                              <GIC_PPI 11
 210                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
 211                              <GIC_PPI 10
 212                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
 213         };
 214
 215         topckgen: syscon@10000000 {
 216                 compatible = "mediatek,mt2712-topckgen", "syscon";
 217                 reg = <0 0x10000000 0 0x1000>;
 218                 #clock-cells = <1>;
 219         };
 220
 221         infracfg: syscon@10001000 {
 222                 compatible = "mediatek,mt2712-infracfg", "syscon";
 223                 reg = <0 0x10001000 0 0x1000>;
 224                 #clock-cells = <1>;
 225         };
 226
 227         pericfg: syscon@10003000 {
 228                 compatible = "mediatek,mt2712-pericfg", "syscon";
 229                 reg = <0 0x10003000 0 0x1000>;
 230                 #clock-cells = <1>;
 231         };
 232
 233         scpsys: scpsys@10006000 {
 234                 compatible = "mediatek,mt2712-scpsys", "syscon";
 235                 #power-domain-cells = <1>;
 236                 reg = <0 0x10006000 0 0x1000>;
 237                 clocks = <&topckgen CLK_TOP_MM_SEL>,
 238                          <&topckgen CLK_TOP_MFG_SEL>,
 239                          <&topckgen CLK_TOP_VENC_SEL>,
 240                          <&topckgen CLK_TOP_JPGDEC_SEL>,
 241                          <&topckgen CLK_TOP_A1SYS_HP_SEL>,
 242                          <&topckgen CLK_TOP_VDEC_SEL>;
 243                 clock-names = "mm", "mfg", "venc",
 244                         "jpgdec", "audio", "vdec";
 245                 infracfg = <&infracfg>;
 246         };
 247
 248         uart5: serial@1000f000 {
 249                 compatible = "mediatek,mt2712-uart",
 250                              "mediatek,mt6577-uart";
 251                 reg = <0 0x1000f000 0 0x400>;
 252                 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
 253                 clocks = <&baud_clk>, <&sys_clk>;
 254                 clock-names = "baud", "bus";
 255                 status = "disabled";
 256         };
 257
 258         apmixedsys: syscon@10209000 {
 259                 compatible = "mediatek,mt2712-apmixedsys", "syscon";
 260                 reg = <0 0x10209000 0 0x1000>;
 261                 #clock-cells = <1>;
 262         };
 263
 264         mcucfg: syscon@10220000 {
 265                 compatible = "mediatek,mt2712-mcucfg", "syscon";
 266                 reg = <0 0x10220000 0 0x1000>;
 267                 #clock-cells = <1>;
 268         };
 269
 270         sysirq: interrupt-controller@10220a80 {
 271                 compatible = "mediatek,mt2712-sysirq",
 272                              "mediatek,mt6577-sysirq";
 273                 interrupt-controller;
 274                 #interrupt-cells = <3>;
 275                 interrupt-parent = <&gic>;
 276                 reg = <0 0x10220a80 0 0x40>;
 277         };
 278
 279         gic: interrupt-controller@10510000 {
 280                 compatible = "arm,gic-400";
 281                 #interrupt-cells = <3>;
 282                 interrupt-parent = <&gic>;
 283                 interrupt-controller;
 284                 reg = <0 0x10510000 0 0x10000>,
 285                       <0 0x10520000 0 0x20000>,
 286                       <0 0x10540000 0 0x20000>,
 287                       <0 0x10560000 0 0x20000>;
 288                 interrupts = <GIC_PPI 9
 289                          (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
 290         };
 291
 292         uart0: serial@11002000 {
 293                 compatible = "mediatek,mt2712-uart",
 294                              "mediatek,mt6577-uart";
 295                 reg = <0 0x11002000 0 0x400>;
 296                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 297                 clocks = <&baud_clk>, <&sys_clk>;
 298                 clock-names = "baud", "bus";
 299                 status = "disabled";
 300         };
 301
 302         uart1: serial@11003000 {
 303                 compatible = "mediatek,mt2712-uart",
 304                              "mediatek,mt6577-uart";
 305                 reg = <0 0x11003000 0 0x400>;
 306                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 307                 clocks = <&baud_clk>, <&sys_clk>;
 308                 clock-names = "baud", "bus";
 309                 status = "disabled";
 310         };
 311
 312         uart2: serial@11004000 {
 313                 compatible = "mediatek,mt2712-uart",
 314                              "mediatek,mt6577-uart";
 315                 reg = <0 0x11004000 0 0x400>;
 316                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 317                 clocks = <&baud_clk>, <&sys_clk>;
 318                 clock-names = "baud", "bus";
 319                 status = "disabled";
 320         };
 321
 322         uart3: serial@11005000 {
 323                 compatible = "mediatek,mt2712-uart",
 324                              "mediatek,mt6577-uart";
 325                 reg = <0 0x11005000 0 0x400>;
 326                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
 327                 clocks = <&baud_clk>, <&sys_clk>;
 328                 clock-names = "baud", "bus";
 329                 status = "disabled";
 330         };
 331
 332         uart4: serial@11019000 {
 333                 compatible = "mediatek,mt2712-uart",
 334                              "mediatek,mt6577-uart";
 335                 reg = <0 0x11019000 0 0x400>;
 336                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
 337                 clocks = <&baud_clk>, <&sys_clk>;
 338                 clock-names = "baud", "bus";
 339                 status = "disabled";
 340         };
 341
 342         mfgcfg: syscon@13000000 {
 343                 compatible = "mediatek,mt2712-mfgcfg", "syscon";
 344                 reg = <0 0x13000000 0 0x1000>;
 345                 #clock-cells = <1>;
 346         };
 347
 348         mmsys: syscon@14000000 {
 349                 compatible = "mediatek,mt2712-mmsys", "syscon";
 350                 reg = <0 0x14000000 0 0x1000>;
 351                 #clock-cells = <1>;
 352         };
 353
 354         imgsys: syscon@15000000 {
 355                 compatible = "mediatek,mt2712-imgsys", "syscon";
 356                 reg = <0 0x15000000 0 0x1000>;
 357                 #clock-cells = <1>;
 358         };
 359
 360         bdpsys: syscon@15010000 {
 361                 compatible = "mediatek,mt2712-bdpsys", "syscon";
 362                 reg = <0 0x15010000 0 0x1000>;
 363                 #clock-cells = <1>;
 364         };
 365
 366         vdecsys: syscon@16000000 {
 367                 compatible = "mediatek,mt2712-vdecsys", "syscon";
 368                 reg = <0 0x16000000 0 0x1000>;
 369                 #clock-cells = <1>;
 370         };
 371
 372         vencsys: syscon@18000000 {
 373                 compatible = "mediatek,mt2712-vencsys", "syscon";
 374                 reg = <0 0x18000000 0 0x1000>;
 375                 #clock-cells = <1>;
 376         };
 377
 378         jpgdecsys: syscon@19000000 {
 379                 compatible = "mediatek,mt2712-jpgdecsys", "syscon";
 380                 reg = <0 0x19000000 0 0x1000>;
 381                 #clock-cells = <1>;
 382         };
 383 };
 384