arch/arm64/boot/dts/mediatek/mt2712e.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: YT Shen <yt.shen@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         compatible = "mediatek,mt2712";
  13         interrupt-parent = <&sysirq>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu-map {
  22                         cluster0 {
  23                                 core0 {
  24                                         cpu = <&cpu0>;
  25                                 };
  26                                 core1 {
  27                                         cpu = <&cpu1>;
  28                                 };
  29                         };
  30
  31                         cluster1 {
  32                                 core0 {
  33                                         cpu = <&cpu2>;
  34                                 };
  35                         };
  36                 };
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a35";
  41                         reg = <0x000>;
  42                 };
  43
  44                 cpu1: cpu@1 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a35";
  47                         reg = <0x001>;
  48                         enable-method = "psci";
  49                 };
  50
  51                 cpu2: cpu@200 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a72";
  54                         reg = <0x200>;
  55                         enable-method = "psci";
  56                 };
  57         };
  58
  59         psci {
  60                 compatible = "arm,psci-0.2";
  61                 method = "smc";
  62         };
  63
  64         baud_clk: dummy26m {
  65                 compatible = "fixed-clock";
  66                 clock-frequency = <26000000>;
  67                 #clock-cells = <0>;
  68         };
  69
  70         sys_clk: dummyclk {
  71                 compatible = "fixed-clock";
  72                 clock-frequency = <26000000>;
  73                 #clock-cells = <0>;
  74         };
  75
  76         timer {
  77                 compatible = "arm,armv8-timer";
  78                 interrupt-parent = <&gic>;
  79                 interrupts = <GIC_PPI 13
  80                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 14
  82                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
  83                              <GIC_PPI 11
  84                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
  85                              <GIC_PPI 10
  86                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
  87         };
  88
  89         uart5: serial@1000f000 {
  90                 compatible = "mediatek,mt2712-uart",
  91                              "mediatek,mt6577-uart";
  92                 reg = <0 0x1000f000 0 0x400>;
  93                 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
  94                 clocks = <&baud_clk>, <&sys_clk>;
  95                 clock-names = "baud", "bus";
  96                 status = "disabled";
  97         };
  98
  99         sysirq: interrupt-controller@10220a80 {
 100                 compatible = "mediatek,mt2712-sysirq",
 101                              "mediatek,mt6577-sysirq";
 102                 interrupt-controller;
 103                 #interrupt-cells = <3>;
 104                 interrupt-parent = <&gic>;
 105                 reg = <0 0x10220a80 0 0x40>;
 106         };
 107
 108         gic: interrupt-controller@10510000 {
 109                 compatible = "arm,gic-400";
 110                 #interrupt-cells = <3>;
 111                 interrupt-parent = <&gic>;
 112                 interrupt-controller;
 113                 reg = <0 0x10510000 0 0x10000>,
 114                       <0 0x10520000 0 0x20000>,
 115                       <0 0x10540000 0 0x20000>,
 116                       <0 0x10560000 0 0x20000>;
 117                 interrupts = <GIC_PPI 9
 118                          (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
 119         };
 120
 121         uart0: serial@11002000 {
 122                 compatible = "mediatek,mt2712-uart",
 123                              "mediatek,mt6577-uart";
 124                 reg = <0 0x11002000 0 0x400>;
 125                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 126                 clocks = <&baud_clk>, <&sys_clk>;
 127                 clock-names = "baud", "bus";
 128                 status = "disabled";
 129         };
 130
 131         uart1: serial@11003000 {
 132                 compatible = "mediatek,mt2712-uart",
 133                              "mediatek,mt6577-uart";
 134                 reg = <0 0x11003000 0 0x400>;
 135                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 136                 clocks = <&baud_clk>, <&sys_clk>;
 137                 clock-names = "baud", "bus";
 138                 status = "disabled";
 139         };
 140
 141         uart2: serial@11004000 {
 142                 compatible = "mediatek,mt2712-uart",
 143                              "mediatek,mt6577-uart";
 144                 reg = <0 0x11004000 0 0x400>;
 145                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 146                 clocks = <&baud_clk>, <&sys_clk>;
 147                 clock-names = "baud", "bus";
 148                 status = "disabled";
 149         };
 150
 151         uart3: serial@11005000 {
 152                 compatible = "mediatek,mt2712-uart",
 153                              "mediatek,mt6577-uart";
 154                 reg = <0 0x11005000 0 0x400>;
 155                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
 156                 clocks = <&baud_clk>, <&sys_clk>;
 157                 clock-names = "baud", "bus";
 158                 status = "disabled";
 159         };
 160
 161         uart4: serial@11019000 {
 162                 compatible = "mediatek,mt2712-uart",
 163                              "mediatek,mt6577-uart";
 164                 reg = <0 0x11019000 0 0x400>;
 165                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
 166                 clocks = <&baud_clk>, <&sys_clk>;
 167                 clock-names = "baud", "bus";
 168                 status = "disabled";
 169         };
 170 };
 171