arch/arm64/boot/dts/freescale/imx8qxp.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2017-2018 NXP
   5  *      Dong Aisheng <aisheng.dong@nxp.com>
   6  */
   7
   8 #include <dt-bindings/clock/imx8-clock.h>
   9 #include <dt-bindings/firmware/imx/rsrc.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
  13
  14 / {
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 gpio0 = &lsio_gpio0;
  21                 gpio1 = &lsio_gpio1;
  22                 gpio2 = &lsio_gpio2;
  23                 gpio3 = &lsio_gpio3;
  24                 gpio4 = &lsio_gpio4;
  25                 gpio5 = &lsio_gpio5;
  26                 gpio6 = &lsio_gpio6;
  27                 gpio7 = &lsio_gpio7;
  28                 mmc0 = &usdhc1;
  29                 mmc1 = &usdhc2;
  30                 mmc2 = &usdhc3;
  31                 mu1 = &lsio_mu1;
  32                 serial0 = &adma_lpuart0;
  33                 serial1 = &adma_lpuart1;
  34                 serial2 = &adma_lpuart2;
  35                 serial3 = &adma_lpuart3;
  36         };
  37
  38         cpus {
  39                 #address-cells = <2>;
  40                 #size-cells = <0>;
  41
  42                 /* We have 1 clusters with 4 Cortex-A35 cores */
  43                 A35_0: cpu@0 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a35";
  46                         reg = <0x0 0x0>;
  47                         enable-method = "psci";
  48                         next-level-cache = <&A35_L2>;
  49                         clocks = <&clk IMX_A35_CLK>;
  50                         operating-points-v2 = <&a35_opp_table>;
  51                         #cooling-cells = <2>;
  52                 };
  53
  54                 A35_1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a35";
  57                         reg = <0x0 0x1>;
  58                         enable-method = "psci";
  59                         next-level-cache = <&A35_L2>;
  60                         clocks = <&clk IMX_A35_CLK>;
  61                         operating-points-v2 = <&a35_opp_table>;
  62                         #cooling-cells = <2>;
  63                 };
  64
  65                 A35_2: cpu@2 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a35";
  68                         reg = <0x0 0x2>;
  69                         enable-method = "psci";
  70                         next-level-cache = <&A35_L2>;
  71                         clocks = <&clk IMX_A35_CLK>;
  72                         operating-points-v2 = <&a35_opp_table>;
  73                         #cooling-cells = <2>;
  74                 };
  75
  76                 A35_3: cpu@3 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a35";
  79                         reg = <0x0 0x3>;
  80                         enable-method = "psci";
  81                         next-level-cache = <&A35_L2>;
  82                         clocks = <&clk IMX_A35_CLK>;
  83                         operating-points-v2 = <&a35_opp_table>;
  84                         #cooling-cells = <2>;
  85                 };
  86
  87                 A35_L2: l2-cache0 {
  88                         compatible = "cache";
  89                 };
  90         };
  91
  92         a35_opp_table: opp-table {
  93                 compatible = "operating-points-v2";
  94                 opp-shared;
  95
  96                 opp-900000000 {
  97                         opp-hz = /bits/ 64 <900000000>;
  98                         opp-microvolt = <1000000>;
  99                         clock-latency-ns = <150000>;
 100                 };
 101
 102                 opp-1200000000 {
 103                         opp-hz = /bits/ 64 <1200000000>;
 104                         opp-microvolt = <1100000>;
 105                         clock-latency-ns = <150000>;
 106                         opp-suspend;
 107                 };
 108         };
 109
 110         gic: interrupt-controller@51a00000 {
 111                 compatible = "arm,gic-v3";
 112                 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
 113                       <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
 114                 #interrupt-cells = <3>;
 115                 interrupt-controller;
 116                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 117         };
 118
 119         reserved-memory {
 120                 #address-cells = <2>;
 121                 #size-cells = <2>;
 122                 ranges;
 123
 124                 dsp_reserved: dsp@92400000 {
 125                         reg = <0 0x92400000 0 0x2000000>;
 126                         no-map;
 127                 };
 128         };
 129
 130         pmu {
 131                 compatible = "arm,armv8-pmuv3";
 132                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 133         };
 134
 135         psci {
 136                 compatible = "arm,psci-1.0";
 137                 method = "smc";
 138         };
 139
 140         scu {
 141                 compatible = "fsl,imx-scu";
 142                 mbox-names = "tx0", "tx1", "tx2", "tx3",
 143                              "rx0", "rx1", "rx2", "rx3",
 144                              "gip3";
 145                 mboxes = <&lsio_mu1 0 0
 146                           &lsio_mu1 0 1
 147                           &lsio_mu1 0 2
 148                           &lsio_mu1 0 3
 149                           &lsio_mu1 1 0
 150                           &lsio_mu1 1 1
 151                           &lsio_mu1 1 2
 152                           &lsio_mu1 1 3
 153                           &lsio_mu1 3 3>;
 154
 155                 clk: clock-controller {
 156                         compatible = "fsl,imx8qxp-clk";
 157                         #clock-cells = <1>;
 158                         clocks = <&xtal32k &xtal24m>;
 159                         clock-names = "xtal_32KHz", "xtal_24Mhz";
 160                 };
 161
 162                 iomuxc: pinctrl {
 163                         compatible = "fsl,imx8qxp-iomuxc";
 164                 };
 165
 166                 ocotp: imx8qx-ocotp {
 167                         compatible = "fsl,imx8qxp-scu-ocotp";
 168                         #address-cells = <1>;
 169                         #size-cells = <1>;
 170                 };
 171
 172                 pd: imx8qx-pd {
 173                         compatible = "fsl,imx8qxp-scu-pd";
 174                         #power-domain-cells = <1>;
 175                 };
 176
 177                 rtc: rtc {
 178                         compatible = "fsl,imx8qxp-sc-rtc";
 179                 };
 180
 181                 watchdog {
 182                         compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
 183                         timeout-sec = <60>;
 184                 };
 185         };
 186
 187         timer {
 188                 compatible = "arm,armv8-timer";
 189                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
 190                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
 191                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
 192                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
 193         };
 194
 195         xtal32k: clock-xtal32k {
 196                 compatible = "fixed-clock";
 197                 #clock-cells = <0>;
 198                 clock-frequency = <32768>;
 199                 clock-output-names = "xtal_32KHz";
 200         };
 201
 202         xtal24m: clock-xtal24m {
 203                 compatible = "fixed-clock";
 204                 #clock-cells = <0>;
 205                 clock-frequency = <24000000>;
 206                 clock-output-names = "xtal_24MHz";
 207         };
 208
 209         adma_subsys: bus@59000000 {
 210                 compatible = "simple-bus";
 211                 #address-cells = <1>;
 212                 #size-cells = <1>;
 213                 ranges = <0x59000000 0x0 0x59000000 0x2000000>;
 214
 215                 adma_lpcg: clock-controller@59000000 {
 216                         compatible = "fsl,imx8qxp-lpcg-adma";
 217                         reg = <0x59000000 0x2000000>;
 218                         #clock-cells = <1>;
 219                 };
 220
 221                 adma_dsp: dsp@596e8000 {
 222                         compatible = "fsl,imx8qxp-dsp";
 223                         reg = <0x596e8000 0x88000>;
 224                         clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
 225                                 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
 226                                 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
 227                         clock-names = "ipg", "ocram", "core";
 228                         power-domains = <&pd IMX_SC_R_MU_13A>,
 229                                 <&pd IMX_SC_R_MU_13B>,
 230                                 <&pd IMX_SC_R_DSP>,
 231                                 <&pd IMX_SC_R_DSP_RAM>;
 232                         mbox-names = "txdb0", "txdb1",
 233                                 "rxdb0", "rxdb1";
 234                         mboxes = <&lsio_mu13 2 0>,
 235                                 <&lsio_mu13 2 1>,
 236                                 <&lsio_mu13 3 0>,
 237                                 <&lsio_mu13 3 1>;
 238                         memory-region = <&dsp_reserved>;
 239                         status = "disabled";
 240                 };
 241
 242                 adma_lpuart0: serial@5a060000 {
 243                         compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
 244                         reg = <0x5a060000 0x1000>;
 245                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 246                         interrupt-parent = <&gic>;
 247                         clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
 248                                  <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
 249                         clock-names = "ipg", "baud";
 250                         power-domains = <&pd IMX_SC_R_UART_0>;
 251                         status = "disabled";
 252                 };
 253
 254                 adma_lpuart1: serial@5a070000 {
 255                         compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
 256                         reg = <0x5a070000 0x1000>;
 257                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 258                         interrupt-parent = <&gic>;
 259                         clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
 260                                  <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
 261                         clock-names = "ipg", "baud";
 262                         power-domains = <&pd IMX_SC_R_UART_1>;
 263                         status = "disabled";
 264                 };
 265
 266                 adma_lpuart2: serial@5a080000 {
 267                         compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
 268                         reg = <0x5a080000 0x1000>;
 269                         interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 270                         interrupt-parent = <&gic>;
 271                         clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
 272                                  <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
 273                         clock-names = "ipg", "baud";
 274                         power-domains = <&pd IMX_SC_R_UART_2>;
 275                         status = "disabled";
 276                 };
 277
 278                 adma_lpuart3: serial@5a090000 {
 279                         compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
 280                         reg = <0x5a090000 0x1000>;
 281                         interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
 282                         interrupt-parent = <&gic>;
 283                         clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
 284                                  <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
 285                         clock-names = "ipg", "baud";
 286                         power-domains = <&pd IMX_SC_R_UART_3>;
 287                         status = "disabled";
 288                 };
 289
 290                 adma_i2c0: i2c@5a800000 {
 291                         compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 292                         reg = <0x5a800000 0x4000>;
 293                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 294                         interrupt-parent = <&gic>;
 295                         clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
 296                         clock-names = "per";
 297                         assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
 298                         assigned-clock-rates = <24000000>;
 299                         power-domains = <&pd IMX_SC_R_I2C_0>;
 300                         status = "disabled";
 301                 };
 302
 303                 adma_i2c1: i2c@5a810000 {
 304                         compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 305                         reg = <0x5a810000 0x4000>;
 306                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 307                         interrupt-parent = <&gic>;
 308                         clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
 309                         clock-names = "per";
 310                         assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
 311                         assigned-clock-rates = <24000000>;
 312                         power-domains = <&pd IMX_SC_R_I2C_1>;
 313                         status = "disabled";
 314                 };
 315
 316                 adma_i2c2: i2c@5a820000 {
 317                         compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 318                         reg = <0x5a820000 0x4000>;
 319                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
 320                         interrupt-parent = <&gic>;
 321                         clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
 322                         clock-names = "per";
 323                         assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
 324                         assigned-clock-rates = <24000000>;
 325                         power-domains = <&pd IMX_SC_R_I2C_2>;
 326                         status = "disabled";
 327                 };
 328
 329                 adma_i2c3: i2c@5a830000 {
 330                         compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 331                         reg = <0x5a830000 0x4000>;
 332                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 333                         interrupt-parent = <&gic>;
 334                         clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
 335                         clock-names = "per";
 336                         assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
 337                         assigned-clock-rates = <24000000>;
 338                         power-domains = <&pd IMX_SC_R_I2C_3>;
 339                         status = "disabled";
 340                 };
 341         };
 342
 343         conn_subsys: bus@5b000000 {
 344                 compatible = "simple-bus";
 345                 #address-cells = <1>;
 346                 #size-cells = <1>;
 347                 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
 348
 349                 conn_lpcg: clock-controller@5b200000 {
 350                         compatible = "fsl,imx8qxp-lpcg-conn";
 351                         reg = <0x5b200000 0xb0000>;
 352                         #clock-cells = <1>;
 353                 };
 354
 355                 usdhc1: mmc@5b010000 {
 356                         compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
 357                         interrupt-parent = <&gic>;
 358                         interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
 359                         reg = <0x5b010000 0x10000>;
 360                         clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
 361                                  <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
 362                                  <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
 363                         clock-names = "ipg", "per", "ahb";
 364                         assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
 365                         assigned-clock-rates = <200000000>;
 366                         power-domains = <&pd IMX_SC_R_SDHC_0>;
 367                         status = "disabled";
 368                 };
 369
 370                 usdhc2: mmc@5b020000 {
 371                         compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
 372                         interrupt-parent = <&gic>;
 373                         interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 374                         reg = <0x5b020000 0x10000>;
 375                         clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
 376                                  <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
 377                                  <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
 378                         clock-names = "ipg", "per", "ahb";
 379                         assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
 380                         assigned-clock-rates = <200000000>;
 381                         power-domains = <&pd IMX_SC_R_SDHC_1>;
 382                         fsl,tuning-start-tap = <20>;
 383                         fsl,tuning-step= <2>;
 384                         status = "disabled";
 385                 };
 386
 387                 usdhc3: mmc@5b030000 {
 388                         compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
 389                         interrupt-parent = <&gic>;
 390                         interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
 391                         reg = <0x5b030000 0x10000>;
 392                         clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
 393                                  <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
 394                                  <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
 395                         clock-names = "ipg", "per", "ahb";
 396                         assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>;
 397                         assigned-clock-rates = <200000000>;
 398                         power-domains = <&pd IMX_SC_R_SDHC_2>;
 399                         status = "disabled";
 400                 };
 401
 402                 fec1: ethernet@5b040000 {
 403                         compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
 404                         reg = <0x5b040000 0x10000>;
 405                         interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 406                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 407                                      <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 408                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
 409                         clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
 410                                  <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
 411                                  <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
 412                                  <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
 413                         clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
 414                         fsl,num-tx-queues=<3>;
 415                         fsl,num-rx-queues=<3>;
 416                         power-domains = <&pd IMX_SC_R_ENET_0>;
 417                         status = "disabled";
 418                 };
 419
 420                 fec2: ethernet@5b050000 {
 421                         compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
 422                         reg = <0x5b050000 0x10000>;
 423                         interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 424                                         <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 425                                         <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 426                                         <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 427                         clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
 428                                  <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
 429                                  <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
 430                                  <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
 431                         clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
 432                         fsl,num-tx-queues=<3>;
 433                         fsl,num-rx-queues=<3>;
 434                         power-domains = <&pd IMX_SC_R_ENET_1>;
 435                         status = "disabled";
 436                 };
 437         };
 438
 439         ddr_subsyss: bus@5c000000 {
 440                 compatible = "simple-bus";
 441                 #address-cells = <1>;
 442                 #size-cells = <1>;
 443                 ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
 444
 445                 ddr-pmu@5c020000 {
 446                         compatible = "fsl,imx8-ddr-pmu";
 447                         reg = <0x5c020000 0x10000>;
 448                         interrupt-parent = <&gic>;
 449                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 450                 };
 451         };
 452
 453         lsio_subsys: bus@5d000000 {
 454                 compatible = "simple-bus";
 455                 #address-cells = <1>;
 456                 #size-cells = <1>;
 457                 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
 458
 459                 lsio_gpio0: gpio@5d080000 {
 460                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 461                         reg = <0x5d080000 0x10000>;
 462                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 463                         gpio-controller;
 464                         #gpio-cells = <2>;
 465                         interrupt-controller;
 466                         #interrupt-cells = <2>;
 467                         power-domains = <&pd IMX_SC_R_GPIO_0>;
 468                 };
 469
 470                 lsio_gpio1: gpio@5d090000 {
 471                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 472                         reg = <0x5d090000 0x10000>;
 473                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 474                         gpio-controller;
 475                         #gpio-cells = <2>;
 476                         interrupt-controller;
 477                         #interrupt-cells = <2>;
 478                         power-domains = <&pd IMX_SC_R_GPIO_1>;
 479                 };
 480
 481                 lsio_gpio2: gpio@5d0a0000 {
 482                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 483                         reg = <0x5d0a0000 0x10000>;
 484                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 485                         gpio-controller;
 486                         #gpio-cells = <2>;
 487                         interrupt-controller;
 488                         #interrupt-cells = <2>;
 489                         power-domains = <&pd IMX_SC_R_GPIO_2>;
 490                 };
 491
 492                 lsio_gpio3: gpio@5d0b0000 {
 493                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 494                         reg = <0x5d0b0000 0x10000>;
 495                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 496                         gpio-controller;
 497                         #gpio-cells = <2>;
 498                         interrupt-controller;
 499                         #interrupt-cells = <2>;
 500                         power-domains = <&pd IMX_SC_R_GPIO_3>;
 501                 };
 502
 503                 lsio_gpio4: gpio@5d0c0000 {
 504                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 505                         reg = <0x5d0c0000 0x10000>;
 506                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 507                         gpio-controller;
 508                         #gpio-cells = <2>;
 509                         interrupt-controller;
 510                         #interrupt-cells = <2>;
 511                         power-domains = <&pd IMX_SC_R_GPIO_4>;
 512                 };
 513
 514                 lsio_gpio5: gpio@5d0d0000 {
 515                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 516                         reg = <0x5d0d0000 0x10000>;
 517                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 518                         gpio-controller;
 519                         #gpio-cells = <2>;
 520                         interrupt-controller;
 521                         #interrupt-cells = <2>;
 522                         power-domains = <&pd IMX_SC_R_GPIO_5>;
 523                 };
 524
 525                 lsio_gpio6: gpio@5d0e0000 {
 526                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 527                         reg = <0x5d0e0000 0x10000>;
 528                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 529                         gpio-controller;
 530                         #gpio-cells = <2>;
 531                         interrupt-controller;
 532                         #interrupt-cells = <2>;
 533                         power-domains = <&pd IMX_SC_R_GPIO_6>;
 534                 };
 535
 536                 lsio_gpio7: gpio@5d0f0000 {
 537                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 538                         reg = <0x5d0f0000 0x10000>;
 539                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 540                         gpio-controller;
 541                         #gpio-cells = <2>;
 542                         interrupt-controller;
 543                         #interrupt-cells = <2>;
 544                         power-domains = <&pd IMX_SC_R_GPIO_7>;
 545                 };
 546
 547                 lsio_mu0: mailbox@5d1b0000 {
 548                         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 549                         reg = <0x5d1b0000 0x10000>;
 550                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 551                         #mbox-cells = <2>;
 552                         status = "disabled";
 553                 };
 554
 555                 lsio_mu1: mailbox@5d1c0000 {
 556                         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 557                         reg = <0x5d1c0000 0x10000>;
 558                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 559                         #mbox-cells = <2>;
 560                 };
 561
 562                 lsio_mu2: mailbox@5d1d0000 {
 563                         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 564                         reg = <0x5d1d0000 0x10000>;
 565                         interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 566                         #mbox-cells = <2>;
 567                         status = "disabled";
 568                 };
 569
 570                 lsio_mu3: mailbox@5d1e0000 {
 571                         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 572                         reg = <0x5d1e0000 0x10000>;
 573                         interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 574                         #mbox-cells = <2>;
 575                         status = "disabled";
 576                 };
 577
 578                 lsio_mu4: mailbox@5d1f0000 {
 579                         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 580                         reg = <0x5d1f0000 0x10000>;
 581                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 582                         #mbox-cells = <2>;
 583                         status = "disabled";
 584                 };
 585
 586                 lsio_mu13: mailbox@5d280000 {
 587                         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 588                         reg = <0x5d280000 0x10000>;
 589                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 590                         #mbox-cells = <2>;
 591                         power-domains = <&pd IMX_SC_R_MU_13A>;
 592                 };
 593
 594                 lsio_lpcg: clock-controller@5d400000 {
 595                         compatible = "fsl,imx8qxp-lpcg-lsio";
 596                         reg = <0x5d400000 0x400000>;
 597                         #clock-cells = <1>;
 598                 };
 599         };
 600 };