arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for Freescale Layerscape-1012A family SoC.
   4  *
   5  * Copyright 2016 Freescale Semiconductor, Inc.
   6  *
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 / {
  13         compatible = "fsl,ls1012a";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 crypto = &crypto;
  20                 rtic-a = &rtic_a;
  21                 rtic-b = &rtic_b;
  22                 rtic-c = &rtic_c;
  23                 rtic-d = &rtic_d;
  24                 sec-mon = &sec_mon;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu0: cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a53";
  34                         reg = <0x0>;
  35                         clocks = <&clockgen 1 0>;
  36                         #cooling-cells = <2>;
  37                         cpu-idle-states = <&CPU_PH20>;
  38                 };
  39         };
  40
  41         idle-states {
  42                 /*
  43                  * PSCI node is not added default, U-boot will add missing
  44                  * parts if it determines to use PSCI.
  45                  */
  46                 entry-method = "psci";
  47
  48                 CPU_PH20: cpu-ph20 {
  49                         compatible = "arm,idle-state";
  50                         idle-state-name = "PH20";
  51                         arm,psci-suspend-param = <0x0>;
  52                         entry-latency-us = <1000>;
  53                         exit-latency-us = <1000>;
  54                         min-residency-us = <3000>;
  55                 };
  56         };
  57
  58         sysclk: sysclk {
  59                 compatible = "fixed-clock";
  60                 #clock-cells = <0>;
  61                 clock-frequency = <125000000>;
  62                 clock-output-names = "sysclk";
  63         };
  64
  65         coreclk: coreclk {
  66                 compatible = "fixed-clock";
  67                 #clock-cells = <0>;
  68                 clock-frequency = <100000000>;
  69                 clock-output-names = "coreclk";
  70         };
  71
  72         timer {
  73                 compatible = "arm,armv8-timer";
  74                 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
  75                              <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
  76                              <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
  77                              <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
  78         };
  79
  80         pmu {
  81                 compatible = "arm,armv8-pmuv3";
  82                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
  83         };
  84
  85         gic: interrupt-controller@1400000 {
  86                 compatible = "arm,gic-400";
  87                 #interrupt-cells = <3>;
  88                 interrupt-controller;
  89                 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
  90                       <0x0 0x1402000 0 0x2000>, /* GICC */
  91                       <0x0 0x1404000 0 0x2000>, /* GICH */
  92                       <0x0 0x1406000 0 0x2000>; /* GICV */
  93                 interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
  94         };
  95
  96         reboot {
  97                 compatible = "syscon-reboot";
  98                 regmap = <&dcfg>;
  99                 offset = <0xb0>;
 100                 mask = <0x02>;
 101         };
 102
 103         thermal-zones {
 104                 cpu_thermal: cpu-thermal {
 105                         polling-delay-passive = <1000>;
 106                         polling-delay = <5000>;
 107                         thermal-sensors = <&tmu 0>;
 108
 109                         trips {
 110                                 cpu_alert: cpu-alert {
 111                                         temperature = <85000>;
 112                                         hysteresis = <2000>;
 113                                         type = "passive";
 114                                 };
 115
 116                                 cpu_crit: cpu-crit {
 117                                         temperature = <95000>;
 118                                         hysteresis = <2000>;
 119                                         type = "critical";
 120                                 };
 121                         };
 122
 123                         cooling-maps {
 124                                 map0 {
 125                                         trip = <&cpu_alert>;
 126                                         cooling-device =
 127                                                 <&cpu0 THERMAL_NO_LIMIT
 128                                                 THERMAL_NO_LIMIT>;
 129                                 };
 130                         };
 131                 };
 132         };
 133
 134         soc {
 135                 compatible = "simple-bus";
 136                 #address-cells = <2>;
 137                 #size-cells = <2>;
 138                 ranges;
 139
 140                 esdhc0: esdhc@1560000 {
 141                         compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
 142                         reg = <0x0 0x1560000 0x0 0x10000>;
 143                         interrupts = <0 62 0x4>;
 144                         clocks = <&clockgen 4 0>;
 145                         voltage-ranges = <1800 1800 3300 3300>;
 146                         sdhci,auto-cmd12;
 147                         big-endian;
 148                         bus-width = <4>;
 149                         status = "disabled";
 150                 };
 151
 152                 scfg: scfg@1570000 {
 153                         compatible = "fsl,ls1012a-scfg", "syscon";
 154                         reg = <0x0 0x1570000 0x0 0x10000>;
 155                         big-endian;
 156                 };
 157
 158                 esdhc1: esdhc@1580000 {
 159                         compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
 160                         reg = <0x0 0x1580000 0x0 0x10000>;
 161                         interrupts = <0 65 0x4>;
 162                         clocks = <&clockgen 4 0>;
 163                         voltage-ranges = <1800 1800 3300 3300>;
 164                         sdhci,auto-cmd12;
 165                         big-endian;
 166                         broken-cd;
 167                         bus-width = <4>;
 168                         status = "disabled";
 169                 };
 170
 171                 crypto: crypto@1700000 {
 172                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 173                                      "fsl,sec-v4.0";
 174                         fsl,sec-era = <8>;
 175                         #address-cells = <1>;
 176                         #size-cells = <1>;
 177                         ranges = <0x0 0x00 0x1700000 0x100000>;
 178                         reg = <0x00 0x1700000 0x0 0x100000>;
 179                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 180
 181                         sec_jr0: jr@10000 {
 182                                 compatible = "fsl,sec-v5.4-job-ring",
 183                                              "fsl,sec-v5.0-job-ring",
 184                                              "fsl,sec-v4.0-job-ring";
 185                                 reg        = <0x10000 0x10000>;
 186                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 187                         };
 188
 189                         sec_jr1: jr@20000 {
 190                                 compatible = "fsl,sec-v5.4-job-ring",
 191                                              "fsl,sec-v5.0-job-ring",
 192                                              "fsl,sec-v4.0-job-ring";
 193                                 reg        = <0x20000 0x10000>;
 194                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 195                         };
 196
 197                         sec_jr2: jr@30000 {
 198                                 compatible = "fsl,sec-v5.4-job-ring",
 199                                              "fsl,sec-v5.0-job-ring",
 200                                              "fsl,sec-v4.0-job-ring";
 201                                 reg        = <0x30000 0x10000>;
 202                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 203                         };
 204
 205                         sec_jr3: jr@40000 {
 206                                 compatible = "fsl,sec-v5.4-job-ring",
 207                                              "fsl,sec-v5.0-job-ring",
 208                                              "fsl,sec-v4.0-job-ring";
 209                                 reg        = <0x40000 0x10000>;
 210                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 211                         };
 212
 213                         rtic@60000 {
 214                                 compatible = "fsl,sec-v5.4-rtic",
 215                                              "fsl,sec-v5.0-rtic",
 216                                              "fsl,sec-v4.0-rtic";
 217                                 #address-cells = <1>;
 218                                 #size-cells = <1>;
 219                                 reg = <0x60000 0x100 0x60e00 0x18>;
 220                                 ranges = <0x0 0x60100 0x500>;
 221
 222                                 rtic_a: rtic-a@0 {
 223                                         compatible = "fsl,sec-v5.4-rtic-memory",
 224                                                      "fsl,sec-v5.0-rtic-memory",
 225                                                      "fsl,sec-v4.0-rtic-memory";
 226                                         reg = <0x00 0x20 0x100 0x100>;
 227                                 };
 228
 229                                 rtic_b: rtic-b@20 {
 230                                         compatible = "fsl,sec-v5.4-rtic-memory",
 231                                                      "fsl,sec-v5.0-rtic-memory",
 232                                                      "fsl,sec-v4.0-rtic-memory";
 233                                         reg = <0x20 0x20 0x200 0x100>;
 234                                 };
 235
 236                                 rtic_c: rtic-c@40 {
 237                                         compatible = "fsl,sec-v5.4-rtic-memory",
 238                                                      "fsl,sec-v5.0-rtic-memory",
 239                                                      "fsl,sec-v4.0-rtic-memory";
 240                                         reg = <0x40 0x20 0x300 0x100>;
 241                                 };
 242
 243                                 rtic_d: rtic-d@60 {
 244                                         compatible = "fsl,sec-v5.4-rtic-memory",
 245                                                      "fsl,sec-v5.0-rtic-memory",
 246                                                      "fsl,sec-v4.0-rtic-memory";
 247                                         reg = <0x60 0x20 0x400 0x100>;
 248                                 };
 249                         };
 250                 };
 251
 252                 sec_mon: sec_mon@1e90000 {
 253                         compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
 254                                      "fsl,sec-v4.0-mon";
 255                         reg = <0x0 0x1e90000 0x0 0x10000>;
 256                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 257                                      <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 258                 };
 259
 260                 dcfg: dcfg@1ee0000 {
 261                         compatible = "fsl,ls1012a-dcfg",
 262                                      "syscon";
 263                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 264                         big-endian;
 265                 };
 266
 267                 clockgen: clocking@1ee1000 {
 268                         compatible = "fsl,ls1012a-clockgen";
 269                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 270                         #clock-cells = <2>;
 271                         clocks = <&sysclk &coreclk>;
 272                         clock-names = "sysclk", "coreclk";
 273                 };
 274
 275                 tmu: tmu@1f00000 {
 276                         compatible = "fsl,qoriq-tmu";
 277                         reg = <0x0 0x1f00000 0x0 0x10000>;
 278                         interrupts = <0 33 0x4>;
 279                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 280                         fsl,tmu-calibration = <0x00000000 0x00000026
 281                                                0x00000001 0x0000002d
 282                                                0x00000002 0x00000032
 283                                                0x00000003 0x00000039
 284                                                0x00000004 0x0000003f
 285                                                0x00000005 0x00000046
 286                                                0x00000006 0x0000004d
 287                                                0x00000007 0x00000054
 288                                                0x00000008 0x0000005a
 289                                                0x00000009 0x00000061
 290                                                0x0000000a 0x0000006a
 291                                                0x0000000b 0x00000071
 292
 293                                                0x00010000 0x00000025
 294                                                0x00010001 0x0000002c
 295                                                0x00010002 0x00000035
 296                                                0x00010003 0x0000003d
 297                                                0x00010004 0x00000045
 298                                                0x00010005 0x0000004e
 299                                                0x00010006 0x00000057
 300                                                0x00010007 0x00000061
 301                                                0x00010008 0x0000006b
 302                                                0x00010009 0x00000076
 303
 304                                                0x00020000 0x00000029
 305                                                0x00020001 0x00000033
 306                                                0x00020002 0x0000003d
 307                                                0x00020003 0x00000049
 308                                                0x00020004 0x00000056
 309                                                0x00020005 0x00000061
 310                                                0x00020006 0x0000006d
 311
 312                                                0x00030000 0x00000021
 313                                                0x00030001 0x0000002a
 314                                                0x00030002 0x0000003c
 315                                                0x00030003 0x0000004e>;
 316                         big-endian;
 317                         #thermal-sensor-cells = <1>;
 318                 };
 319
 320                 i2c0: i2c@2180000 {
 321                         compatible = "fsl,vf610-i2c";
 322                         #address-cells = <1>;
 323                         #size-cells = <0>;
 324                         reg = <0x0 0x2180000 0x0 0x10000>;
 325                         interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 326                         clocks = <&clockgen 4 0>;
 327                         status = "disabled";
 328                 };
 329
 330                 i2c1: i2c@2190000 {
 331                         compatible = "fsl,vf610-i2c";
 332                         #address-cells = <1>;
 333                         #size-cells = <0>;
 334                         reg = <0x0 0x2190000 0x0 0x10000>;
 335                         interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 336                         clocks = <&clockgen 4 0>;
 337                         status = "disabled";
 338                 };
 339
 340                 dspi: spi@2100000 {
 341                         compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
 342                         #address-cells = <1>;
 343                         #size-cells = <0>;
 344                         reg = <0x0 0x2100000 0x0 0x10000>;
 345                         interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
 346                         clock-names = "dspi";
 347                         clocks = <&clockgen 4 0>;
 348                         spi-num-chipselects = <5>;
 349                         big-endian;
 350                         status = "disabled";
 351                 };
 352
 353                 duart0: serial@21c0500 {
 354                         compatible = "fsl,ns16550", "ns16550a";
 355                         reg = <0x00 0x21c0500 0x0 0x100>;
 356                         interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
 357                         clocks = <&clockgen 4 0>;
 358                         status = "disabled";
 359                 };
 360
 361                 duart1: serial@21c0600 {
 362                         compatible = "fsl,ns16550", "ns16550a";
 363                         reg = <0x00 0x21c0600 0x0 0x100>;
 364                         interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
 365                         clocks = <&clockgen 4 0>;
 366                         status = "disabled";
 367                 };
 368
 369                 gpio0: gpio@2300000 {
 370                         compatible = "fsl,qoriq-gpio";
 371                         reg = <0x0 0x2300000 0x0 0x10000>;
 372                         interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
 373                         gpio-controller;
 374                         #gpio-cells = <2>;
 375                         interrupt-controller;
 376                         #interrupt-cells = <2>;
 377                 };
 378
 379                 gpio1: gpio@2310000 {
 380                         compatible = "fsl,qoriq-gpio";
 381                         reg = <0x0 0x2310000 0x0 0x10000>;
 382                         interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
 383                         gpio-controller;
 384                         #gpio-cells = <2>;
 385                         interrupt-controller;
 386                         #interrupt-cells = <2>;
 387                 };
 388
 389                 wdog0: wdog@2ad0000 {
 390                         compatible = "fsl,ls1012a-wdt",
 391                                      "fsl,imx21-wdt";
 392                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 393                         interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 394                         clocks = <&clockgen 4 0>;
 395                         big-endian;
 396                 };
 397
 398                 sai1: sai@2b50000 {
 399                         #sound-dai-cells = <0>;
 400                         compatible = "fsl,vf610-sai";
 401                         reg = <0x0 0x2b50000 0x0 0x10000>;
 402                         interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 403                         clocks = <&clockgen 4 3>, <&clockgen 4 3>,
 404                                  <&clockgen 4 3>, <&clockgen 4 3>;
 405                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 406                         dma-names = "tx", "rx";
 407                         dmas = <&edma0 1 47>,
 408                                <&edma0 1 46>;
 409                         status = "disabled";
 410                 };
 411
 412                 sai2: sai@2b60000 {
 413                         #sound-dai-cells = <0>;
 414                         compatible = "fsl,vf610-sai";
 415                         reg = <0x0 0x2b60000 0x0 0x10000>;
 416                         interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 417                         clocks = <&clockgen 4 3>, <&clockgen 4 3>,
 418                                  <&clockgen 4 3>, <&clockgen 4 3>;
 419                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 420                         dma-names = "tx", "rx";
 421                         dmas = <&edma0 1 45>,
 422                                <&edma0 1 44>;
 423                         status = "disabled";
 424                 };
 425
 426                 edma0: edma@2c00000 {
 427                         #dma-cells = <2>;
 428                         compatible = "fsl,vf610-edma";
 429                         reg = <0x0 0x2c00000 0x0 0x10000>,
 430                               <0x0 0x2c10000 0x0 0x10000>,
 431                               <0x0 0x2c20000 0x0 0x10000>;
 432                         interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
 433                                      <0 103 IRQ_TYPE_LEVEL_HIGH>;
 434                         interrupt-names = "edma-tx", "edma-err";
 435                         dma-channels = <32>;
 436                         big-endian;
 437                         clock-names = "dmamux0", "dmamux1";
 438                         clocks = <&clockgen 4 3>,
 439                                  <&clockgen 4 3>;
 440                 };
 441
 442                 usb0: usb3@2f00000 {
 443                         compatible = "snps,dwc3";
 444                         reg = <0x0 0x2f00000 0x0 0x10000>;
 445                         interrupts = <0 60 0x4>;
 446                         dr_mode = "host";
 447                         snps,quirk-frame-length-adjustment = <0x20>;
 448                         snps,dis_rxdet_inp3_quirk;
 449                 };
 450
 451                 sata: sata@3200000 {
 452                         compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
 453                         reg = <0x0 0x3200000 0x0 0x10000>,
 454                                 <0x0 0x20140520 0x0 0x4>;
 455                         reg-names = "ahci", "sata-ecc";
 456                         interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 457                         clocks = <&clockgen 4 0>;
 458                         dma-coherent;
 459                         status = "disabled";
 460                 };
 461
 462                 usb1: usb2@8600000 {
 463                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 464                         reg = <0x0 0x8600000 0x0 0x1000>;
 465                         interrupts = <0 139 0x4>;
 466                         dr_mode = "host";
 467                         phy_type = "ulpi";
 468                 };
 469
 470                 msi: msi-controller1@1572000 {
 471                         compatible = "fsl,ls1012a-msi";
 472                         reg = <0x0 0x1572000 0x0 0x8>;
 473                         msi-controller;
 474                         interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
 475                 };
 476
 477                 pcie@3400000 {
 478                         compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
 479                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 480                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 481                         reg-names = "regs", "config";
 482                         interrupts = <0 118 0x4>, /* controller interrupt */
 483                                      <0 117 0x4>; /* PME interrupt */
 484                         interrupt-names = "aer", "pme";
 485                         #address-cells = <3>;
 486                         #size-cells = <2>;
 487                         device_type = "pci";
 488                         num-lanes = <4>;
 489                         bus-range = <0x0 0xff>;
 490                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 491                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 492                         msi-parent = <&msi>;
 493                         #interrupt-cells = <1>;
 494                         interrupt-map-mask = <0 0 0 7>;
 495                         interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
 496                                         <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
 497                                         <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
 498                                         <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
 499                 };
 500         };
 501
 502         firmware {
 503                 optee {
 504                         compatible = "linaro,optee-tz";
 505                         method = "smc";
 506                 };
 507         };
 508 };