arch/arm64/boot/dts/apm/apm-storm.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * dts file for AppliedMicro (APM) X-Gene Storm SOC
   4  *
   5  * Copyright (C) 2013, Applied Micro Circuits Corporation
   6  */
   7
   8 / {
   9         compatible = "apm,xgene-storm";
  10         interrupt-parent = <&gic>;
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         cpus {
  15                 #address-cells = <2>;
  16                 #size-cells = <0>;
  17
  18                 cpu@0 {
  19                         device_type = "cpu";
  20                         compatible = "apm,potenza";
  21                         reg = <0x0 0x000>;
  22                         enable-method = "spin-table";
  23                         cpu-release-addr = <0x1 0x0000fff8>;
  24                         next-level-cache = <&xgene_L2_0>;
  25                 };
  26                 cpu@1 {
  27                         device_type = "cpu";
  28                         compatible = "apm,potenza";
  29                         reg = <0x0 0x001>;
  30                         enable-method = "spin-table";
  31                         cpu-release-addr = <0x1 0x0000fff8>;
  32                         next-level-cache = <&xgene_L2_0>;
  33                 };
  34                 cpu@100 {
  35                         device_type = "cpu";
  36                         compatible = "apm,potenza";
  37                         reg = <0x0 0x100>;
  38                         enable-method = "spin-table";
  39                         cpu-release-addr = <0x1 0x0000fff8>;
  40                         next-level-cache = <&xgene_L2_1>;
  41                 };
  42                 cpu@101 {
  43                         device_type = "cpu";
  44                         compatible = "apm,potenza";
  45                         reg = <0x0 0x101>;
  46                         enable-method = "spin-table";
  47                         cpu-release-addr = <0x1 0x0000fff8>;
  48                         next-level-cache = <&xgene_L2_1>;
  49                 };
  50                 cpu@200 {
  51                         device_type = "cpu";
  52                         compatible = "apm,potenza";
  53                         reg = <0x0 0x200>;
  54                         enable-method = "spin-table";
  55                         cpu-release-addr = <0x1 0x0000fff8>;
  56                         next-level-cache = <&xgene_L2_2>;
  57                 };
  58                 cpu@201 {
  59                         device_type = "cpu";
  60                         compatible = "apm,potenza";
  61                         reg = <0x0 0x201>;
  62                         enable-method = "spin-table";
  63                         cpu-release-addr = <0x1 0x0000fff8>;
  64                         next-level-cache = <&xgene_L2_2>;
  65                 };
  66                 cpu@300 {
  67                         device_type = "cpu";
  68                         compatible = "apm,potenza";
  69                         reg = <0x0 0x300>;
  70                         enable-method = "spin-table";
  71                         cpu-release-addr = <0x1 0x0000fff8>;
  72                         next-level-cache = <&xgene_L2_3>;
  73                 };
  74                 cpu@301 {
  75                         device_type = "cpu";
  76                         compatible = "apm,potenza";
  77                         reg = <0x0 0x301>;
  78                         enable-method = "spin-table";
  79                         cpu-release-addr = <0x1 0x0000fff8>;
  80                         next-level-cache = <&xgene_L2_3>;
  81                 };
  82                 xgene_L2_0: l2-cache-0 {
  83                         compatible = "cache";
  84                 };
  85                 xgene_L2_1: l2-cache-1 {
  86                         compatible = "cache";
  87                 };
  88                 xgene_L2_2: l2-cache-2 {
  89                         compatible = "cache";
  90                 };
  91                 xgene_L2_3: l2-cache-3 {
  92                         compatible = "cache";
  93                 };
  94         };
  95
  96         gic: interrupt-controller@78010000 {
  97                 compatible = "arm,cortex-a15-gic";
  98                 #interrupt-cells = <3>;
  99                 interrupt-controller;
 100                 reg = <0x0 0x78010000 0x0 0x1000>,      /* GIC Dist */
 101                       <0x0 0x78020000 0x0 0x1000>,      /* GIC CPU */
 102                       <0x0 0x78040000 0x0 0x2000>,      /* GIC VCPU Control */
 103                       <0x0 0x78060000 0x0 0x2000>;      /* GIC VCPU */
 104                 interrupts = <1 9 0xf04>;       /* GIC Maintenence IRQ */
 105         };
 106
 107         timer {
 108                 compatible = "arm,armv8-timer";
 109                 interrupts = <1 0 0xff08>,      /* Secure Phys IRQ */
 110                              <1 13 0xff08>,     /* Non-secure Phys IRQ */
 111                              <1 14 0xff08>,     /* Virt IRQ */
 112                              <1 15 0xff08>;     /* Hyp IRQ */
 113                 clock-frequency = <50000000>;
 114         };
 115
 116         pmu {
 117                 compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
 118                 interrupts = <1 12 0xff04>;
 119         };
 120
 121         soc {
 122                 compatible = "simple-bus";
 123                 #address-cells = <2>;
 124                 #size-cells = <2>;
 125                 ranges;
 126                 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
 127
 128                 clocks {
 129                         #address-cells = <2>;
 130                         #size-cells = <2>;
 131                         ranges;
 132                         refclk: refclk {
 133                                 compatible = "fixed-clock";
 134                                 #clock-cells = <1>;
 135                                 clock-frequency = <100000000>;
 136                                 clock-output-names = "refclk";
 137                         };
 138
 139                         pcppll: pcppll@17000100 {
 140                                 compatible = "apm,xgene-pcppll-clock";
 141                                 #clock-cells = <1>;
 142                                 clocks = <&refclk 0>;
 143                                 clock-names = "pcppll";
 144                                 reg = <0x0 0x17000100 0x0 0x1000>;
 145                                 clock-output-names = "pcppll";
 146                                 type = <0>;
 147                         };
 148
 149                         socpll: socpll@17000120 {
 150                                 compatible = "apm,xgene-socpll-clock";
 151                                 #clock-cells = <1>;
 152                                 clocks = <&refclk 0>;
 153                                 clock-names = "socpll";
 154                                 reg = <0x0 0x17000120 0x0 0x1000>;
 155                                 clock-output-names = "socpll";
 156                                 type = <1>;
 157                         };
 158
 159                         socplldiv2: socplldiv2  {
 160                                 compatible = "fixed-factor-clock";
 161                                 #clock-cells = <1>;
 162                                 clocks = <&socpll 0>;
 163                                 clock-names = "socplldiv2";
 164                                 clock-mult = <1>;
 165                                 clock-div = <2>;
 166                                 clock-output-names = "socplldiv2";
 167                         };
 168
 169                         ahbclk: ahbclk@17000000 {
 170                                 compatible = "apm,xgene-device-clock";
 171                                 #clock-cells = <1>;
 172                                 clocks = <&socplldiv2 0>;
 173                                 reg = <0x0 0x17000000 0x0 0x2000>;
 174                                 reg-names = "div-reg";
 175                                 divider-offset = <0x164>;
 176                                 divider-width = <0x5>;
 177                                 divider-shift = <0x0>;
 178                                 clock-output-names = "ahbclk";
 179                         };
 180
 181                         sdioclk: sdioclk@1f2ac000 {
 182                                 compatible = "apm,xgene-device-clock";
 183                                 #clock-cells = <1>;
 184                                 clocks = <&socplldiv2 0>;
 185                                 reg = <0x0 0x1f2ac000 0x0 0x1000
 186                                         0x0 0x17000000 0x0 0x2000>;
 187                                 reg-names = "csr-reg", "div-reg";
 188                                 csr-offset = <0x0>;
 189                                 csr-mask = <0x2>;
 190                                 enable-offset = <0x8>;
 191                                 enable-mask = <0x2>;
 192                                 divider-offset = <0x178>;
 193                                 divider-width = <0x8>;
 194                                 divider-shift = <0x0>;
 195                                 clock-output-names = "sdioclk";
 196                         };
 197
 198                         ethclk: ethclk {
 199                                 compatible = "apm,xgene-device-clock";
 200                                 #clock-cells = <1>;
 201                                 clocks = <&socplldiv2 0>;
 202                                 clock-names = "ethclk";
 203                                 reg = <0x0 0x17000000 0x0 0x1000>;
 204                                 reg-names = "div-reg";
 205                                 divider-offset = <0x238>;
 206                                 divider-width = <0x9>;
 207                                 divider-shift = <0x0>;
 208                                 clock-output-names = "ethclk";
 209                         };
 210
 211                         menetclk: menetclk {
 212                                 compatible = "apm,xgene-device-clock";
 213                                 #clock-cells = <1>;
 214                                 clocks = <&ethclk 0>;
 215                                 reg = <0x0 0x1702c000 0x0 0x1000>;
 216                                 reg-names = "csr-reg";
 217                                 clock-output-names = "menetclk";
 218                         };
 219
 220                         sge0clk: sge0clk@1f21c000 {
 221                                 compatible = "apm,xgene-device-clock";
 222                                 #clock-cells = <1>;
 223                                 clocks = <&socplldiv2 0>;
 224                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 225                                 reg-names = "csr-reg";
 226                                 csr-mask = <0xa>;
 227                                 enable-mask = <0xf>;
 228                                 clock-output-names = "sge0clk";
 229                         };
 230
 231                         xge0clk: xge0clk@1f61c000 {
 232                                 compatible = "apm,xgene-device-clock";
 233                                 #clock-cells = <1>;
 234                                 clocks = <&socplldiv2 0>;
 235                                 reg = <0x0 0x1f61c000 0x0 0x1000>;
 236                                 reg-names = "csr-reg";
 237                                 csr-mask = <0x3>;
 238                                 clock-output-names = "xge0clk";
 239                         };
 240
 241                         xge1clk: xge1clk@1f62c000 {
 242                                 compatible = "apm,xgene-device-clock";
 243                                 status = "disabled";
 244                                 #clock-cells = <1>;
 245                                 clocks = <&socplldiv2 0>;
 246                                 reg = <0x0 0x1f62c000 0x0 0x1000>;
 247                                 reg-names = "csr-reg";
 248                                 csr-mask = <0x3>;
 249                                 clock-output-names = "xge1clk";
 250                         };
 251
 252                         sataphy1clk: sataphy1clk@1f21c000 {
 253                                 compatible = "apm,xgene-device-clock";
 254                                 #clock-cells = <1>;
 255                                 clocks = <&socplldiv2 0>;
 256                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 257                                 reg-names = "csr-reg";
 258                                 clock-output-names = "sataphy1clk";
 259                                 status = "disabled";
 260                                 csr-offset = <0x4>;
 261                                 csr-mask = <0x00>;
 262                                 enable-offset = <0x0>;
 263                                 enable-mask = <0x06>;
 264                         };
 265
 266                         sataphy2clk: sataphy1clk@1f22c000 {
 267                                 compatible = "apm,xgene-device-clock";
 268                                 #clock-cells = <1>;
 269                                 clocks = <&socplldiv2 0>;
 270                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 271                                 reg-names = "csr-reg";
 272                                 clock-output-names = "sataphy2clk";
 273                                 status = "ok";
 274                                 csr-offset = <0x4>;
 275                                 csr-mask = <0x3a>;
 276                                 enable-offset = <0x0>;
 277                                 enable-mask = <0x06>;
 278                         };
 279
 280                         sataphy3clk: sataphy1clk@1f23c000 {
 281                                 compatible = "apm,xgene-device-clock";
 282                                 #clock-cells = <1>;
 283                                 clocks = <&socplldiv2 0>;
 284                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 285                                 reg-names = "csr-reg";
 286                                 clock-output-names = "sataphy3clk";
 287                                 status = "ok";
 288                                 csr-offset = <0x4>;
 289                                 csr-mask = <0x3a>;
 290                                 enable-offset = <0x0>;
 291                                 enable-mask = <0x06>;
 292                         };
 293
 294                         sata01clk: sata01clk@1f21c000 {
 295                                 compatible = "apm,xgene-device-clock";
 296                                 #clock-cells = <1>;
 297                                 clocks = <&socplldiv2 0>;
 298                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 299                                 reg-names = "csr-reg";
 300                                 clock-output-names = "sata01clk";
 301                                 csr-offset = <0x4>;
 302                                 csr-mask = <0x05>;
 303                                 enable-offset = <0x0>;
 304                                 enable-mask = <0x39>;
 305                         };
 306
 307                         sata23clk: sata23clk@1f22c000 {
 308                                 compatible = "apm,xgene-device-clock";
 309                                 #clock-cells = <1>;
 310                                 clocks = <&socplldiv2 0>;
 311                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 312                                 reg-names = "csr-reg";
 313                                 clock-output-names = "sata23clk";
 314                                 csr-offset = <0x4>;
 315                                 csr-mask = <0x05>;
 316                                 enable-offset = <0x0>;
 317                                 enable-mask = <0x39>;
 318                         };
 319
 320                         sata45clk: sata45clk@1f23c000 {
 321                                 compatible = "apm,xgene-device-clock";
 322                                 #clock-cells = <1>;
 323                                 clocks = <&socplldiv2 0>;
 324                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 325                                 reg-names = "csr-reg";
 326                                 clock-output-names = "sata45clk";
 327                                 csr-offset = <0x4>;
 328                                 csr-mask = <0x05>;
 329                                 enable-offset = <0x0>;
 330                                 enable-mask = <0x39>;
 331                         };
 332
 333                         rtcclk: rtcclk@17000000 {
 334                                 compatible = "apm,xgene-device-clock";
 335                                 #clock-cells = <1>;
 336                                 clocks = <&socplldiv2 0>;
 337                                 reg = <0x0 0x17000000 0x0 0x2000>;
 338                                 reg-names = "csr-reg";
 339                                 csr-offset = <0xc>;
 340                                 csr-mask = <0x2>;
 341                                 enable-offset = <0x10>;
 342                                 enable-mask = <0x2>;
 343                                 clock-output-names = "rtcclk";
 344                         };
 345
 346                         rngpkaclk: rngpkaclk@17000000 {
 347                                 compatible = "apm,xgene-device-clock";
 348                                 #clock-cells = <1>;
 349                                 clocks = <&socplldiv2 0>;
 350                                 reg = <0x0 0x17000000 0x0 0x2000>;
 351                                 reg-names = "csr-reg";
 352                                 csr-offset = <0xc>;
 353                                 csr-mask = <0x10>;
 354                                 enable-offset = <0x10>;
 355                                 enable-mask = <0x10>;
 356                                 clock-output-names = "rngpkaclk";
 357                         };
 358
 359                         pcie0clk: pcie0clk@1f2bc000 {
 360                                 status = "disabled";
 361                                 compatible = "apm,xgene-device-clock";
 362                                 #clock-cells = <1>;
 363                                 clocks = <&socplldiv2 0>;
 364                                 reg = <0x0 0x1f2bc000 0x0 0x1000>;
 365                                 reg-names = "csr-reg";
 366                                 clock-output-names = "pcie0clk";
 367                         };
 368
 369                         pcie1clk: pcie1clk@1f2cc000 {
 370                                 status = "disabled";
 371                                 compatible = "apm,xgene-device-clock";
 372                                 #clock-cells = <1>;
 373                                 clocks = <&socplldiv2 0>;
 374                                 reg = <0x0 0x1f2cc000 0x0 0x1000>;
 375                                 reg-names = "csr-reg";
 376                                 clock-output-names = "pcie1clk";
 377                         };
 378
 379                         pcie2clk: pcie2clk@1f2dc000 {
 380                                 status = "disabled";
 381                                 compatible = "apm,xgene-device-clock";
 382                                 #clock-cells = <1>;
 383                                 clocks = <&socplldiv2 0>;
 384                                 reg = <0x0 0x1f2dc000 0x0 0x1000>;
 385                                 reg-names = "csr-reg";
 386                                 clock-output-names = "pcie2clk";
 387                         };
 388
 389                         pcie3clk: pcie3clk@1f50c000 {
 390                                 status = "disabled";
 391                                 compatible = "apm,xgene-device-clock";
 392                                 #clock-cells = <1>;
 393                                 clocks = <&socplldiv2 0>;
 394                                 reg = <0x0 0x1f50c000 0x0 0x1000>;
 395                                 reg-names = "csr-reg";
 396                                 clock-output-names = "pcie3clk";
 397                         };
 398
 399                         pcie4clk: pcie4clk@1f51c000 {
 400                                 status = "disabled";
 401                                 compatible = "apm,xgene-device-clock";
 402                                 #clock-cells = <1>;
 403                                 clocks = <&socplldiv2 0>;
 404                                 reg = <0x0 0x1f51c000 0x0 0x1000>;
 405                                 reg-names = "csr-reg";
 406                                 clock-output-names = "pcie4clk";
 407                         };
 408
 409                         dmaclk: dmaclk@1f27c000 {
 410                                 compatible = "apm,xgene-device-clock";
 411                                 #clock-cells = <1>;
 412                                 clocks = <&socplldiv2 0>;
 413                                 reg = <0x0 0x1f27c000 0x0 0x1000>;
 414                                 reg-names = "csr-reg";
 415                                 clock-output-names = "dmaclk";
 416                         };
 417                 };
 418
 419                 msi: msi@79000000 {
 420                         compatible = "apm,xgene1-msi";
 421                         msi-controller;
 422                         reg = <0x00 0x79000000 0x0 0x900000>;
 423                         interrupts = <  0x0 0x10 0x4
 424                                         0x0 0x11 0x4
 425                                         0x0 0x12 0x4
 426                                         0x0 0x13 0x4
 427                                         0x0 0x14 0x4
 428                                         0x0 0x15 0x4
 429                                         0x0 0x16 0x4
 430                                         0x0 0x17 0x4
 431                                         0x0 0x18 0x4
 432                                         0x0 0x19 0x4
 433                                         0x0 0x1a 0x4
 434                                         0x0 0x1b 0x4
 435                                         0x0 0x1c 0x4
 436                                         0x0 0x1d 0x4
 437                                         0x0 0x1e 0x4
 438                                         0x0 0x1f 0x4>;
 439                 };
 440
 441                 scu: system-clk-controller@17000000 {
 442                         compatible = "apm,xgene-scu","syscon";
 443                         reg = <0x0 0x17000000 0x0 0x400>;
 444                 };
 445
 446                 reboot: reboot@17000014 {
 447                         compatible = "syscon-reboot";
 448                         regmap = <&scu>;
 449                         offset = <0x14>;
 450                         mask = <0x1>;
 451                 };
 452
 453                 csw: csw@7e200000 {
 454                         compatible = "apm,xgene-csw", "syscon";
 455                         reg = <0x0 0x7e200000 0x0 0x1000>;
 456                 };
 457
 458                 mcba: mcba@7e700000 {
 459                         compatible = "apm,xgene-mcb", "syscon";
 460                         reg = <0x0 0x7e700000 0x0 0x1000>;
 461                 };
 462
 463                 mcbb: mcbb@7e720000 {
 464                         compatible = "apm,xgene-mcb", "syscon";
 465                         reg = <0x0 0x7e720000 0x0 0x1000>;
 466                 };
 467
 468                 efuse: efuse@1054a000 {
 469                         compatible = "apm,xgene-efuse", "syscon";
 470                         reg = <0x0 0x1054a000 0x0 0x20>;
 471                 };
 472
 473                 rb: rb@7e000000 {
 474                         compatible = "apm,xgene-rb", "syscon";
 475                         reg = <0x0 0x7e000000 0x0 0x10>;
 476                 };
 477
 478                 edac@78800000 {
 479                         compatible = "apm,xgene-edac";
 480                         #address-cells = <2>;
 481                         #size-cells = <2>;
 482                         ranges;
 483                         regmap-csw = <&csw>;
 484                         regmap-mcba = <&mcba>;
 485                         regmap-mcbb = <&mcbb>;
 486                         regmap-efuse = <&efuse>;
 487                         regmap-rb = <&rb>;
 488                         reg = <0x0 0x78800000 0x0 0x100>;
 489                         interrupts = <0x0 0x20 0x4>,
 490                                      <0x0 0x21 0x4>,
 491                                      <0x0 0x27 0x4>;
 492
 493                         edacmc@7e800000 {
 494                                 compatible = "apm,xgene-edac-mc";
 495                                 reg = <0x0 0x7e800000 0x0 0x1000>;
 496                                 memory-controller = <0>;
 497                         };
 498
 499                         edacmc@7e840000 {
 500                                 compatible = "apm,xgene-edac-mc";
 501                                 reg = <0x0 0x7e840000 0x0 0x1000>;
 502                                 memory-controller = <1>;
 503                         };
 504
 505                         edacmc@7e880000 {
 506                                 compatible = "apm,xgene-edac-mc";
 507                                 reg = <0x0 0x7e880000 0x0 0x1000>;
 508                                 memory-controller = <2>;
 509                         };
 510
 511                         edacmc@7e8c0000 {
 512                                 compatible = "apm,xgene-edac-mc";
 513                                 reg = <0x0 0x7e8c0000 0x0 0x1000>;
 514                                 memory-controller = <3>;
 515                         };
 516
 517                         edacpmd@7c000000 {
 518                                 compatible = "apm,xgene-edac-pmd";
 519                                 reg = <0x0 0x7c000000 0x0 0x200000>;
 520                                 pmd-controller = <0>;
 521                         };
 522
 523                         edacpmd@7c200000 {
 524                                 compatible = "apm,xgene-edac-pmd";
 525                                 reg = <0x0 0x7c200000 0x0 0x200000>;
 526                                 pmd-controller = <1>;
 527                         };
 528
 529                         edacpmd@7c400000 {
 530                                 compatible = "apm,xgene-edac-pmd";
 531                                 reg = <0x0 0x7c400000 0x0 0x200000>;
 532                                 pmd-controller = <2>;
 533                         };
 534
 535                         edacpmd@7c600000 {
 536                                 compatible = "apm,xgene-edac-pmd";
 537                                 reg = <0x0 0x7c600000 0x0 0x200000>;
 538                                 pmd-controller = <3>;
 539                         };
 540
 541                         edacl3@7e600000 {
 542                                 compatible = "apm,xgene-edac-l3";
 543                                 reg = <0x0 0x7e600000 0x0 0x1000>;
 544                         };
 545
 546                         edacsoc@7e930000 {
 547                                 compatible = "apm,xgene-edac-soc-v1";
 548                                 reg = <0x0 0x7e930000 0x0 0x1000>;
 549                         };
 550                 };
 551
 552                 pmu: pmu@78810000 {
 553                         compatible = "apm,xgene-pmu-v2";
 554                         #address-cells = <2>;
 555                         #size-cells = <2>;
 556                         ranges;
 557                         regmap-csw = <&csw>;
 558                         regmap-mcba = <&mcba>;
 559                         regmap-mcbb = <&mcbb>;
 560                         reg = <0x0 0x78810000 0x0 0x1000>;
 561                         interrupts = <0x0 0x22 0x4>;
 562
 563                         pmul3c@7e610000 {
 564                                 compatible = "apm,xgene-pmu-l3c";
 565                                 reg = <0x0 0x7e610000 0x0 0x1000>;
 566                         };
 567
 568                         pmuiob@7e940000 {
 569                                 compatible = "apm,xgene-pmu-iob";
 570                                 reg = <0x0 0x7e940000 0x0 0x1000>;
 571                         };
 572
 573                         pmucmcb@7e710000 {
 574                                 compatible = "apm,xgene-pmu-mcb";
 575                                 reg = <0x0 0x7e710000 0x0 0x1000>;
 576                                 enable-bit-index = <0>;
 577                         };
 578
 579                         pmucmcb@7e730000 {
 580                                 compatible = "apm,xgene-pmu-mcb";
 581                                 reg = <0x0 0x7e730000 0x0 0x1000>;
 582                                 enable-bit-index = <1>;
 583                         };
 584
 585                         pmucmc@7e810000 {
 586                                 compatible = "apm,xgene-pmu-mc";
 587                                 reg = <0x0 0x7e810000 0x0 0x1000>;
 588                                 enable-bit-index = <0>;
 589                         };
 590
 591                         pmucmc@7e850000 {
 592                                 compatible = "apm,xgene-pmu-mc";
 593                                 reg = <0x0 0x7e850000 0x0 0x1000>;
 594                                 enable-bit-index = <1>;
 595                         };
 596
 597                         pmucmc@7e890000 {
 598                                 compatible = "apm,xgene-pmu-mc";
 599                                 reg = <0x0 0x7e890000 0x0 0x1000>;
 600                                 enable-bit-index = <2>;
 601                         };
 602
 603                         pmucmc@7e8d0000 {
 604                                 compatible = "apm,xgene-pmu-mc";
 605                                 reg = <0x0 0x7e8d0000 0x0 0x1000>;
 606                                 enable-bit-index = <3>;
 607                         };
 608                 };
 609
 610                 pcie0: pcie@1f2b0000 {
 611                         status = "disabled";
 612                         device_type = "pci";
 613                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 614                         #interrupt-cells = <1>;
 615                         #size-cells = <2>;
 616                         #address-cells = <3>;
 617                         reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
 618                                 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 619                         reg-names = "csr", "cfg";
 620                         ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
 621                                   0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000   /* mem */
 622                                   0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
 623                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 624                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 625                         bus-range = <0x00 0xff>;
 626                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 627                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
 628                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
 629                                          0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4
 630                                          0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>;
 631                         dma-coherent;
 632                         clocks = <&pcie0clk 0>;
 633                         msi-parent = <&msi>;
 634                 };
 635
 636                 pcie1: pcie@1f2c0000 {
 637                         status = "disabled";
 638                         device_type = "pci";
 639                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 640                         #interrupt-cells = <1>;
 641                         #size-cells = <2>;
 642                         #address-cells = <3>;
 643                         reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
 644                                 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 645                         reg-names = "csr", "cfg";
 646                         ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
 647                                   0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000   /* mem */
 648                                   0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
 649                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 650                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 651                         bus-range = <0x00 0xff>;
 652                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 653                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
 654                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
 655                                          0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4
 656                                          0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>;
 657                         dma-coherent;
 658                         clocks = <&pcie1clk 0>;
 659                         msi-parent = <&msi>;
 660                 };
 661
 662                 pcie2: pcie@1f2d0000 {
 663                         status = "disabled";
 664                         device_type = "pci";
 665                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 666                         #interrupt-cells = <1>;
 667                         #size-cells = <2>;
 668                         #address-cells = <3>;
 669                         reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
 670                                  0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
 671                         reg-names = "csr", "cfg";
 672                         ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000   /* io  */
 673                                   0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000   /* mem */
 674                                   0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
 675                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 676                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 677                         bus-range = <0x00 0xff>;
 678                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 679                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
 680                                          0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
 681                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4
 682                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>;
 683                         dma-coherent;
 684                         clocks = <&pcie2clk 0>;
 685                         msi-parent = <&msi>;
 686                 };
 687
 688                 pcie3: pcie@1f500000 {
 689                         status = "disabled";
 690                         device_type = "pci";
 691                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 692                         #interrupt-cells = <1>;
 693                         #size-cells = <2>;
 694                         #address-cells = <3>;
 695                         reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
 696                                 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 697                         reg-names = "csr", "cfg";
 698                         ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io  */
 699                                   0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000   /* mem */
 700                                   0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
 701                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 702                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 703                         bus-range = <0x00 0xff>;
 704                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 705                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
 706                                          0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
 707                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4
 708                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>;
 709                         dma-coherent;
 710                         clocks = <&pcie3clk 0>;
 711                         msi-parent = <&msi>;
 712                 };
 713
 714                 pcie4: pcie@1f510000 {
 715                         status = "disabled";
 716                         device_type = "pci";
 717                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 718                         #interrupt-cells = <1>;
 719                         #size-cells = <2>;
 720                         #address-cells = <3>;
 721                         reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
 722                                 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
 723                         reg-names = "csr", "cfg";
 724                         ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io  */
 725                                   0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000   /* mem */
 726                                   0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
 727                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 728                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 729                         bus-range = <0x00 0xff>;
 730                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 731                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
 732                                          0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
 733                                          0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4
 734                                          0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>;
 735                         dma-coherent;
 736                         clocks = <&pcie4clk 0>;
 737                         msi-parent = <&msi>;
 738                 };
 739
 740                 mailbox: mailbox@10540000 {
 741                         compatible = "apm,xgene-slimpro-mbox";
 742                         reg = <0x0 0x10540000 0x0 0xa000>;
 743                         #mbox-cells = <1>;
 744                         interrupts =    <0x0 0x0 0x4>,
 745                                         <0x0 0x1 0x4>,
 746                                         <0x0 0x2 0x4>,
 747                                         <0x0 0x3 0x4>,
 748                                         <0x0 0x4 0x4>,
 749                                         <0x0 0x5 0x4>,
 750                                         <0x0 0x6 0x4>,
 751                                         <0x0 0x7 0x4>;
 752                 };
 753
 754                 i2cslimpro {
 755                         compatible = "apm,xgene-slimpro-i2c";
 756                         mboxes = <&mailbox 0>;
 757                 };
 758
 759                 hwmonslimpro {
 760                         compatible = "apm,xgene-slimpro-hwmon";
 761                         mboxes = <&mailbox 7>;
 762                 };
 763
 764                 serial0: serial@1c020000 {
 765                         status = "disabled";
 766                         device_type = "serial";
 767                         compatible = "ns16550a";
 768                         reg = <0 0x1c020000 0x0 0x1000>;
 769                         reg-shift = <2>;
 770                         clock-frequency = <10000000>; /* Updated by bootloader */
 771                         interrupt-parent = <&gic>;
 772                         interrupts = <0x0 0x4c 0x4>;
 773                 };
 774
 775                 serial1: serial@1c021000 {
 776                         status = "disabled";
 777                         device_type = "serial";
 778                         compatible = "ns16550a";
 779                         reg = <0 0x1c021000 0x0 0x1000>;
 780                         reg-shift = <2>;
 781                         clock-frequency = <10000000>; /* Updated by bootloader */
 782                         interrupt-parent = <&gic>;
 783                         interrupts = <0x0 0x4d 0x4>;
 784                 };
 785
 786                 serial2: serial@1c022000 {
 787                         status = "disabled";
 788                         device_type = "serial";
 789                         compatible = "ns16550a";
 790                         reg = <0 0x1c022000 0x0 0x1000>;
 791                         reg-shift = <2>;
 792                         clock-frequency = <10000000>; /* Updated by bootloader */
 793                         interrupt-parent = <&gic>;
 794                         interrupts = <0x0 0x4e 0x4>;
 795                 };
 796
 797                 serial3: serial@1c023000 {
 798                         status = "disabled";
 799                         device_type = "serial";
 800                         compatible = "ns16550a";
 801                         reg = <0 0x1c023000 0x0 0x1000>;
 802                         reg-shift = <2>;
 803                         clock-frequency = <10000000>; /* Updated by bootloader */
 804                         interrupt-parent = <&gic>;
 805                         interrupts = <0x0 0x4f 0x4>;
 806                 };
 807
 808                 mmc0: mmc@1c000000 {
 809                         compatible = "arasan,sdhci-4.9a";
 810                         reg = <0x0 0x1c000000 0x0 0x100>;
 811                         interrupts = <0x0 0x49 0x4>;
 812                         dma-coherent;
 813                         no-1-8-v;
 814                         clock-names = "clk_xin", "clk_ahb";
 815                         clocks = <&sdioclk 0>, <&ahbclk 0>;
 816                 };
 817
 818                 gfcgpio: gpio0@1701c000 {
 819                         compatible = "apm,xgene-gpio";
 820                         reg = <0x0 0x1701c000 0x0 0x40>;
 821                         gpio-controller;
 822                         #gpio-cells = <2>;
 823                 };
 824
 825                 dwgpio: gpio@1c024000 {
 826                         compatible = "snps,dw-apb-gpio";
 827                         reg = <0x0 0x1c024000 0x0 0x1000>;
 828                         reg-io-width = <4>;
 829                         #address-cells = <1>;
 830                         #size-cells = <0>;
 831
 832                         porta: gpio-controller@0 {
 833                                 compatible = "snps,dw-apb-gpio-port";
 834                                 gpio-controller;
 835                                 snps,nr-gpios = <32>;
 836                                 reg = <0>;
 837                         };
 838                 };
 839
 840                 i2c0: i2c@10512000 {
 841                         status = "disabled";
 842                         #address-cells = <1>;
 843                         #size-cells = <0>;
 844                         compatible = "snps,designware-i2c";
 845                         reg = <0x0 0x10512000 0x0 0x1000>;
 846                         interrupts = <0 0x44 0x4>;
 847                         #clock-cells = <1>;
 848                         clocks = <&ahbclk 0>;
 849                         bus_num = <0>;
 850                 };
 851
 852                 phy1: phy@1f21a000 {
 853                         compatible = "apm,xgene-phy";
 854                         reg = <0x0 0x1f21a000 0x0 0x100>;
 855                         #phy-cells = <1>;
 856                         clocks = <&sataphy1clk 0>;
 857                         status = "disabled";
 858                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 859                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 860                 };
 861
 862                 phy2: phy@1f22a000 {
 863                         compatible = "apm,xgene-phy";
 864                         reg = <0x0 0x1f22a000 0x0 0x100>;
 865                         #phy-cells = <1>;
 866                         clocks = <&sataphy2clk 0>;
 867                         status = "ok";
 868                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 869                         apm,tx-eye-tuning = <1 10 10 2 10 10>;
 870                 };
 871
 872                 phy3: phy@1f23a000 {
 873                         compatible = "apm,xgene-phy";
 874                         reg = <0x0 0x1f23a000 0x0 0x100>;
 875                         #phy-cells = <1>;
 876                         clocks = <&sataphy3clk 0>;
 877                         status = "ok";
 878                         apm,tx-boost-gain = <31 31 31 31 31 31>;
 879                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 880                 };
 881
 882                 sata1: sata@1a000000 {
 883                         compatible = "apm,xgene-ahci";
 884                         reg = <0x0 0x1a000000 0x0 0x1000>,
 885                               <0x0 0x1f210000 0x0 0x1000>,
 886                               <0x0 0x1f21d000 0x0 0x1000>,
 887                               <0x0 0x1f21e000 0x0 0x1000>,
 888                               <0x0 0x1f217000 0x0 0x1000>;
 889                         interrupts = <0x0 0x86 0x4>;
 890                         dma-coherent;
 891                         status = "disabled";
 892                         clocks = <&sata01clk 0>;
 893                         phys = <&phy1 0>;
 894                         phy-names = "sata-phy";
 895                 };
 896
 897                 sata2: sata@1a400000 {
 898                         compatible = "apm,xgene-ahci";
 899                         reg = <0x0 0x1a400000 0x0 0x1000>,
 900                               <0x0 0x1f220000 0x0 0x1000>,
 901                               <0x0 0x1f22d000 0x0 0x1000>,
 902                               <0x0 0x1f22e000 0x0 0x1000>,
 903                               <0x0 0x1f227000 0x0 0x1000>;
 904                         interrupts = <0x0 0x87 0x4>;
 905                         dma-coherent;
 906                         status = "ok";
 907                         clocks = <&sata23clk 0>;
 908                         phys = <&phy2 0>;
 909                         phy-names = "sata-phy";
 910                 };
 911
 912                 sata3: sata@1a800000 {
 913                         compatible = "apm,xgene-ahci";
 914                         reg = <0x0 0x1a800000 0x0 0x1000>,
 915                               <0x0 0x1f230000 0x0 0x1000>,
 916                               <0x0 0x1f23d000 0x0 0x1000>,
 917                               <0x0 0x1f23e000 0x0 0x1000>;
 918                         interrupts = <0x0 0x88 0x4>;
 919                         dma-coherent;
 920                         status = "ok";
 921                         clocks = <&sata45clk 0>;
 922                         phys = <&phy3 0>;
 923                         phy-names = "sata-phy";
 924                 };
 925
 926                 /* Do not change dwusb name, coded for backward compatibility */
 927                 usb0: dwusb@19000000 {
 928                         status = "disabled";
 929                         compatible = "snps,dwc3";
 930                         reg =  <0x0 0x19000000 0x0 0x100000>;
 931                         interrupts = <0x0 0x89 0x4>;
 932                         dma-coherent;
 933                         dr_mode = "host";
 934                 };
 935
 936                 usb1: dwusb@19800000 {
 937                         status = "disabled";
 938                         compatible = "snps,dwc3";
 939                         reg =  <0x0 0x19800000 0x0 0x100000>;
 940                         interrupts = <0x0 0x8a 0x4>;
 941                         dma-coherent;
 942                         dr_mode = "host";
 943                 };
 944
 945                 sbgpio: gpio@17001000{
 946                         compatible = "apm,xgene-gpio-sb";
 947                         reg = <0x0 0x17001000 0x0 0x400>;
 948                         #gpio-cells = <2>;
 949                         gpio-controller;
 950                         interrupts =    <0x0 0x28 0x1>,
 951                                         <0x0 0x29 0x1>,
 952                                         <0x0 0x2a 0x1>,
 953                                         <0x0 0x2b 0x1>,
 954                                         <0x0 0x2c 0x1>,
 955                                         <0x0 0x2d 0x1>;
 956                         interrupt-parent = <&gic>;
 957                         #interrupt-cells = <2>;
 958                         interrupt-controller;
 959                 };
 960
 961                 rtc: rtc@10510000 {
 962                         compatible = "apm,xgene-rtc";
 963                         reg = <0x0 0x10510000 0x0 0x400>;
 964                         interrupts = <0x0 0x46 0x4>;
 965                         #clock-cells = <1>;
 966                         clocks = <&rtcclk 0>;
 967                 };
 968
 969                 mdio: mdio@17020000 {
 970                         compatible = "apm,xgene-mdio-rgmii";
 971                         #address-cells = <1>;
 972                         #size-cells = <0>;
 973                         reg = <0x0 0x17020000 0x0 0xd100>;
 974                         clocks = <&menetclk 0>;
 975                 };
 976
 977                 menet: ethernet@17020000 {
 978                         compatible = "apm,xgene-enet";
 979                         status = "disabled";
 980                         reg = <0x0 0x17020000 0x0 0xd100>,
 981                               <0x0 0x17030000 0x0 0xc300>,
 982                               <0x0 0x10000000 0x0 0x200>;
 983                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 984                         interrupts = <0x0 0x3c 0x4>;
 985                         dma-coherent;
 986                         clocks = <&menetclk 0>;
 987                         /* mac address will be overwritten by the bootloader */
 988                         local-mac-address = [00 00 00 00 00 00];
 989                         phy-connection-type = "rgmii";
 990                         phy-handle = <&menetphy>,<&menet0phy>;
 991                         mdio {
 992                                 compatible = "apm,xgene-mdio";
 993                                 #address-cells = <1>;
 994                                 #size-cells = <0>;
 995                                 menetphy: menetphy@3 {
 996                                         compatible = "ethernet-phy-id001c.c915";
 997                                         reg = <0x3>;
 998                                 };
 999
1000                         };
1001                 };
1002
1003                 sgenet0: ethernet@1f210000 {
1004                         compatible = "apm,xgene1-sgenet";
1005                         status = "disabled";
1006                         reg = <0x0 0x1f210000 0x0 0xd100>,
1007                               <0x0 0x1f200000 0x0 0xc300>,
1008                               <0x0 0x1b000000 0x0 0x200>;
1009                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
1010                         interrupts = <0x0 0xa0 0x4>,
1011                                      <0x0 0xa1 0x4>;
1012                         dma-coherent;
1013                         clocks = <&sge0clk 0>;
1014                         local-mac-address = [00 00 00 00 00 00];
1015                         phy-connection-type = "sgmii";
1016                         phy-handle = <&sgenet0phy>;
1017                 };
1018
1019                 sgenet1: ethernet@1f210030 {
1020                         compatible = "apm,xgene1-sgenet";
1021                         status = "disabled";
1022                         reg = <0x0 0x1f210030 0x0 0xd100>,
1023                               <0x0 0x1f200000 0x0 0xc300>,
1024                               <0x0 0x1b000000 0x0 0x8000>;
1025                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
1026                         interrupts = <0x0 0xac 0x4>,
1027                                      <0x0 0xad 0x4>;
1028                         port-id = <1>;
1029                         dma-coherent;
1030                         local-mac-address = [00 00 00 00 00 00];
1031                         phy-connection-type = "sgmii";
1032                         phy-handle = <&sgenet1phy>;
1033                 };
1034
1035                 xgenet: ethernet@1f610000 {
1036                         compatible = "apm,xgene1-xgenet";
1037                         status = "disabled";
1038                         reg = <0x0 0x1f610000 0x0 0xd100>,
1039                               <0x0 0x1f600000 0x0 0xc300>,
1040                               <0x0 0x18000000 0x0 0x200>;
1041                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
1042                         interrupts = <0x0 0x60 0x4>,
1043                                      <0x0 0x61 0x4>,
1044                                      <0x0 0x62 0x4>,
1045                                      <0x0 0x63 0x4>,
1046                                      <0x0 0x64 0x4>,
1047                                      <0x0 0x65 0x4>,
1048                                      <0x0 0x66 0x4>,
1049                                      <0x0 0x67 0x4>;
1050                         channel = <0>;
1051                         dma-coherent;
1052                         clocks = <&xge0clk 0>;
1053                         /* mac address will be overwritten by the bootloader */
1054                         local-mac-address = [00 00 00 00 00 00];
1055                         phy-connection-type = "xgmii";
1056                 };
1057
1058                 xgenet1: ethernet@1f620000 {
1059                         compatible = "apm,xgene1-xgenet";
1060                         status = "disabled";
1061                         reg = <0x0 0x1f620000 0x0 0xd100>,
1062                               <0x0 0x1f600000 0x0 0xc300>,
1063                               <0x0 0x18000000 0x0 0x8000>;
1064                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
1065                         interrupts = <0x0 0x6c 0x4>,
1066                                      <0x0 0x6d 0x4>;
1067                         port-id = <1>;
1068                         dma-coherent;
1069                         clocks = <&xge1clk 0>;
1070                         /* mac address will be overwritten by the bootloader */
1071                         local-mac-address = [00 00 00 00 00 00];
1072                         phy-connection-type = "xgmii";
1073                 };
1074
1075                 rng: rng@10520000 {
1076                         compatible = "apm,xgene-rng";
1077                         reg = <0x0 0x10520000 0x0 0x100>;
1078                         interrupts = <0x0 0x41 0x4>;
1079                         clocks = <&rngpkaclk 0>;
1080                 };
1081
1082                 dma: dma@1f270000 {
1083                         compatible = "apm,xgene-storm-dma";
1084                         device_type = "dma";
1085                         reg = <0x0 0x1f270000 0x0 0x10000>,
1086                               <0x0 0x1f200000 0x0 0x10000>,
1087                               <0x0 0x1b000000 0x0 0x400000>,
1088                               <0x0 0x1054a000 0x0 0x100>;
1089                         interrupts = <0x0 0x82 0x4>,
1090                                      <0x0 0xb8 0x4>,
1091                                      <0x0 0xb9 0x4>,
1092                                      <0x0 0xba 0x4>,
1093                                      <0x0 0xbb 0x4>;
1094                         dma-coherent;
1095                         clocks = <&dmaclk 0>;
1096                 };
1097         };
1098 };