arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright Altera Corporation (C) 2015. All rights reserved.
   4  */
   5
   6 /dts-v1/;
   7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/clock/stratix10-clock.h>
  10
  11 / {
  12         compatible = "altr,socfpga-stratix10";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         reserved-memory {
  17                 #address-cells = <2>;
  18                 #size-cells = <2>;
  19                 ranges;
  20
  21                 service_reserved: svcbuffer@0 {
  22                         compatible = "shared-dma-pool";
  23                         reg = <0x0 0x0 0x0 0x1000000>;
  24                         alignment = <0x1000>;
  25                         no-map;
  26                 };
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu0: cpu@0 {
  34                         compatible = "arm,cortex-a53";
  35                         device_type = "cpu";
  36                         enable-method = "psci";
  37                         reg = <0x0>;
  38                 };
  39
  40                 cpu1: cpu@1 {
  41                         compatible = "arm,cortex-a53";
  42                         device_type = "cpu";
  43                         enable-method = "psci";
  44                         reg = <0x1>;
  45                 };
  46
  47                 cpu2: cpu@2 {
  48                         compatible = "arm,cortex-a53";
  49                         device_type = "cpu";
  50                         enable-method = "psci";
  51                         reg = <0x2>;
  52                 };
  53
  54                 cpu3: cpu@3 {
  55                         compatible = "arm,cortex-a53";
  56                         device_type = "cpu";
  57                         enable-method = "psci";
  58                         reg = <0x3>;
  59                 };
  60         };
  61
  62         pmu {
  63                 compatible = "arm,armv8-pmuv3";
  64                 interrupts = <0 120 8>,
  65                              <0 121 8>,
  66                              <0 122 8>,
  67                              <0 123 8>;
  68                 interrupt-affinity = <&cpu0>,
  69                                      <&cpu1>,
  70                                      <&cpu2>,
  71                                      <&cpu3>;
  72                 interrupt-parent = <&intc>;
  73         };
  74
  75         psci {
  76                 compatible = "arm,psci-0.2";
  77                 method = "smc";
  78         };
  79
  80         intc: intc@fffc1000 {
  81                 compatible = "arm,gic-400", "arm,cortex-a15-gic";
  82                 #interrupt-cells = <3>;
  83                 interrupt-controller;
  84                 reg = <0x0 0xfffc1000 0x0 0x1000>,
  85                       <0x0 0xfffc2000 0x0 0x2000>,
  86                       <0x0 0xfffc4000 0x0 0x2000>,
  87                       <0x0 0xfffc6000 0x0 0x2000>;
  88         };
  89
  90         soc {
  91                 #address-cells = <1>;
  92                 #size-cells = <1>;
  93                 compatible = "simple-bus";
  94                 device_type = "soc";
  95                 interrupt-parent = <&intc>;
  96                 ranges = <0 0 0 0xffffffff>;
  97
  98                 base_fpga_region {
  99                         #address-cells = <0x1>;
 100                         #size-cells = <0x1>;
 101
 102                         compatible = "fpga-region";
 103                         fpga-mgr = <&fpga_mgr>;
 104                 };
 105
 106                 clkmgr: clock-controller@ffd10000 {
 107                         compatible = "intel,stratix10-clkmgr";
 108                         reg = <0xffd10000 0x1000>;
 109                         #clock-cells = <1>;
 110                 };
 111
 112                 clocks {
 113                         cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
 114                                 #clock-cells = <0>;
 115                                 compatible = "fixed-clock";
 116                         };
 117
 118                         cb_intosc_ls_clk: cb-intosc-ls-clk {
 119                                 #clock-cells = <0>;
 120                                 compatible = "fixed-clock";
 121                         };
 122
 123                         f2s_free_clk: f2s-free-clk {
 124                                 #clock-cells = <0>;
 125                                 compatible = "fixed-clock";
 126                         };
 127
 128                         osc1: osc1 {
 129                                 #clock-cells = <0>;
 130                                 compatible = "fixed-clock";
 131                         };
 132
 133                         qspi_clk: qspi-clk {
 134                                 #clock-cells = <0>;
 135                                 compatible = "fixed-clock";
 136                                 clock-frequency = <200000000>;
 137                         };
 138                 };
 139
 140                 gmac0: ethernet@ff800000 {
 141                         compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
 142                         reg = <0xff800000 0x2000>;
 143                         interrupts = <0 90 4>;
 144                         interrupt-names = "macirq";
 145                         mac-address = [00 00 00 00 00 00];
 146                         resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
 147                         reset-names = "stmmaceth", "stmmaceth-ocp";
 148                         clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
 149                         clock-names = "stmmaceth";
 150                         tx-fifo-depth = <16384>;
 151                         rx-fifo-depth = <16384>;
 152                         snps,multicast-filter-bins = <256>;
 153                         iommus = <&smmu 1>;
 154                         altr,sysmgr-syscon = <&sysmgr 0x44 0>;
 155                         status = "disabled";
 156                 };
 157
 158                 gmac1: ethernet@ff802000 {
 159                         compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
 160                         reg = <0xff802000 0x2000>;
 161                         interrupts = <0 91 4>;
 162                         interrupt-names = "macirq";
 163                         mac-address = [00 00 00 00 00 00];
 164                         resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
 165                         reset-names = "stmmaceth", "stmmaceth-ocp";
 166                         clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
 167                         clock-names = "stmmaceth";
 168                         tx-fifo-depth = <16384>;
 169                         rx-fifo-depth = <16384>;
 170                         snps,multicast-filter-bins = <256>;
 171                         iommus = <&smmu 2>;
 172                         altr,sysmgr-syscon = <&sysmgr 0x48 8>;
 173                         status = "disabled";
 174                 };
 175
 176                 gmac2: ethernet@ff804000 {
 177                         compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
 178                         reg = <0xff804000 0x2000>;
 179                         interrupts = <0 92 4>;
 180                         interrupt-names = "macirq";
 181                         mac-address = [00 00 00 00 00 00];
 182                         resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
 183                         reset-names = "stmmaceth", "stmmaceth-ocp";
 184                         clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
 185                         clock-names = "stmmaceth";
 186                         tx-fifo-depth = <16384>;
 187                         rx-fifo-depth = <16384>;
 188                         snps,multicast-filter-bins = <256>;
 189                         iommus = <&smmu 3>;
 190                         altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
 191                         status = "disabled";
 192                 };
 193
 194                 gpio0: gpio@ffc03200 {
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                         compatible = "snps,dw-apb-gpio";
 198                         reg = <0xffc03200 0x100>;
 199                         resets = <&rst GPIO0_RESET>;
 200                         status = "disabled";
 201
 202                         porta: gpio-controller@0 {
 203                                 compatible = "snps,dw-apb-gpio-port";
 204                                 gpio-controller;
 205                                 #gpio-cells = <2>;
 206                                 snps,nr-gpios = <24>;
 207                                 reg = <0>;
 208                                 interrupt-controller;
 209                                 #interrupt-cells = <2>;
 210                                 interrupts = <0 110 4>;
 211                         };
 212                 };
 213
 214                 gpio1: gpio@ffc03300 {
 215                         #address-cells = <1>;
 216                         #size-cells = <0>;
 217                         compatible = "snps,dw-apb-gpio";
 218                         reg = <0xffc03300 0x100>;
 219                         resets = <&rst GPIO1_RESET>;
 220                         status = "disabled";
 221
 222                         portb: gpio-controller@0 {
 223                                 compatible = "snps,dw-apb-gpio-port";
 224                                 gpio-controller;
 225                                 #gpio-cells = <2>;
 226                                 snps,nr-gpios = <24>;
 227                                 reg = <0>;
 228                                 interrupt-controller;
 229                                 #interrupt-cells = <2>;
 230                                 interrupts = <0 111 4>;
 231                         };
 232                 };
 233
 234                 i2c0: i2c@ffc02800 {
 235                         #address-cells = <1>;
 236                         #size-cells = <0>;
 237                         compatible = "snps,designware-i2c";
 238                         reg = <0xffc02800 0x100>;
 239                         interrupts = <0 103 4>;
 240                         resets = <&rst I2C0_RESET>;
 241                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 242                         status = "disabled";
 243                 };
 244
 245                 i2c1: i2c@ffc02900 {
 246                         #address-cells = <1>;
 247                         #size-cells = <0>;
 248                         compatible = "snps,designware-i2c";
 249                         reg = <0xffc02900 0x100>;
 250                         interrupts = <0 104 4>;
 251                         resets = <&rst I2C1_RESET>;
 252                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 253                         status = "disabled";
 254                 };
 255
 256                 i2c2: i2c@ffc02a00 {
 257                         #address-cells = <1>;
 258                         #size-cells = <0>;
 259                         compatible = "snps,designware-i2c";
 260                         reg = <0xffc02a00 0x100>;
 261                         interrupts = <0 105 4>;
 262                         resets = <&rst I2C2_RESET>;
 263                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 264                         status = "disabled";
 265                 };
 266
 267                 i2c3: i2c@ffc02b00 {
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270                         compatible = "snps,designware-i2c";
 271                         reg = <0xffc02b00 0x100>;
 272                         interrupts = <0 106 4>;
 273                         resets = <&rst I2C3_RESET>;
 274                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 275                         status = "disabled";
 276                 };
 277
 278                 i2c4: i2c@ffc02c00 {
 279                         #address-cells = <1>;
 280                         #size-cells = <0>;
 281                         compatible = "snps,designware-i2c";
 282                         reg = <0xffc02c00 0x100>;
 283                         interrupts = <0 107 4>;
 284                         resets = <&rst I2C4_RESET>;
 285                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 286                         status = "disabled";
 287                 };
 288
 289                 mmc: dwmmc0@ff808000 {
 290                         #address-cells = <1>;
 291                         #size-cells = <0>;
 292                         compatible = "altr,socfpga-dw-mshc";
 293                         reg = <0xff808000 0x1000>;
 294                         interrupts = <0 96 4>;
 295                         fifo-depth = <0x400>;
 296                         resets = <&rst SDMMC_RESET>;
 297                         reset-names = "reset";
 298                         clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
 299                                  <&clkmgr STRATIX10_SDMMC_CLK>;
 300                         clock-names = "biu", "ciu";
 301                         iommus = <&smmu 5>;
 302                         status = "disabled";
 303                 };
 304
 305                 nand: nand@ffb90000 {
 306                         #address-cells = <1>;
 307                         #size-cells = <0>;
 308                         compatible = "altr,socfpga-denali-nand";
 309                         reg = <0xffb90000 0x10000>,
 310                               <0xffb80000 0x1000>;
 311                         reg-names = "nand_data", "denali_reg";
 312                         interrupts = <0 97 4>;
 313                         clocks = <&clkmgr STRATIX10_NAND_CLK>,
 314                                  <&clkmgr STRATIX10_NAND_X_CLK>,
 315                                  <&clkmgr STRATIX10_NAND_ECC_CLK>;
 316                         clock-names = "nand", "nand_x", "ecc";
 317                         resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
 318                         status = "disabled";
 319                 };
 320
 321                 ocram: sram@ffe00000 {
 322                         compatible = "mmio-sram";
 323                         reg = <0xffe00000 0x100000>;
 324                 };
 325
 326                 pdma: pdma@ffda0000 {
 327                         compatible = "arm,pl330", "arm,primecell";
 328                         reg = <0xffda0000 0x1000>;
 329                         interrupts = <0 81 4>,
 330                                      <0 82 4>,
 331                                      <0 83 4>,
 332                                      <0 84 4>,
 333                                      <0 85 4>,
 334                                      <0 86 4>,
 335                                      <0 87 4>,
 336                                      <0 88 4>,
 337                                      <0 89 4>;
 338                         #dma-cells = <1>;
 339                         #dma-channels = <8>;
 340                         #dma-requests = <32>;
 341                         clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
 342                         clock-names = "apb_pclk";
 343                         resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
 344                         reset-names = "dma", "dma-ocp";
 345                 };
 346
 347                 rst: rstmgr@ffd11000 {
 348                         #reset-cells = <1>;
 349                         compatible = "altr,stratix10-rst-mgr";
 350                         reg = <0xffd11000 0x1000>;
 351                 };
 352
 353                 smmu: iommu@fa000000 {
 354                         compatible = "arm,mmu-500", "arm,smmu-v2";
 355                         reg = <0xfa000000 0x40000>;
 356                         #global-interrupts = <2>;
 357                         #iommu-cells = <1>;
 358                         clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
 359                         clock-names = "iommu";
 360                         interrupt-parent = <&intc>;
 361                         interrupts = <0 128 4>, /* Global Secure Fault */
 362                                 <0 129 4>, /* Global Non-secure Fault */
 363                                 /* Non-secure Context Interrupts (32) */
 364                                 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
 365                                 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
 366                                 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
 367                                 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
 368                                 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
 369                                 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
 370                                 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
 371                                 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
 372                         stream-match-mask = <0x7ff0>;
 373                         status = "disabled";
 374                 };
 375
 376                 spi0: spi@ffda4000 {
 377                         compatible = "snps,dw-apb-ssi";
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                         reg = <0xffda4000 0x1000>;
 381                         interrupts = <0 99 4>;
 382                         resets = <&rst SPIM0_RESET>;
 383                         reg-io-width = <4>;
 384                         num-cs = <4>;
 385                         clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
 386                         status = "disabled";
 387                 };
 388
 389                 spi1: spi@ffda5000 {
 390                         compatible = "snps,dw-apb-ssi";
 391                         #address-cells = <1>;
 392                         #size-cells = <0>;
 393                         reg = <0xffda5000 0x1000>;
 394                         interrupts = <0 100 4>;
 395                         resets = <&rst SPIM1_RESET>;
 396                         reg-io-width = <4>;
 397                         num-cs = <4>;
 398                         clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
 399                         status = "disabled";
 400                 };
 401
 402                 sysmgr: sysmgr@ffd12000 {
 403                         compatible = "altr,sys-mgr-s10","altr,sys-mgr";
 404                         reg = <0xffd12000 0x228>;
 405                 };
 406
 407                 /* Local timer */
 408                 timer {
 409                         compatible = "arm,armv8-timer";
 410                         interrupts = <1 13 0xf08>,
 411                                      <1 14 0xf08>,
 412                                      <1 11 0xf08>,
 413                                      <1 10 0xf08>;
 414                 };
 415
 416                 timer0: timer0@ffc03000 {
 417                         compatible = "snps,dw-apb-timer";
 418                         interrupts = <0 113 4>;
 419                         reg = <0xffc03000 0x100>;
 420                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 421                         clock-names = "timer";
 422                 };
 423
 424                 timer1: timer1@ffc03100 {
 425                         compatible = "snps,dw-apb-timer";
 426                         interrupts = <0 114 4>;
 427                         reg = <0xffc03100 0x100>;
 428                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 429                         clock-names = "timer";
 430                 };
 431
 432                 timer2: timer2@ffd00000 {
 433                         compatible = "snps,dw-apb-timer";
 434                         interrupts = <0 115 4>;
 435                         reg = <0xffd00000 0x100>;
 436                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 437                         clock-names = "timer";
 438                 };
 439
 440                 timer3: timer3@ffd00100 {
 441                         compatible = "snps,dw-apb-timer";
 442                         interrupts = <0 116 4>;
 443                         reg = <0xffd00100 0x100>;
 444                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 445                         clock-names = "timer";
 446                 };
 447
 448                 uart0: serial0@ffc02000 {
 449                         compatible = "snps,dw-apb-uart";
 450                         reg = <0xffc02000 0x100>;
 451                         interrupts = <0 108 4>;
 452                         reg-shift = <2>;
 453                         reg-io-width = <4>;
 454                         resets = <&rst UART0_RESET>;
 455                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 456                         status = "disabled";
 457                 };
 458
 459                 uart1: serial1@ffc02100 {
 460                         compatible = "snps,dw-apb-uart";
 461                         reg = <0xffc02100 0x100>;
 462                         interrupts = <0 109 4>;
 463                         reg-shift = <2>;
 464                         reg-io-width = <4>;
 465                         resets = <&rst UART1_RESET>;
 466                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 467                         status = "disabled";
 468                 };
 469
 470                 usbphy0: usbphy@0 {
 471                         #phy-cells = <0>;
 472                         compatible = "usb-nop-xceiv";
 473                         status = "okay";
 474                 };
 475
 476                 usb0: usb@ffb00000 {
 477                         compatible = "snps,dwc2";
 478                         reg = <0xffb00000 0x40000>;
 479                         interrupts = <0 93 4>;
 480                         phys = <&usbphy0>;
 481                         phy-names = "usb2-phy";
 482                         resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
 483                         reset-names = "dwc2", "dwc2-ecc";
 484                         clocks = <&clkmgr STRATIX10_USB_CLK>;
 485                         iommus = <&smmu 6>;
 486                         status = "disabled";
 487                 };
 488
 489                 usb1: usb@ffb40000 {
 490                         compatible = "snps,dwc2";
 491                         reg = <0xffb40000 0x40000>;
 492                         interrupts = <0 94 4>;
 493                         phys = <&usbphy0>;
 494                         phy-names = "usb2-phy";
 495                         resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
 496                         reset-names = "dwc2", "dwc2-ecc";
 497                         clocks = <&clkmgr STRATIX10_USB_CLK>;
 498                         iommus = <&smmu 7>;
 499                         status = "disabled";
 500                 };
 501
 502                 watchdog0: watchdog@ffd00200 {
 503                         compatible = "snps,dw-wdt";
 504                         reg = <0xffd00200 0x100>;
 505                         interrupts = <0 117 4>;
 506                         resets = <&rst WATCHDOG0_RESET>;
 507                         clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
 508                         status = "disabled";
 509                 };
 510
 511                 watchdog1: watchdog@ffd00300 {
 512                         compatible = "snps,dw-wdt";
 513                         reg = <0xffd00300 0x100>;
 514                         interrupts = <0 118 4>;
 515                         resets = <&rst WATCHDOG1_RESET>;
 516                         clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
 517                         status = "disabled";
 518                 };
 519
 520                 watchdog2: watchdog@ffd00400 {
 521                         compatible = "snps,dw-wdt";
 522                         reg = <0xffd00400 0x100>;
 523                         interrupts = <0 125 4>;
 524                         resets = <&rst WATCHDOG2_RESET>;
 525                         clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
 526                         status = "disabled";
 527                 };
 528
 529                 watchdog3: watchdog@ffd00500 {
 530                         compatible = "snps,dw-wdt";
 531                         reg = <0xffd00500 0x100>;
 532                         interrupts = <0 126 4>;
 533                         resets = <&rst WATCHDOG3_RESET>;
 534                         clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
 535                         status = "disabled";
 536                 };
 537
 538                 sdr: sdr@f8011100 {
 539                         compatible = "altr,sdr-ctl", "syscon";
 540                         reg = <0xf8011100 0xc0>;
 541                 };
 542
 543                 eccmgr {
 544                         compatible = "altr,socfpga-s10-ecc-manager",
 545                                      "altr,socfpga-a10-ecc-manager";
 546                         altr,sysmgr-syscon = <&sysmgr>;
 547                         #address-cells = <1>;
 548                         #size-cells = <1>;
 549                         interrupts = <0 15 4>;
 550                         interrupt-controller;
 551                         #interrupt-cells = <2>;
 552                         ranges;
 553
 554                         sdramedac {
 555                                 compatible = "altr,sdram-edac-s10";
 556                                 altr,sdr-syscon = <&sdr>;
 557                                 interrupts = <16 4>;
 558                         };
 559
 560                         ocram-ecc@ff8cc000 {
 561                                 compatible = "altr,socfpga-s10-ocram-ecc",
 562                                              "altr,socfpga-a10-ocram-ecc";
 563                                 reg = <0xff8cc000 0x100>;
 564                                 altr,ecc-parent = <&ocram>;
 565                                 interrupts = <1 4>;
 566                         };
 567
 568                         usb0-ecc@ff8c4000 {
 569                                 compatible = "altr,socfpga-s10-usb-ecc",
 570                                              "altr,socfpga-usb-ecc";
 571                                 reg = <0xff8c4000 0x100>;
 572                                 altr,ecc-parent = <&usb0>;
 573                                 interrupts = <2 4>;
 574                         };
 575
 576                         emac0-rx-ecc@ff8c0000 {
 577                                 compatible = "altr,socfpga-s10-eth-mac-ecc",
 578                                              "altr,socfpga-eth-mac-ecc";
 579                                 reg = <0xff8c0000 0x100>;
 580                                 altr,ecc-parent = <&gmac0>;
 581                                 interrupts = <4 4>;
 582                         };
 583
 584                         emac0-tx-ecc@ff8c0400 {
 585                                 compatible = "altr,socfpga-s10-eth-mac-ecc",
 586                                              "altr,socfpga-eth-mac-ecc";
 587                                 reg = <0xff8c0400 0x100>;
 588                                 altr,ecc-parent = <&gmac0>;
 589                                 interrupts = <5 4>;
 590                         };
 591
 592                 };
 593
 594                 qspi: spi@ff8d2000 {
 595                         compatible = "cdns,qspi-nor";
 596                         #address-cells = <1>;
 597                         #size-cells = <0>;
 598                         reg = <0xff8d2000 0x100>,
 599                               <0xff900000 0x100000>;
 600                         interrupts = <0 3 4>;
 601                         cdns,fifo-depth = <128>;
 602                         cdns,fifo-width = <4>;
 603                         cdns,trigger-address = <0x00000000>;
 604                         clocks = <&qspi_clk>;
 605
 606                         status = "disabled";
 607                 };
 608
 609                 firmware {
 610                         svc {
 611                                 compatible = "intel,stratix10-svc";
 612                                 method = "smc";
 613                                 memory-region = <&service_reserved>;
 614
 615                                 fpga_mgr: fpga-mgr {
 616                                         compatible = "intel,stratix10-soc-fpga-mgr";
 617                                 };
 618                         };
 619                 };
 620         };
 621 };