arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi

   1 /*
   2  * Copyright Altera Corporation (C) 2015. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 /dts-v1/;
  18 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
  19 #include <dt-bindings/gpio/gpio.h>
  20 #include <dt-bindings/clock/stratix10-clock.h>
  21
  22 / {
  23         compatible = "altr,socfpga-stratix10";
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         reserved-memory {
  28                 #address-cells = <2>;
  29                 #size-cells = <2>;
  30                 ranges;
  31
  32                 service_reserved: svcbuffer@0 {
  33                         compatible = "shared-dma-pool";
  34                         reg = <0x0 0x0 0x0 0x1000000>;
  35                         alignment = <0x1000>;
  36                         no-map;
  37                 };
  38         };
  39
  40         cpus {
  41                 #address-cells = <1>;
  42                 #size-cells = <0>;
  43
  44                 cpu0: cpu@0 {
  45                         compatible = "arm,cortex-a53";
  46                         device_type = "cpu";
  47                         enable-method = "psci";
  48                         reg = <0x0>;
  49                 };
  50
  51                 cpu1: cpu@1 {
  52                         compatible = "arm,cortex-a53";
  53                         device_type = "cpu";
  54                         enable-method = "psci";
  55                         reg = <0x1>;
  56                 };
  57
  58                 cpu2: cpu@2 {
  59                         compatible = "arm,cortex-a53";
  60                         device_type = "cpu";
  61                         enable-method = "psci";
  62                         reg = <0x2>;
  63                 };
  64
  65                 cpu3: cpu@3 {
  66                         compatible = "arm,cortex-a53";
  67                         device_type = "cpu";
  68                         enable-method = "psci";
  69                         reg = <0x3>;
  70                 };
  71         };
  72
  73         pmu {
  74                 compatible = "arm,armv8-pmuv3";
  75                 interrupts = <0 120 8>,
  76                              <0 121 8>,
  77                              <0 122 8>,
  78                              <0 123 8>;
  79                 interrupt-affinity = <&cpu0>,
  80                                      <&cpu1>,
  81                                      <&cpu2>,
  82                                      <&cpu3>;
  83                 interrupt-parent = <&intc>;
  84         };
  85
  86         psci {
  87                 compatible = "arm,psci-0.2";
  88                 method = "smc";
  89         };
  90
  91         intc: intc@fffc1000 {
  92                 compatible = "arm,gic-400", "arm,cortex-a15-gic";
  93                 #interrupt-cells = <3>;
  94                 interrupt-controller;
  95                 reg = <0x0 0xfffc1000 0x0 0x1000>,
  96                       <0x0 0xfffc2000 0x0 0x2000>,
  97                       <0x0 0xfffc4000 0x0 0x2000>,
  98                       <0x0 0xfffc6000 0x0 0x2000>;
  99         };
 100
 101         soc {
 102                 #address-cells = <1>;
 103                 #size-cells = <1>;
 104                 compatible = "simple-bus";
 105                 device_type = "soc";
 106                 interrupt-parent = <&intc>;
 107                 ranges = <0 0 0 0xffffffff>;
 108
 109                 base_fpga_region {
 110                         #address-cells = <0x1>;
 111                         #size-cells = <0x1>;
 112
 113                         compatible = "fpga-region";
 114                         fpga-mgr = <&fpga_mgr>;
 115                 };
 116
 117                 clkmgr: clock-controller@ffd10000 {
 118                         compatible = "intel,stratix10-clkmgr";
 119                         reg = <0xffd10000 0x1000>;
 120                         #clock-cells = <1>;
 121                 };
 122
 123                 clocks {
 124                         cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
 125                                 #clock-cells = <0>;
 126                                 compatible = "fixed-clock";
 127                         };
 128
 129                         cb_intosc_ls_clk: cb-intosc-ls-clk {
 130                                 #clock-cells = <0>;
 131                                 compatible = "fixed-clock";
 132                         };
 133
 134                         f2s_free_clk: f2s-free-clk {
 135                                 #clock-cells = <0>;
 136                                 compatible = "fixed-clock";
 137                         };
 138
 139                         osc1: osc1 {
 140                                 #clock-cells = <0>;
 141                                 compatible = "fixed-clock";
 142                         };
 143
 144                         qspi_clk: qspi-clk {
 145                                 #clock-cells = <0>;
 146                                 compatible = "fixed-clock";
 147                                 clock-frequency = <200000000>;
 148                         };
 149                 };
 150
 151                 gmac0: ethernet@ff800000 {
 152                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
 153                         reg = <0xff800000 0x2000>;
 154                         interrupts = <0 90 4>;
 155                         interrupt-names = "macirq";
 156                         mac-address = [00 00 00 00 00 00];
 157                         resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
 158                         reset-names = "stmmaceth", "stmmaceth-ocp";
 159                         clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
 160                         clock-names = "stmmaceth";
 161                         tx-fifo-depth = <16384>;
 162                         rx-fifo-depth = <16384>;
 163                         snps,multicast-filter-bins = <256>;
 164                         iommus = <&smmu 1>;
 165                         status = "disabled";
 166                 };
 167
 168                 gmac1: ethernet@ff802000 {
 169                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
 170                         reg = <0xff802000 0x2000>;
 171                         interrupts = <0 91 4>;
 172                         interrupt-names = "macirq";
 173                         mac-address = [00 00 00 00 00 00];
 174                         resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
 175                         reset-names = "stmmaceth", "stmmaceth-ocp";
 176                         clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
 177                         clock-names = "stmmaceth";
 178                         tx-fifo-depth = <16384>;
 179                         rx-fifo-depth = <16384>;
 180                         snps,multicast-filter-bins = <256>;
 181                         iommus = <&smmu 2>;
 182                         status = "disabled";
 183                 };
 184
 185                 gmac2: ethernet@ff804000 {
 186                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
 187                         reg = <0xff804000 0x2000>;
 188                         interrupts = <0 92 4>;
 189                         interrupt-names = "macirq";
 190                         mac-address = [00 00 00 00 00 00];
 191                         resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
 192                         reset-names = "stmmaceth", "stmmaceth-ocp";
 193                         clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
 194                         clock-names = "stmmaceth";
 195                         tx-fifo-depth = <16384>;
 196                         rx-fifo-depth = <16384>;
 197                         snps,multicast-filter-bins = <256>;
 198                         iommus = <&smmu 3>;
 199                         status = "disabled";
 200                 };
 201
 202                 gpio0: gpio@ffc03200 {
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205                         compatible = "snps,dw-apb-gpio";
 206                         reg = <0xffc03200 0x100>;
 207                         resets = <&rst GPIO0_RESET>;
 208                         status = "disabled";
 209
 210                         porta: gpio-controller@0 {
 211                                 compatible = "snps,dw-apb-gpio-port";
 212                                 gpio-controller;
 213                                 #gpio-cells = <2>;
 214                                 snps,nr-gpios = <24>;
 215                                 reg = <0>;
 216                                 interrupt-controller;
 217                                 #interrupt-cells = <2>;
 218                                 interrupts = <0 110 4>;
 219                         };
 220                 };
 221
 222                 gpio1: gpio@ffc03300 {
 223                         #address-cells = <1>;
 224                         #size-cells = <0>;
 225                         compatible = "snps,dw-apb-gpio";
 226                         reg = <0xffc03300 0x100>;
 227                         resets = <&rst GPIO1_RESET>;
 228                         status = "disabled";
 229
 230                         portb: gpio-controller@0 {
 231                                 compatible = "snps,dw-apb-gpio-port";
 232                                 gpio-controller;
 233                                 #gpio-cells = <2>;
 234                                 snps,nr-gpios = <24>;
 235                                 reg = <0>;
 236                                 interrupt-controller;
 237                                 #interrupt-cells = <2>;
 238                                 interrupts = <0 111 4>;
 239                         };
 240                 };
 241
 242                 i2c0: i2c@ffc02800 {
 243                         #address-cells = <1>;
 244                         #size-cells = <0>;
 245                         compatible = "snps,designware-i2c";
 246                         reg = <0xffc02800 0x100>;
 247                         interrupts = <0 103 4>;
 248                         resets = <&rst I2C0_RESET>;
 249                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 250                         status = "disabled";
 251                 };
 252
 253                 i2c1: i2c@ffc02900 {
 254                         #address-cells = <1>;
 255                         #size-cells = <0>;
 256                         compatible = "snps,designware-i2c";
 257                         reg = <0xffc02900 0x100>;
 258                         interrupts = <0 104 4>;
 259                         resets = <&rst I2C1_RESET>;
 260                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 261                         status = "disabled";
 262                 };
 263
 264                 i2c2: i2c@ffc02a00 {
 265                         #address-cells = <1>;
 266                         #size-cells = <0>;
 267                         compatible = "snps,designware-i2c";
 268                         reg = <0xffc02a00 0x100>;
 269                         interrupts = <0 105 4>;
 270                         resets = <&rst I2C2_RESET>;
 271                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 272                         status = "disabled";
 273                 };
 274
 275                 i2c3: i2c@ffc02b00 {
 276                         #address-cells = <1>;
 277                         #size-cells = <0>;
 278                         compatible = "snps,designware-i2c";
 279                         reg = <0xffc02b00 0x100>;
 280                         interrupts = <0 106 4>;
 281                         resets = <&rst I2C3_RESET>;
 282                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 283                         status = "disabled";
 284                 };
 285
 286                 i2c4: i2c@ffc02c00 {
 287                         #address-cells = <1>;
 288                         #size-cells = <0>;
 289                         compatible = "snps,designware-i2c";
 290                         reg = <0xffc02c00 0x100>;
 291                         interrupts = <0 107 4>;
 292                         resets = <&rst I2C4_RESET>;
 293                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 294                         status = "disabled";
 295                 };
 296
 297                 mmc: dwmmc0@ff808000 {
 298                         #address-cells = <1>;
 299                         #size-cells = <0>;
 300                         compatible = "altr,socfpga-dw-mshc";
 301                         reg = <0xff808000 0x1000>;
 302                         interrupts = <0 96 4>;
 303                         fifo-depth = <0x400>;
 304                         resets = <&rst SDMMC_RESET>;
 305                         reset-names = "reset";
 306                         clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
 307                                  <&clkmgr STRATIX10_SDMMC_CLK>;
 308                         clock-names = "biu", "ciu";
 309                         iommus = <&smmu 5>;
 310                         status = "disabled";
 311                 };
 312
 313                 ocram: sram@ffe00000 {
 314                         compatible = "mmio-sram";
 315                         reg = <0xffe00000 0x100000>;
 316                 };
 317
 318                 pdma: pdma@ffda0000 {
 319                         compatible = "arm,pl330", "arm,primecell";
 320                         reg = <0xffda0000 0x1000>;
 321                         interrupts = <0 81 4>,
 322                                      <0 82 4>,
 323                                      <0 83 4>,
 324                                      <0 84 4>,
 325                                      <0 85 4>,
 326                                      <0 86 4>,
 327                                      <0 87 4>,
 328                                      <0 88 4>,
 329                                      <0 89 4>;
 330                         #dma-cells = <1>;
 331                         #dma-channels = <8>;
 332                         #dma-requests = <32>;
 333                         clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
 334                         clock-names = "apb_pclk";
 335                 };
 336
 337                 rst: rstmgr@ffd11000 {
 338                         #reset-cells = <1>;
 339                         compatible = "altr,stratix10-rst-mgr";
 340                         reg = <0xffd11000 0x1000>;
 341                 };
 342
 343                 smmu: iommu@fa000000 {
 344                         compatible = "arm,mmu-500", "arm,smmu-v2";
 345                         reg = <0xfa000000 0x40000>;
 346                         #global-interrupts = <2>;
 347                         #iommu-cells = <1>;
 348                         clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
 349                         clock-names = "iommu";
 350                         interrupt-parent = <&intc>;
 351                         interrupts = <0 128 4>, /* Global Secure Fault */
 352                                 <0 129 4>, /* Global Non-secure Fault */
 353                                 /* Non-secure Context Interrupts (32) */
 354                                 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
 355                                 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
 356                                 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
 357                                 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
 358                                 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
 359                                 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
 360                                 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
 361                                 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
 362                         stream-match-mask = <0x7ff0>;
 363                         status = "disabled";
 364                 };
 365
 366                 spi0: spi@ffda4000 {
 367                         compatible = "snps,dw-apb-ssi";
 368                         #address-cells = <1>;
 369                         #size-cells = <0>;
 370                         reg = <0xffda4000 0x1000>;
 371                         interrupts = <0 99 4>;
 372                         resets = <&rst SPIM0_RESET>;
 373                         reg-io-width = <4>;
 374                         num-cs = <4>;
 375                         clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
 376                         status = "disabled";
 377                 };
 378
 379                 spi1: spi@ffda5000 {
 380                         compatible = "snps,dw-apb-ssi";
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                         reg = <0xffda5000 0x1000>;
 384                         interrupts = <0 100 4>;
 385                         resets = <&rst SPIM1_RESET>;
 386                         reg-io-width = <4>;
 387                         num-cs = <4>;
 388                         clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
 389                         status = "disabled";
 390                 };
 391
 392                 sysmgr: sysmgr@ffd12000 {
 393                         compatible = "altr,sys-mgr", "syscon";
 394                         reg = <0xffd12000 0x228>;
 395                 };
 396
 397                 /* Local timer */
 398                 timer {
 399                         compatible = "arm,armv8-timer";
 400                         interrupts = <1 13 0xf08>,
 401                                      <1 14 0xf08>,
 402                                      <1 11 0xf08>,
 403                                      <1 10 0xf08>;
 404                 };
 405
 406                 timer0: timer0@ffc03000 {
 407                         compatible = "snps,dw-apb-timer";
 408                         interrupts = <0 113 4>;
 409                         reg = <0xffc03000 0x100>;
 410                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 411                         clock-names = "timer";
 412                 };
 413
 414                 timer1: timer1@ffc03100 {
 415                         compatible = "snps,dw-apb-timer";
 416                         interrupts = <0 114 4>;
 417                         reg = <0xffc03100 0x100>;
 418                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 419                         clock-names = "timer";
 420                 };
 421
 422                 timer2: timer2@ffd00000 {
 423                         compatible = "snps,dw-apb-timer";
 424                         interrupts = <0 115 4>;
 425                         reg = <0xffd00000 0x100>;
 426                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 427                         clock-names = "timer";
 428                 };
 429
 430                 timer3: timer3@ffd00100 {
 431                         compatible = "snps,dw-apb-timer";
 432                         interrupts = <0 116 4>;
 433                         reg = <0xffd00100 0x100>;
 434                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 435                         clock-names = "timer";
 436                 };
 437
 438                 uart0: serial0@ffc02000 {
 439                         compatible = "snps,dw-apb-uart";
 440                         reg = <0xffc02000 0x100>;
 441                         interrupts = <0 108 4>;
 442                         reg-shift = <2>;
 443                         reg-io-width = <4>;
 444                         resets = <&rst UART0_RESET>;
 445                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 446                         status = "disabled";
 447                 };
 448
 449                 uart1: serial1@ffc02100 {
 450                         compatible = "snps,dw-apb-uart";
 451                         reg = <0xffc02100 0x100>;
 452                         interrupts = <0 109 4>;
 453                         reg-shift = <2>;
 454                         reg-io-width = <4>;
 455                         resets = <&rst UART1_RESET>;
 456                         clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
 457                         status = "disabled";
 458                 };
 459
 460                 usbphy0: usbphy@0 {
 461                         #phy-cells = <0>;
 462                         compatible = "usb-nop-xceiv";
 463                         status = "okay";
 464                 };
 465
 466                 usb0: usb@ffb00000 {
 467                         compatible = "snps,dwc2";
 468                         reg = <0xffb00000 0x40000>;
 469                         interrupts = <0 93 4>;
 470                         phys = <&usbphy0>;
 471                         phy-names = "usb2-phy";
 472                         resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
 473                         reset-names = "dwc2", "dwc2-ecc";
 474                         clocks = <&clkmgr STRATIX10_USB_CLK>;
 475                         iommus = <&smmu 6>;
 476                         status = "disabled";
 477                 };
 478
 479                 usb1: usb@ffb40000 {
 480                         compatible = "snps,dwc2";
 481                         reg = <0xffb40000 0x40000>;
 482                         interrupts = <0 94 4>;
 483                         phys = <&usbphy0>;
 484                         phy-names = "usb2-phy";
 485                         resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
 486                         reset-names = "dwc2", "dwc2-ecc";
 487                         clocks = <&clkmgr STRATIX10_USB_CLK>;
 488                         iommus = <&smmu 7>;
 489                         status = "disabled";
 490                 };
 491
 492                 watchdog0: watchdog@ffd00200 {
 493                         compatible = "snps,dw-wdt";
 494                         reg = <0xffd00200 0x100>;
 495                         interrupts = <0 117 4>;
 496                         resets = <&rst WATCHDOG0_RESET>;
 497                         clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
 498                         status = "disabled";
 499                 };
 500
 501                 watchdog1: watchdog@ffd00300 {
 502                         compatible = "snps,dw-wdt";
 503                         reg = <0xffd00300 0x100>;
 504                         interrupts = <0 118 4>;
 505                         resets = <&rst WATCHDOG1_RESET>;
 506                         clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
 507                         status = "disabled";
 508                 };
 509
 510                 watchdog2: watchdog@ffd00400 {
 511                         compatible = "snps,dw-wdt";
 512                         reg = <0xffd00400 0x100>;
 513                         interrupts = <0 125 4>;
 514                         resets = <&rst WATCHDOG2_RESET>;
 515                         clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
 516                         status = "disabled";
 517                 };
 518
 519                 watchdog3: watchdog@ffd00500 {
 520                         compatible = "snps,dw-wdt";
 521                         reg = <0xffd00500 0x100>;
 522                         interrupts = <0 126 4>;
 523                         resets = <&rst WATCHDOG3_RESET>;
 524                         clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
 525                         status = "disabled";
 526                 };
 527
 528                 sdr: sdr@f8011100 {
 529                         compatible = "altr,sdr-ctl", "syscon";
 530                         reg = <0xf8011100 0xc0>;
 531                 };
 532
 533                 eccmgr {
 534                         compatible = "altr,socfpga-a10-ecc-manager";
 535                         altr,sysmgr-syscon = <&sysmgr>;
 536                         #address-cells = <1>;
 537                         #size-cells = <1>;
 538                         interrupts = <0 15 4>, <0 95 4>;
 539                         interrupt-controller;
 540                         #interrupt-cells = <2>;
 541                         ranges;
 542
 543                         sdramedac {
 544                                 compatible = "altr,sdram-edac-s10";
 545                                 altr,sdr-syscon = <&sdr>;
 546                                 interrupts = <16 4>, <48 4>;
 547                         };
 548
 549                         usb0-ecc@ff8c4000 {
 550                                 compatible = "altr,socfpga-usb-ecc";
 551                                 reg = <0xff8c4000 0x100>;
 552                                 altr,ecc-parent = <&usb0>;
 553                                 interrupts = <2 4>,
 554                                              <34 4>;
 555                         };
 556
 557                         emac0-rx-ecc@ff8c0000 {
 558                                 compatible = "altr,socfpga-eth-mac-ecc";
 559                                 reg = <0xff8c0000 0x100>;
 560                                 altr,ecc-parent = <&gmac0>;
 561                                 interrupts = <4 4>,
 562                                              <36 4>;
 563                         };
 564
 565                         emac0-tx-ecc@ff8c0400 {
 566                                 compatible = "altr,socfpga-eth-mac-ecc";
 567                                 reg = <0xff8c0400 0x100>;
 568                                 altr,ecc-parent = <&gmac0>;
 569                                 interrupts = <5 4>,
 570                                              <37 4>;
 571                         };
 572
 573                 };
 574
 575                 qspi: spi@ff8d2000 {
 576                         compatible = "cdns,qspi-nor";
 577                         #address-cells = <1>;
 578                         #size-cells = <0>;
 579                         reg = <0xff8d2000 0x100>,
 580                               <0xff900000 0x100000>;
 581                         interrupts = <0 3 4>;
 582                         cdns,fifo-depth = <128>;
 583                         cdns,fifo-width = <4>;
 584                         cdns,trigger-address = <0x00000000>;
 585                         clocks = <&qspi_clk>;
 586
 587                         status = "disabled";
 588                 };
 589
 590                 firmware {
 591                         svc {
 592                                 compatible = "intel,stratix10-svc";
 593                                 method = "smc";
 594                                 memory-region = <&service_reserved>;
 595
 596                                 fpga_mgr: fpga-mgr {
 597                                         compatible = "intel,stratix10-soc-fpga-mgr";
 598                                 };
 599                         };
 600                 };
 601         };
 602 };